Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

On Fri, May 25, 2018 at 10:14 AM, Rafael J. Wysocki wrote: > On Thu, May 24, 2018 at 2:28 PM, Dmitry Osipenko wrote: >> On 24.05.2018 11:01, Rafael J. Wysocki wrote: >>> On Thu, May 24, 2018 at 7:37 AM, Dmitry Osipenko wrote: On 24.05.2018 07:30, Viresh Kumar wrote: > On 23-05-18,

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

On 25.05.2018 11:36, Rafael J. Wysocki wrote: > On Fri, May 25, 2018 at 10:14 AM, Rafael J. Wysocki wrote: >> On Thu, May 24, 2018 at 2:28 PM, Dmitry Osipenko wrote: >>> On 24.05.2018 11:01, Rafael J. Wysocki wrote: On Thu, May 24, 2018 at 7:37 AM, Dmitry Osipenko wrote: > On

Re: [PATCH] swiotlb: Fix inversed DMA_ATTR_NO_WARN test

On 2018-05-25 10:41 AM, Christoph Hellwig wrote: > On Tue, May 22, 2018 at 03:13:58PM +0200, Christian König wrote: >> Am 02.05.2018 um 18:59 schrieb Michel Dänzer: >>> On 2018-05-02 06:21 PM, Christoph Hellwig wrote: On Wed, May 02, 2018 at 04:31:09PM +0200, Michel Dänzer wrote: >> No.

RE: [PATCH v6 0/7] vfio/type1: Add support for valid iova list management

Hi Alex, > -Original Message- > From: Alex Williamson [mailto:alex.william...@redhat.com] > Sent: Thursday, May 24, 2018 7:21 PM > To: Shameerali Kolothum Thodi > Cc: eric.au...@redhat.com; pmo...@linux.vnet.ibm.com; > k...@vger.kernel.org; linux-kernel@vger.kernel.org;

Re: [PATCH] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

On Fri, May 25, 2018 at 8:27 AM, George Cherian wrote: > Hi Prashanth, > > > On 05/25/2018 12:55 AM, Prakash, Prashanth wrote: >> >> Hi George, >> >> On 5/22/2018 5:42 AM, George Cherian wrote: >>> >>> Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides performance >>> feedback via set of

Re: [PATCH 1/2] nvme-pci: set nvmeq->cq_vector after alloc cq/sq

Thanks, applied to nvme-4.18.

Re: [PATCH V3] nvme-rdma: stop queue first before free it in config admin queue

Thanks, applied to nvme-4.18.

Re: [PATCH 2/2] ACPI: EC: Dispatch the EC GPE directly on s2idle wake

On Fri, May 25, 2018 at 10:08 AM, Rafael J. Wysocki wrote: > On Fri, May 25, 2018 at 8:49 AM, Ulf Hansson wrote: >> Rafael, >> >> On 18 May 2018 at 08:10, kbuild test robot wrote: >>> Hi Rafael, >>> >>> I love your patch! Yet something to improve: >>> >>> [auto build test ERROR on

Re: [PATCH v4 1/2] dt-bindings: input: Add Add Spreadtrum SC27xx vibrator documentation

On 19 May 2018 at 00:54, Rob Herring wrote: > On Thu, May 10, 2018 at 01:08:33PM +0800, Baolin Wang wrote: >> From: Xiaotong Lu >> >> This patch adds the binding documentation for Spreadtrum SC27xx series >> vibrator device. >> >> Signed-off-by: Xiaotong Lu >> Signed-off-by: Baolin Wang >> ---

RE: [alsa-devel] [RFC/RFT PATCH] ASoC: topology: Improve backwards compatibility with v4 topology files

> -Original Message- > From: alsa-devel-boun...@alsa-project.org [mailto:alsa-devel-bounces@alsa- > project.org] On Behalf Of Mark Brown > Sent: Thursday, May 24, 2018 11:12 PM > On Thu, May 24, 2018 at 07:55:06AM -0700, Guenter Roeck wrote: > > On Thu, May 24, 2018 at 7:18 AM Mark Brown

[PATCH v2 0/2] rtmutex wait_lock is irq safe

Since commit b4abf91047cf ("rtmutex: Make wait_lock irq safe") the rtmutex wait_lock is irq safe. Therefore the irqsave/restore in kernel/signal is no longer required (see Patch 2/2). During discussions about v1 of this patch, Eric Biederman noticed, that there is a no longer valid

[PATCH v2 2/2] signal: Remove no longer required irqsave/restore

Commit a841796f11c9 ("signal: align __lock_task_sighand() irq disabling and RCU") introduced a rcu read side critical section with interrupts disabled. The changelog suggested that a better long-term fix would be "to make rt_mutex_unlock() disable irqs when acquiring the rt_mutex structure's

[PATCH v2 1/2] rcu: Update documentation of rcu_read_unlock()

Since commit b4abf91047cf ("rtmutex: Make wait_lock irq safe") the explanation in rcu_read_unlock() documentation about irq unsafe rtmutex wait_lock is no longer valid. Remove it to prevent kernel developers reading the documentation to rely on it. Suggested-by: Eric W. Biederman Signed-off-by:

Re: [PATCH] mmc: sdhci-*: Don't emit error msg if sdhci_add_host() fails

On 25/05/18 10:15, Jisheng Zhang wrote: > I noticed below error msg with sdhci-pxav3 on some berlin platforms: > > [.] sdhci-pxav3 f7ab.sdhci failed to add host > > It is due to getting related vmmc or vqmmc regulator returns > -EPROBE_DEFER. It doesn't matter at all but it's confusing.

[ANNOUNCE] 4.4.132-rt149

Hello RT Folks! I'm pleased to announce the 4.4.132-rt149 stable release. This release is just an update to the new stable 4.4.132 version and no RT specific changes have been made. You can get this release via the git tree at:

[PATCH 3/3 v2] gspca_zc3xx: Enable short exposure times for OV7648

The 50Hz and 60Hz power line frequency settings disable short (1/120s and 1/100s) exposure times for banding filter (causing overexposed image near lamps). No flicker setting enables them (when banding filter is disabled and they're not used). Seems that the logic is just the wrong way around.

[PATCH 2/3 v2] gspca_zc3xx: Fix power line frequency settings for OV7648

Power line frequency settings for OV7648 sensor contain autogain and exposure commands, affecting unrelated controls. Remove them. Signed-off-by: Ondrej Zary --- drivers/media/usb/gspca/zc3xx.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/media/usb/gspca/zc3xx.c

Re: [PATCH] media: v4l2-ctrl: Add control for VP9 profile

On 17/05/18 11:53, Keiichi Watanabe wrote: > Add a new control V4L2_CID_MPEG_VIDEO_VP9_PROFILE for selecting desired > profile for VP9 encoder and querying for supported profiles by VP9 encoder > or decoder. > > An existing control V4L2_CID_MPEG_VIDEO_VPX_PROFILE cannot be > used for querying

[PATCH 1/3] gspca_zc3xx: Implement proper autogain and exposure control for OV7648

The ZS0211 internal autogain causes pumping and flickering with OV7648 sensor on 0ac8:307b webcam. Implement OV7648 autogain and exposure control and use that instead. Signed-off-by: Ondrej Zary --- drivers/media/usb/gspca/zc3xx.c | 42 + 1 file changed,

Re: [PATCH v6 2/6] dt-bindings: Add the rzn1-clocks.h file

Hi Michel, On Wed, May 23, 2018 at 10:17 AM, M P wrote: > On Wed, 23 May 2018 at 08:26, Geert Uytterhoeven > wrote: >> On Wed, May 23, 2018 at 8:44 AM, M P wrote: >> > On Tue, 22 May 2018 at 19:44, Geert Uytterhoeven >> > wrote: >> >> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet >> >>

[PATCH v10 3/5] arm64: dts: add ufs dts node

arm64: dts: add ufs node for Hisilicon. Signed-off-by: Li Wei --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 18 ++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index

[PATCH v10 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs

add ufs node document for Hisilicon. Signed-off-by: Li Wei --- Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 41 ++ .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 10 -- 2 files changed, 48 insertions(+), 3 deletions(-) create mode 100644

[PATCH v10 1/5] scsi: ufs: add Hisilicon ufs driver code

add Hisilicon ufs driver code. Signed-off-by: Li Wei Signed-off-by: Geng Jianfeng Signed-off-by: Zang Leigang Signed-off-by: Yu Jianfeng --- drivers/scsi/ufs/Kconfig| 9 + drivers/scsi/ufs/Makefile | 1 + drivers/scsi/ufs/ufs-hisi.c | 619

[PATCH v10 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC

This patchset adds driver support for UFS for Hi3660 SoC. It is verified on HiKey960 board. Li Wei (5): scsi: ufs: add Hisilicon ufs driver code dt-bindings: scsi: ufs: add document for hisi-ufs arm64: dts: add ufs dts node arm64: defconfig: enable configs for Hisilicon ufs arm64:

[PATCH v10 5/5] arm64: defconfig: enable f2fs and squashfs

Partitions in HiKey960 are formatted as f2fs and squashfs. f2fs is for userdata; squashfs is for system. Both partitions are required by Android. Signed-off-by: Li Wei Signed-off-by: Zhangfei Gao Signed-off-by: Guodong Xu --- arch/arm64/configs/defconfig | 8 1 file changed, 8

[PATCH v10 4/5] arm64: defconfig: enable configs for Hisilicon ufs

This enable configs for Hisilicon Hi UFS driver. Signed-off-by: Li Wei Signed-off-by: Zhangfei Gao Signed-off-by: Guodong Xu --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index

Re: [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712

Hi, CK: On Fri, 2018-05-25 at 11:18 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote: > > From: Stu Hsieh > > > > Update device tree binding documentation for the display subsystem for > > Mediatek MT2712 SoCs. > > > > I've acked v2 of this

[PATCH] ASoC: AMD: make channel 1 dma as circular

channel 1: SYSMEM<->ACP channel 2: ACP<->I2S Instead of waiting on period interrupt of ch 2 and then starting dma on ch1, we make ch1 dma as circular. This removes dependency of period granularity on hw pointer. Signed-off-by: Akshu Agrawal --- sound/soc/amd/acp-pcm-dma.c | 72

Re: [PATCH v7 2/5] dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation

Hi Michel, On Thu, May 24, 2018 at 11:28 AM, Michel Pollet wrote: > The Renesas R9A06G032 SYSCTRL node description. > > Signed-off-by: Michel Pollet Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt > @@ -0,0 +1,32 @@ > +*

Re: [PATCH 2/2] ACPI: EC: Dispatch the EC GPE directly on s2idle wake

On 25 May 2018 at 10:48, Rafael J. Wysocki wrote: > On Fri, May 25, 2018 at 10:08 AM, Rafael J. Wysocki wrote: >> On Fri, May 25, 2018 at 8:49 AM, Ulf Hansson wrote: >>> Rafael, >>> >>> On 18 May 2018 at 08:10, kbuild test robot wrote: Hi Rafael, I love your patch! Yet something

Re: [PATCH v1] arch/x86/kernel/pci-dma: Remove useless parameter of arch_dma_alloc_attrs

Thanks, applied to the dma-mapping tree.

[PATCH] usb: gadget: composite: fix delayed_status race condition when set_interface

It happens when enable debug log, if set_alt() returns USB_GADGET_DELAYED_STATUS and usb_composite_setup_continue() is called before increasing count of @delayed_status, so fix it by using spinlock of @cdev->lock. Signed-off-by: Chunfeng Yun Tested-by: Jay Hsu ---

Re: [PATCH v6 3/9] docs: Add Generic Counter interface documentation

On 05/22/2018 07:08 PM, Jonathan Cameron wrote: +* Quadrature x2 Rising: + Rising edges on either quadrature pair signals updates the respective + count. Quadrature encoding determines the direction. >>> This one I've never met. Really? There are devices who do this form >>> of

Re: [PATCH v3 4/8] drm/mediatek: add ddp component AAL1

Hi. CK: On Fri, 2018-05-25 at 12:23 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote: > > From: Stu Hsieh > > > > This patch add component AAL1 and > > rename AAL to AAL0 > > > > Signed-off-by: Stu Hsieh > > --- > >

Re: [PATCH v7 3/5] ARM: dts: Renesas R9A06G032 base device tree file

Hi Michel, On Thu, May 24, 2018 at 11:28 AM, Michel Pollet wrote: > This adds the Renesas R9A06G032 bare bone support. > > This currently only handles generic parts (gic, architected timer) > and a UART. > > Signed-off-by: Michel Pollet Thanks for your patch! > --- /dev/null > +++

Re: [PATCH v7 4/5] ARM: dts: Renesas RZN1D-DB Board base file

On Thu, May 24, 2018 at 11:28 AM, Michel Pollet wrote: > This adds a base device tree file for the RZN1-DB board, with only the > basic support allowing the system to boot to a prompt. Only one UART is > used, with only a single CPU running. > > Signed-off-by: Michel Pollet Reviewed-by: Geert

Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712

Hi, CK: On Fri, 2018-05-25 at 12:51 +0800, CK Hu wrote: > Hi, Stu: > > I've some inline comment. > > On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote: > > From: Stu Hsieh > > > > This patch add support for the Mediatek MT2712 DISP subsystem. > > There are two OVL engine and

Re: [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1

Hi, CK: For this patch, I would move it after "add ddp component OD1" And add this line "#define OD1_MOUT_EN_RDMA1 BIT(16)" from the path "Add support for mediatek SOC MT2712" to this patch Regards, Stu On Fri, 2018-05-25 at 11:26 +0800, CK Hu wrote: > Hi, Stu: > > On Fri,

[PATCH] afs/server: Remove leftover variable

Variable ret is set two times in afs_install_server() but never dereferenced. It is a leftover of a rework of afs_install_server() by commit d2ddc776a458 ("afs: Overhaul volume and server record caching and fileserver rotation"). Signed-off-by: Anna-Maria Gleixner --- fs/afs/server.c | 3 +-- 1

Re: [PATCH v8 3/6] cpuset: Add cpuset.sched.load_balance flag to v2

On 24-May 11:22, Waiman Long wrote: > On 05/24/2018 11:16 AM, Juri Lelli wrote: > > On 24/05/18 11:09, Waiman Long wrote: > >> On 05/24/2018 10:36 AM, Juri Lelli wrote: > >>> On 17/05/18 16:55, Waiman Long wrote: > >>> > >>> [...] > >>> > +A parent cgroup cannot distribute all its

RE: [External] Re: [RFC PATCH v2 00/12] get rid of GFP_ZONE_TABLE/BAD

From: Michal Hocko [mailto:mho...@kernel.org] Sent: Thursday, May 24, 2018 8:19 PM> > > Let me try to reply your questions. > > Exactly, GFP_ZONE_TABLE is too complicated. I think there are two advantages > > from the series of patches. > > > > 1. XOR operation is simple and efficient,

[tip:sched/core] kthread: Allow kthread_park() on a parked kthread

Commit-ID: b1f5b378e126133521df668379249fb8265121f1 Gitweb: https://git.kernel.org/tip/b1f5b378e126133521df668379249fb8265121f1 Author: Peter Zijlstra AuthorDate: Fri, 4 May 2018 11:11:42 +0200 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:03:51 +0200 kthread: Allow

[PATCH 1/4] PM / suspend: Prevent might sleep splats

From: Thomas Gleixner timekeeping suspend/resume calls read_persistent_clock() which takes rtc_lock. That results in might sleep warnings because at that point we run with interrupts disabled. We cannot convert rtc_lock to a raw spinlock as that would trigger other might sleep warnings. As a

[PATCH 4/4] PM / wakeup: Make s2idle_lock a RAW_SPINLOCK

The `s2idle_lock' is acquired during suspend while interrupts are disabled even on RT. The lock is acquired for short sections only. Make it a RAW lock which avoids "sleeping while atomic" warnings on RT. Signed-off-by: Sebastian Andrzej Siewior --- kernel/power/suspend.c | 14 +++--- 1

[tip:sched/core] sched/topology: Clarify root domain(s) debug string

Commit-ID: bf5015a50f1fdb248b48405b67cae24dc02605d6 Gitweb: https://git.kernel.org/tip/bf5015a50f1fdb248b48405b67cae24dc02605d6 Author: Juri Lelli AuthorDate: Thu, 24 May 2018 17:29:36 +0200 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:03:38 +0200 sched/topology: Clarify

[tip:sched/core] sched, tracing: Fix trace_sched_pi_setprio() for deboosting

Commit-ID: 4ff648decf4712d39f184fc2df3163f43975575a Gitweb: https://git.kernel.org/tip/4ff648decf4712d39f184fc2df3163f43975575a Author: Sebastian Andrzej Siewior AuthorDate: Thu, 24 May 2018 15:26:48 +0200 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:04:01 +0200 sched,

[PATCH 2/4] PM / wakeup: Make events_lock a RAW_SPINLOCK

The `events_lock' is acquired during suspend while interrupts are disabled even on RT. The lock is taken only for a very brief moment. Make it a RAW lock which avoids "sleeping while atomic" warnings on RT. Signed-off-by: Sebastian Andrzej Siewior --- drivers/base/power/wakeup.c | 18

[tip:sched/core] sched/cpufreq: Modify aggregate utilization to always include blocked FAIR utilization

Commit-ID: 8ecf04e11283a28ca88b8b8049ac93c3a99fcd2c Gitweb: https://git.kernel.org/tip/8ecf04e11283a28ca88b8b8049ac93c3a99fcd2c Author: Patrick Bellasi AuthorDate: Thu, 24 May 2018 15:10:22 +0100 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:04:52 +0200 sched/cpufreq: Modify

[tip:sched/core] sched/fair: Update util_est before updating schedutil

Commit-ID: 2539fc82aa9b07d968cf9ba1ffeec3e0416ac721 Gitweb: https://git.kernel.org/tip/2539fc82aa9b07d968cf9ba1ffeec3e0416ac721 Author: Patrick Bellasi AuthorDate: Thu, 24 May 2018 15:10:23 +0100 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:04:56 +0200 sched/fair: Update

RE: [PATCH V2 1/4] clk: bulk: add of_clk_bulk_get()

Hi Stephen, > -Original Message- > From: Stephen Boyd [mailto:sb...@kernel.org] > Sent: Saturday, March 24, 2018 12:53 AM > To: A.s. Dong ; linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; hdego...@redhat.com; >

PM / suspend / s2idle: avoiding splats on RT

Patch #1 is a repost with the s2idle bits included. I tested via echo s2idle > mem_sleep && echo mem > state and I woke up the machine via the power on button. Patches #2+ were additionally required with s2idle. Sebastian

[tip:perf/core] perf/core: Fix group scheduling with mixed hw and sw events

Commit-ID: a1150c202207cc8501bebc45b63c264f91959260 Gitweb: https://git.kernel.org/tip/a1150c202207cc8501bebc45b63c264f91959260 Author: Song Liu AuthorDate: Thu, 3 May 2018 12:47:16 -0700 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:11:10 +0200 perf/core: Fix group

RE: [PATCH V2 2/4] clk: add new APIs to operate on all available clocks

> -Original Message- > From: Stephen Boyd [mailto:sb...@kernel.org] > Sent: Saturday, March 24, 2018 12:57 AM > To: A.s. Dong ; linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; hdego...@redhat.com; >

Re: [PATCH v3 2/3] arm: shmobile: Add the R9A06G032 SMP enabler driver

Hi Michel, On Thu, May 24, 2018 at 12:30 PM, Michel Pollet wrote: > The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time, it > requires a special enable method to get it started. > > Signed-off-by: Michel Pollet Thanks for your patch! > arch/arm/mach-shmobile/smp-r9a06g032.c

[PATCH v4 04/26] arm64: alternative: Apply alternatives early in boot process

From: Daniel Thompson Currently alternatives are applied very late in the boot process (and a long time after we enable scheduling). Some alternative sequences, such as those that alter the way CPU context is stored, must be applied much earlier in the boot sequence. Introduce

[PATCH v4 00/26] arm64: provide pseudo NMI with GICv3

This series is a continuation of the work started by Daniel [1]. The goal is to use GICv3 interrupt priorities to simulate an NMI. To achieve this, set two priorities, one for standard interrupts and another, higher priority, for NMIs. Whenever we want to disable interrupts, we mask the standard

[PATCH v4 10/26] arm64: Delay daif masking for user return

Masking daif flags is done very early before returning to EL0. Only toggle the interrupt masking while in the vector entry and mask daif once in kernel_exit. Signed-off-by: Julien Thierry Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: James Morse --- arch/arm64/kernel/entry.S | 8

[PATCH v4 19/26] irqchip/gic-v3: Switch to PMR masking after IRQ acknowledge

After an interrupt has been acknowledged, mask the IRQ priority through PMR and clear PSR.I bit, allowing higher priority interrupts to be received during interrupt handling. Signed-off-by: Julien Thierry Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Thomas Gleixner Cc: Jason

[PATCH v4 15/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking

Instead disabling interrupts by setting the PSR.I bit, use a priority higher than the one used for interrupts to mask them via PMR. The value chosen for PMR to enable/disable interrupts encodes the status of interrupts on a single bit. This information is stored in the irqflags values used when

[PATCH v4 14/26] arm64: kvm: Unmask PMR before entering guest

Interrupts masked by ICC_PMR_EL1 will not be signaled to the CPU. This means that hypervisor will not receive masked interrupts while running a guest. Avoid this by making sure ICC_PMR_EL1 is unmasked when we enter a guest. Signed-off-by: Julien Thierry Cc: Christoffer Dall Cc: Marc Zyngier

[tip:perf/core] perf/x86: Store user space frame-pointer value on a sample

Commit-ID: 10b1105004fbd81058383537b67df35cc188ab62 Gitweb: https://git.kernel.org/tip/10b1105004fbd81058383537b67df35cc188ab62 Author: Alexey Budankov AuthorDate: Thu, 24 May 2018 17:11:54 +0300 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:11:12 +0200 perf/x86: Store user

[PATCH v4 23/26] irqchip/gic: Add functions to access irq priorities

Add accessors to the GIC distributor/redistributors priority registers. Signed-off-by: Julien Thierry Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier --- drivers/irqchip/irq-gic-common.c | 10 ++ drivers/irqchip/irq-gic-common.h | 2 ++ 2 files changed, 12 insertions(+) diff

RE: [PATCH V2 3/4] clk: add managed version of clk_bulk_get_all

> -Original Message- > From: kbuild test robot [mailto:l...@intel.com] > Sent: Friday, March 23, 2018 2:49 PM > To: A.s. Dong > Cc: kbuild-...@01.org; linux-...@vger.kernel.org; linux- > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com;

[PATCH v4 22/26] arm64: Detect current view of GIC priorities

The values non secure EL1 needs to use for PMR and RPR registers depends on the value of SCR_EL3.FIQ. The values non secure EL1 sees from the distributor and redistributor depend on whether security is enabled for the GIC or not. Figure out what values we are dealing with to know if the values

[tip:locking/core] locking/rwsem: Simplify the is-owner-spinnable checks

Commit-ID: 1b22fc609cecd1b16c4a015e1a6b3c9717484e3a Gitweb: https://git.kernel.org/tip/1b22fc609cecd1b16c4a015e1a6b3c9717484e3a Author: Oleg Nesterov AuthorDate: Fri, 18 May 2018 18:55:35 +0200 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:11:47 +0200 locking/rwsem: Simplify

[PATCH V4] powercap/drivers/idle_injection: Add an idle injection framework

Initially, the cpu_cooling device for ARM was changed by adding a new policy inserting idle cycles. The intel_powerclamp driver does a similar action. Instead of implementing idle injections privately in the cpu_cooling device, move the idle injection code in a dedicated framework and give the

[PATCH v4 24/26] irqchip/gic-v3: Add base support for pseudo-NMI

Provide a higher priority to be used for pseudo-NMIs. When such an interrupt is received, enter the NMI state and prevent other NMIs to be raised. When returning from a pseudo-NMI, skip preemption and tracing if the interrupted context has interrupts disabled. Signed-off-by: Julien Thierry Cc:

[PATCH v4 26/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI

Provide a way to set a GICv3 interrupt as pseudo-NMI. The interrupt must not be enabled when setting/clearing the NMI status of the interrupt. Signed-off-by: Julien Thierry Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 54

[PATCH v4 25/26] irqchip/gic-v3: Provide NMI handlers

Provide irqchip handlers that are NMI safe for PPIs and SPIs. Signed-off-by: Julien Thierry Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 44 1 file changed, 44 insertions(+) diff --git

[PATCH v4 21/26] arm64: Add build option for IRQ masking via priority

Provide a build option to enable using GICv3 priorities to enable/disable interrupts. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/Kconfig | 15 +++ 1 file changed, 15 insertions(+) diff --git

[PATCH v4 20/26] arm64: Switch to PMR masking when starting CPUs

Once the boot CPU has been prepared or a new secondary CPU has been brought up, use ICC_PMR_EL1 to mask interrupts on that CPU and clear PSR.I bit. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Catalin Marinas Cc: Will Deacon Cc: James Morse Cc: Marc Zyngier ---

[PATCH v4 18/26] irqchip/gic-v3: Do not overwrite PMR value

If the architecture is using ICC_PMR_EL1 to mask IRQs, do not overwrite that value. Signed-off-by: Julien Thierry Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git

[PATCH v4 17/26] irqchip/gic-v3: Factor group0 detection into functions

The code to detect whether Linux has access to group0 interrupts can prove useful in other parts of the driver. Provide a separate function to do this. Signed-off-by: Julien Thierry Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 55

[PATCH v4 16/26] arm64: daifflags: Include PMR in daifflags restore operations

The addition of PMR should not bypass the semantics of daifflags. When DA_F are set, I bit is also set as no interrupts (even of higher priority) is allowed. When DA_F are cleared, I bit is cleared and interrupt enabling/disabling goes through ICC_PMR_EL1. Signed-off-by: Julien Thierry Cc:

[PATCH v4 12/26] arm64: Unmask PMR before going idle

CPU does not received signals for interrupts with a priority masked by ICC_PMR_EL1. This means the CPU might not come back from a WFI instruction. Make sure ICC_PMR_EL1 does not mask interrupts when doing a WFI. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Catalin Marinas

Re: [tip:sched/core] sched, tracing: Fix trace_sched_pi_setprio() for deboosting

On 2018-05-25 02:47:20 [-0700], tip-bot for Sebastian Andrzej Siewior wrote: > Commit-ID: 4ff648decf4712d39f184fc2df3163f43975575a > Gitweb: > https://git.kernel.org/tip/4ff648decf4712d39f184fc2df3163f43975575a > Author: Sebastian Andrzej Siewior > AuthorDate: Thu, 24 May 2018 15:26:48

[tip:perf/core] perf/core: Wire up compat PERF_EVENT_IOC_QUERY_BPF, PERF_EVENT_IOC_MODIFY_ATTRIBUTES

Commit-ID: 82489c5fe5f99ca95f708fecae9f2c8aa99398bb Gitweb: https://git.kernel.org/tip/82489c5fe5f99ca95f708fecae9f2c8aa99398bb Author: Eugene Syromiatnikov AuthorDate: Mon, 21 May 2018 14:34:20 +0200 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:11:11 +0200 perf/core: Wire

[PATCH v4 11/26] arm64: Make PMR part of task context

If ICC_PMR_EL1 is used to mask interrupts, its value should be saved/restored whenever a task is context switched out/in or gets an exception. Add PMR to the registers to save in the pt_regs struct upon kernel entry, and restore it before ERET. Also, initialize it to a sane value when creating

[PATCH v4 13/26] arm/arm64: gic-v3: Add helper functions to manage IRQ priorities

Add a function to check if priority masking is supported and accessors for PMR/RPR. Signed-off-by: Julien Thierry Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier --- arch/arm/include/asm/arch_gicv3.h | 21 + arch/arm64/include/asm/arch_gicv3.h |

[PATCH] Bluetooth: Add a new Realtek 8723DE ID 0bda:b009

Without this patch we cannot turn on the Bluethooth adapter on HP 14-bs007la. T: Bus=01 Lev=02 Prnt=03 Port=00 Cnt=01 Dev#= 4 Spd=12 MxCh= 0 D: Ver= 1.10 Cls=e0(wlcon) Sub=01 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=0bda ProdID=b009 Rev= 2.00 S: Manufacturer=Realtek S: Product=802.11n WLAN

[PATCH v4 09/26] arm64: Use daifflag_restore after bp_hardening

For EL0 entries requiring bp_hardening, daif status is kept at DAIF_PROCCTX_NOIRQ until after hardening has been done. Then interrupts are enabled through local_irq_enable(). Before using local_irq_* functions, daifflags should be properly restored to a state where IRQs are enabled. Enable IRQs

[PATCH v4 08/26] arm64: daifflags: Use irqflags functions for daifflags

Some of the work done in daifflags save/restore is already provided by irqflags functions. Daifflags should always be a superset of irqflags (it handles irq status + status of other flags). Modifying behaviour of irqflags should alter the behaviour of daifflags. Use irqflags_save/restore

[PATCH v4 02/26] arm64: cpufeature: Add cpufeature for IRQ priority masking

Add a cpufeature indicating whether a cpu supports masking interrupts by priority. Signed-off-by: Julien Thierry Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: Suzuki K Poulose --- arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpufeature.c | 15 +++ 2

[PATCH v4 05/26] irqchip/gic: Unify GIC priority definitions

LPIs use the same priority value as other GIC interrupts. Make the GIC default priority definition visible to ITS implementation and use this same definition for LPI priorities. Signed-off-by: Julien Thierry Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier ---

[PATCH v4 06/26] irqchip/gic: Lower priority of GIC interrupts

The current value used for IRQ priorities is high among the non-secure interrupt priority values. Lower the default priority of interrupts so there is more flexibility to define higher priority interrupts. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Marc Zyngier ---

[PATCH v4 07/26] irqchip/gic-v3: Remove acknowledge loop

Multiple interrupts pending for a CPU is actually rare. Doing an acknowledge loop does not give much better performance or even can deteriorate them. Do not loop when an interrupt has been acknowledged, just return from interrupt and wait for another one to be raised. Signed-off-by: Julien

[PATCH v4 03/26] arm64: cpufeature: Use alternatives for VHE cpu_enable

The cpu_enable callback for VHE feature requires all alternatives to have been applied. This prevents applying VHE alternative separately from the rest. Use an alternative depending on VHE feature to know whether VHE alternatives have already been applied. Signed-off-by: Julien Thierry Cc:

[tip:perf/core] perf/core: Fix bad use of igrab()

Commit-ID: 9511bce9fe8e5e6c0f923c09243a713eba560141 Gitweb: https://git.kernel.org/tip/9511bce9fe8e5e6c0f923c09243a713eba560141 Author: Song Liu AuthorDate: Tue, 17 Apr 2018 23:29:07 -0700 Committer: Ingo Molnar CommitDate: Fri, 25 May 2018 08:11:10 +0200 perf/core: Fix bad use of

[PATCH v4 01/26] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature

Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kernel/cpufeature.c

[PATCH 3/4] PM / s2idle: Make s2idle_wait_head swait based

s2idle_wait_head is used during s2idle with interrupts disabled even on RT. There is no "custom" wake up function so swait could be used instead which is also lower weight compared to the wait_queue. Make s2idle_wait_head a swait_queue_head. Signed-off-by: Sebastian Andrzej Siewior ---

[PATCH v2 1/6] soc: qcom: rpmpd: Add a powerdomain driver to model corners

The powerdomains for corners just pass the performance state set by the consumers to the RPM (Remote Power manager) which then takes care of setting the appropriate voltage on the corresponding rails to meet the performance needs. We add all powerdomain data needed on msm8996 here. This driver

Re: [PATCH v4 04/26] arm64: alternative: Apply alternatives early in boot process

On 25/05/18 10:49, Julien Thierry wrote: From: Daniel Thompson Currently alternatives are applied very late in the boot process (and a long time after we enable scheduling). Some alternative sequences, such as those that alter the way CPU context is stored, must be applied much earlier in the

[PATCH v2 6/6] soc: qcom: rpmpd/rpmhpd: Add a max vote on all corners at init

As we move from no clients/consumers in kernel voting on corners, to *some* voting and some not voting, we might end up in a situation where the clients which remove votes can adversly impact others who still don't have a way to vote. To avoid this situation, have a max vote on all corners at

[PATCH v2 4/6] arm64: dts: msm8996: Add rpmpd device node

Add rpmpd device node and its OPP table Signed-off-by: Rajendra Nayak Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 40 +++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi

[PATCH v2 2/6] dt-bindings: opp: Introduce qcom-opp bindings

On Qualcomm platforms, an OPP node needs to describe an additional level/corner value that is then communicated to a remote microprocessor by the CPU, which then takes some actions (like adjusting voltage values across various rails) based on the value passed. Describe these bindings in the

[PATCH v2 5/6] soc: qcom: rpmh powerdomain driver

The RPMh powerdomain driver aggregates the corner votes from various consumers for the ARC resources and communicates it to RPMh. We also add data for all powerdomains on sdm845 as part of the patch. The driver can be extended to support other SoCs which support RPMh Signed-off-by: Rajendra

Re: [PATCHv4 05/10] arm64/cpufeature: detect pointer authentication

On Wed, May 23, 2018 at 09:48:28AM +0100, Suzuki K Poulose wrote: > > Mark, > > On 03/05/18 14:20, Mark Rutland wrote: > > So that we can dynamically handle the presence of pointer authentication > > functionality, wire up probing code in cpufeature.c. > > > > From ARMv8.3 onwards,

[PATCH v2 3/6] soc: qcom: rpmpd: Add support for get/set performance state

Add support for the .set_performace_state() and .opp_to_performance_state() callbacks in the rpmpd driver. Signed-off-by: Rajendra Nayak Signed-off-by: Viresh Kumar --- drivers/soc/qcom/rpmpd.c | 46 1 file changed, 46 insertions(+) diff --git

[PATCH v2 0/6] Add powerdomain driver for corners on msm8996/sdm845

Changes in v2: * added a powerdomain driver for sdm845 which supports communicating to RPMh * dropped the changes to sdhc driver to move over to using OPP as there is active discussion on using OPP as the interface vs handling all of it in clock drivers * Other minor binding updates based on

Re: [PATCH 1/4] PM / suspend: Prevent might sleep splats

On Fri, May 25, 2018 at 11:46 AM, Sebastian Andrzej Siewior wrote: > From: Thomas Gleixner > > timekeeping suspend/resume calls read_persistent_clock() which takes > rtc_lock. That results in might sleep warnings because at that point > we run with interrupts disabled. > > We cannot convert

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