Hi Guenter,
thank you for the feedback! checkpatch didn't catch this.
I sent v2 of the patch.
Best regards,
Michael
On Tue, 2020-11-10 at 06:39 -0800, Guenter Roeck wrote:
> On 11/9/20 11:46 PM, Michael Brunner wrote:
> > Change the detection order to priorize DMI table entries over
> > availa
Hi Sherry, Arnd,
On 10/11/20 8:29 pm, Arnd Bergmann wrote:
> On Tue, Nov 10, 2020 at 3:20 PM Kishon Vijay Abraham I wrote:
>> On 10/11/20 7:55 am, Sherry Sun wrote:
>
>>> But for VOP, only two boards are needed(one board as host and one board as
>>> card) to realize the
>>> communication betwee
The standard DT property name is "interrupt-names".
Fixes: fd913ef7ce619467 ("Bluetooth: btusb: Add out-of-band wakeup support")
Signed-off-by: Geert Uytterhoeven
Acked-by: Rob Herring
Reviewed-by: Brian Norris
Acked-by: Rajat Jain
---
Who takes this patch, before it celebrates its 4th birthda
On Tue, 10 Nov 2020 at 14:54, Marco Elver wrote:
>
> On Tue, 10 Nov 2020 at 10:36, Dmitry Vyukov wrote:
> [...]
> > > > On Tue, Nov 10, 2020 at 8:50 AM Anders Roxell
> > > > wrote:
> [...]
> > > > > When building an arm64 allmodconfig and booting up that in qemu I see
> > > > >
> > > > > [10011
On Thu, Oct 22, 2020 at 2:52 AM Oleksij Rempel wrote:
>
> In order to automate the verification of DT nodes convert
> fsl-flexcan.txt to fsl,flexcan.yaml
>
> Signed-off-by: Oleksij Rempel
> Link: https://lore.kernel.org/r/20201016073315.16232-3-o.rem...@pengutronix.de
> Signed-off-by: Marc Kleine
The Freescale QorIQ AHCI SATA controller is only present on Freescale
Layerscape SoCs. Add platform dependencies to the AHCI_QORIQ config
symbol, to avoid asking the user about it when configuring a kernel
without Layerscape support.
Signed-off-by: Geert Uytterhoeven
Acked-by: Arnd Bergmann
Ack
On 11/10/2020 5:21 AM, Kurt Kanzenbach wrote:
> On Mon Nov 09 2020, Florian Fainelli wrote:
>> From: Kurt Kanzenbach
>>
>> Convert the b53 DSA device tree bindings to YAML in order to allow
>> for automatic checking and such.
>>
>> Suggested-by: Florian Fainelli
>> Signed-off-by: Kurt Kanzenba
On 11/10/2020 1:31 AM, Rafał Miłecki wrote:
> 10.11.2020 04:31, Florian Fainelli wrote:
>> Provide an empty 'ports' container node with the correct #address-cells
>> and #size-cells properties. This silences the following warning:
>>
>> arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml:
>> etherne
The Freescale QorIQ clock controller is only present on Freescale E500MC
and Layerscape SoCs. Add platform dependencies to the CLK_QORIQ config
symbol, to avoid asking the user about it when configuring a kernel
without E500MC or Layerscape support.
Signed-off-by: Geert Uytterhoeven
Acked-by: Ar
The MicroBlaze platform code is not a clock provider, and just needs to
call of_clk_init().
Hence it can include instead of .
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Stephen Boyd
---
v2:
- Add Reviewed-by.
---
arch/microblaze/kernel/setup.c | 2 +-
1 file changed, 1 insertion(+), 1 d
On 01/01/70 01:00, Valentin Schneider wrote:
> On 10/11/20 13:03, Peter Zijlstra wrote:
>> On Mon, Nov 02, 2020 at 10:30:50AM +, Valentin Schneider wrote:
>>
>>> Now, I'd like to pen exactly why we think it's okay to forgo irq_{enter,
>>> exit}() for that one IRQ and not any other.
>>
>> Thom
Restore alignment of the continuation of the devm_ioremap() call in
register_intc_controller().
Fixes: 4bdc0d676a643140 ("remove ioremap_nocache and devm_ioremap_nocache")
Signed-off-by: Geert Uytterhoeven
---
drivers/sh/intc/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
The SuperH/J2 DT platform code is not a clock provider, and just needs
to call of_clk_init().
Hence it can include instead of .
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Stephen Boyd
---
v2:
- Add Reviewed-by.
---
arch/sh/boards/of-generic.c | 2 +-
1 file changed, 1 insertion(+), 1 de
On Tue, Nov 10, 2020 at 11:40:34AM +0100, Paolo Bonzini wrote:
> However, f/m/s mean nothing when running virtualized. First, trying to
> derive any non-architectural property from the f/m/s is going to fail.
> Second, even the host can be anything as long as it's newer than the f/m/s
> that the V
The Xtensa time code is not a clock provider, and just needs to call
of_clk_init().
Hence it can include instead of .
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Stephen Boyd
Acked-by: Max Filippov
---
v2:
- Add Reviewed-by, Acked-by.
---
arch/xtensa/kernel/time.c | 2 +-
1 file changed
Andy Shevchenko writes:
> On Mon, Nov 9, 2020 at 3:27 PM Lars Povlsen
> wrote:
>>
>> This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
>> (SGPIO) device used in various SoC's.
>
> Please, elaborate what you said previously, because now it has no
> justification to be a pin con
Currently, we do not have any documentation on commit reverts regarding
the requirement of Signed-off-by tag for it. This may be misleading to
the users.
Evaluating MISSING_SIGN_OFF checkpatch warnings on v4.13..v5.8 showed
that 4 out of 11 cases missing a sign-off are revert commits.
Add documen
Hi Zhenzhong
On Tue, 2020-11-10 at 15:19 +0800, Zhenzhong Duan wrote:
> "intel_iommu=off" command line is used to disable iommu but iommu is force
> enabled in a tboot system for security reason.
>
> However for better performance on high speed network device, a new option
> "intel_iommu=tboot_no
Hello!
On 11/10/20 6:49 PM, Geert Uytterhoeven wrote:
> Restore alignment of the continuation of the devm_ioremap() call in
It's a plain ioremap() call below, isn't it, :-)
> register_intc_controller().
>
> Fixes: 4bdc0d676a643140 ("remove ioremap_nocache and devm_ioremap_nocache")
> Signed
On Tue, Nov 10 2020 at 08:55, Tom Lendacky wrote:
> On 11/10/20 8:34 AM, Thomas Gleixner wrote:
> I was about to send the dmesg output when I saw this. A quick test with
> this change resolves the boot issue, thanks!
/me feels stupid
> I'm still seeing the warning at arch/x86/kernel/apic/apic.c:2
C6X never used , which was presumably opied from ARM.
Signed-off-by: Geert Uytterhoeven
---
arch/c6x/include/asm/procinfo.h | 24
arch/c6x/kernel/asm-offsets.c | 1 -
2 files changed, 25 deletions(-)
delete mode 100644 arch/c6x/include/asm/procinfo.h
diff --git a/ar
On 2020-11-09 11:32, David Brazdil wrote:
When the a CPU is booted in EL2, the kernel checks for VHE support and
initializes the CPU core accordingly. For nVHE it also installs the
stub
vectors and drops down to EL1.
Once KVM gains the ability to boot cores without going through the
kernel ent
Currently the Kontron sl28cpld Board Management Controller is found only
on Kontron boards equipped with a Freescale Layerscape SoC. Hence add a
dependency on ARCH_LAYERSCAPE, to prevent asking the user about a driver
for this controller when configuring a kernel without Layerscape support.
Fixes
Andy Shevchenko writes:
> On Mon, Nov 9, 2020 at 5:27 PM Alexandre Belloni
> wrote:
>> On 09/11/2020 17:16:49+0200, Andy Shevchenko wrote:
>> > On Mon, Nov 9, 2020 at 4:32 PM Alexandre Belloni
>> > wrote:
>> > > On 09/11/2020 16:17:40+0200, Andy Shevchenko wrote:
>
> ...
>
>> > > > > +
On 26.10.20 21:10, Cristian Marussi wrote:
> Add support for new SCMIv3.0 Sensors extensions related to new sensors'
> features, like multiple axis and update intervals, while keeping
> compatibility with SCMIv2.0 features.
> While at that, refactor and simplify all the internal helpers macros and
Hi,
On 10/11/20 11:50, Heikki Krogerus wrote:
> On Mon, Nov 09, 2020 at 10:15:36PM -0800, Prashant Malani wrote:
>> Set the number of altmodes available for a registered partner using the
>> Type C connector class framework routine.
>>
>> Signed-off-by: Prashant Malani
>
> Reviewed-by: Heikki Kr
On Mon, Nov 09, 2020 at 01:05:12PM +, Wang Wensheng wrote:
> A reboot notifier, which stops the WDT by calling the stop hook without
> any check, would be registered when we set WDOG_STOP_ON_REBOOT flag.
>
> Howerer we allow the WDT driver to omit the stop hook since commit
> "d0684c8a93549" (
On Tue, 2020-11-10 at 16:54 +0100, Thomas Gleixner wrote:
> On Tue, Nov 10 2020 at 08:55, Tom Lendacky wrote:
> > On 11/10/20 8:34 AM, Thomas Gleixner wrote:
> > I was about to send the dmesg output when I saw this. A quick test
> > with
> > this change resolves the boot issue, thanks!
>
> /me fee
On 26.10.20 21:10, Cristian Marussi wrote:
> Add support for new SCMIv3.0 SENSOR_UPDATE notification.
>
> Signed-off-by: Cristian Marussi
> ---
> drivers/firmware/arm_scmi/sensors.c | 124
> include/linux/scmi_protocol.h | 9 ++
> 2 files changed, 116 inserti
On 26.10.20 21:10, Cristian Marussi wrote:
> Add new .reading_get_timestamped() method to sensor_ops to support SCMIv3.0
> timestamped reads.
>
> Signed-off-by: Cristian Marussi
> ---
> drivers/firmware/arm_scmi/sensors.c | 134 ++--
> include/linux/scmi_protocol.h
On Fri, 6 Nov 2020 14:14:31 +0800, Ajye Huang wrote:
> Note:
> - The patch is made by the collaboration of
> Ajye Huang
> Cheng-Yi Chiang
>
> v6:
> - Documentation: Addressed suggestions from Rob Herring.
> - Define "maxItems: 1" in dmic-gpios property.
> - Only keep one example and add dm
On Tue, 10 Nov 2020 10:31:30 +0800, Shane Chien wrote:
> This series of patches is to fix vaud18 power leakage problem.
> vaud18 will be enable only when mt6359 audio path is turned on.
>
> Change since v2:
> - fix dt-binnding syntex error
>
> Change since v1:
> - use dapm regulator supply widg
On Mon, 28 Sep 2020 14:37:42 +0800, Ajye Huang wrote:
> Note:
> - This patch depends on this patch series
> ASoC: qcom: dt-bindings: Add sc7180 machine bindings
> https://patchwork.kernel.org/patch/11773221/
> ASoC: qcom: sc7180: Add machine driver for sound card registration
> https://patchwor
On Tue, Nov 10, 2020 at 04:40:23PM +1100, Brad Campbell wrote:
> On 10/11/20 3:55 pm, Guenter Roeck wrote:
> > On Tue, Nov 10, 2020 at 01:04:04PM +1100, Brad Campbell wrote:
> >> On 9/11/20 3:06 am, Guenter Roeck wrote:
> >>> On 11/8/20 2:14 AM, Henrik Rydberg wrote:
> On Sun, Nov 08, 2020 at
>
> On Tue, Nov 10, 2020 at 11:57:07AM +0100, Bastien Nocera wrote:
> > Hey,
> >
> > systemd has been shipping this script to enable auto-suspend on a
> > number of USB and PCI devices:
> >
> https://github.com/systemd/systemd/blob/master/tools/chromiumos/gen_autosuspen
> d_rules.py
> >
> > The pr
On Sun, Nov 8, 2020 at 8:03 PM Weiyi Lu wrote:
>
> Add MT8192 clock dt-bindings, include topckgen, apmixedsys,
> infracfg, pericfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu
> ---
> include/dt-bindings/clock/mt8192-clk.h | 592
> +
> 1 file changed, 592 in
On Mon, 9 Nov 2020 17:30:07 +0800, Shane Chien wrote:
> This series of patches is to fix vaud18 power leakage problem.
> vaud18 will be enable only when mt6359 audio path is turned on.
>
> Change since v1:
> - use dapm regulator supply widget for vaud18 control.
> - add vaud18 regulator property
Hi,
a handful of minor fixes and updates:
- handle missing device replace item on mount (syzbot report)
- fix space reservation calculation when finishing relocation
- fix memory leak on error path in ref-verify (debugging feature)
- fix potential overflow during defrag on 32bit arches
- mino
Hi,Mark
Thank you, I already understand, sorry for causing you trouble.
Ajye
On Tue, Nov 10, 2020 at 7:56 PM Mark Brown wrote:
>
> On Tue, Nov 10, 2020 at 05:40:40PM +0800, Ajye Huang wrote:
> > Hi, Mark
> >
> > Could you please kindly review the series patch v6? And may I get your
> > approval
On 10/11/20 16:50, Borislav Petkov wrote:
I was thinking of
having a mapping between f/m/s and a list of MSRs which those models
have - even non-architectural ones - but that's a waste of energy. Why?
Because using the *msr_safe() variants will give you the same thing
Yes, pretty much.
If it
On 10/11/2020 15:32, Paul E. McKenney wrote:
> On Mon, Nov 09, 2020 at 11:07:21PM -0500, Paul Gortmaker wrote:
>> RFC/v1 ---> v2:
>>
>> commit #1:
>>leave one line stub behind for !SMP solving build failures.
>>Reported by Randy Dunlap and various build bots.
>>
>> commit #4
>>manage to
On Tue, Nov 10, 2020 at 03:41:47PM +, Michael Brunner wrote:
> Hi Guenter,
>
> thank you for the feedback! checkpatch didn't catch this.
> I sent v2 of the patch.
>
It may have been "demoted" to --strict for whatever reason.
Guenter
> Best regards,
> Michael
>
> On Tue, 2020-11-10 at 06
On Tue, Nov 10, 2020 at 04:12:38PM +0100, Bartosz Golaszewski wrote:
> On Tue, Nov 10, 2020 at 4:09 PM Andy Shevchenko
> wrote:
> >
> > On Tue, Nov 10, 2020 at 05:04:47PM +0200, Andy Shevchenko wrote:
> > > On Tue, Nov 10, 2020 at 03:55:51PM +0100, Bartosz Golaszewski wrote:
> > > > From: Bartosz
On Tue, Nov 10, 2020 at 03:23:21PM +, Michael Brunner wrote:
> Change the detection order to priorize DMI table entries over available
> ACPI entries.
>
> This makes it more easy for product developers to patch product specific
> handling into the driver.
> Furthermore it allows to simplify th
On Mon, Nov 09, 2020 at 08:48:01PM -0800, Sami Tolvanen wrote:
> On Mon, Nov 9, 2020 at 6:29 PM Josh Poimboeuf wrote:
> > How would I recreate all these warnings?
>
> You can reproduce all of these using a normal gcc build without any of
> the LTO patches by running objtool check -arfld vmlinux.o
This adds syscon_regmap_lookup_by_phandle_optional() function to get an
optional regmap.
It behaves the same as syscon_regmap_lookup_by_phandle() except where
there is no regmap phandle. In this case, instead of returning -ENODEV,
the function returns NULL. This makes error checking simpler when t
On Tue, Nov 10, 2020 at 03:43:50PM +0100, Geert Uytterhoeven wrote:
> The Intel Keem Bay display controller is only present on Intel Keem Bay
> SoCs. Hence add a dependency on ARCH_KEEMBAY, to prevent asking the
> user about this driver when configuring a kernel without Intel Keem Bay
> platform s
On Tue, 10 Nov 2020 08:19:32 -0300 Thadeu Lima de Souza Cascardo wrote:
> Yeah, I agree with your initial email. The patch I submitted for that fix
> needs
> rework, which is what I tried and failed so far. I need to get back to some
> testing of my latest fix and find out what needs fixing there.
On 11/10/20 9:54 AM, Thomas Gleixner wrote:
> On Tue, Nov 10 2020 at 08:55, Tom Lendacky wrote:
>> On 11/10/20 8:34 AM, Thomas Gleixner wrote:
>> I was about to send the dmesg output when I saw this. A quick test with
>> this change resolves the boot issue, thanks!
>
> /me feels stupid
>
>> I'm s
On Tue, Nov 10, 2020 at 5:07 PM Andy Shevchenko
wrote:
> On Tue, Nov 10, 2020 at 03:55:45PM +0100, Bartosz Golaszewski wrote:
> With reverted reg_width change
I should have relaxed this to "with whatever settlement we become
about regmap configuration".
> Reviewed-by: Andy Shevchenko
--
Wit
Hi Daniel, Thomas,
This patch series picks up missing Device Tree binding updates for the
Renesas Timer Unit (TMU), and converts the bindings to json-schema.
Thanks for applying!
Geert Uytterhoeven (1):
dt-bindings: timer: renesas: tmu: Convert to json-schema
Marian-Cristian Rotariu (
From: Marian-Cristian Rotariu
Document RZ/G2H (R8A774E1) SoC in the Renesas TMU bindings.
Signed-off-by: Marian-Cristian Rotariu
Signed-off-by: Lad Prabhakar
Signed-off-by: Geert Uytterhoeven
---
v5:
- Pick up as a dependency.
---
Documentation/devicetree/bindings/timer/renesas,tmu.txt |
Convert the Renesas R-Mobile/R-Car Timer Unit (TMU) Device Tree binding
documentation to json-schema.
Document missing properties.
Update the example to match reality.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Rob Herring
---
v5:
- No changes,
v4:
- Rebase on top of "dt-bindings: time
On Tue, Nov 10, 2020 at 12:21:11PM +0100, Arnd Bergmann wrote:
> On Tue, Nov 10, 2020 at 10:58 AM Mike Rapoport wrote:
> > > >
> > > > asm/sparsemem.h is not available on some architectures.
> > > > It's better to use linux/mmzone.h instead.
>
> Ah, I missed that, too.
>
> > > Hm, linux/mmzone.h
Add CPU feature flags for Control-flow Enforcement Technology (CET).
CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack
CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect Branch Tracking
Signed-off-by: Yu-cheng Yu
Reviewed-by: Kees Cook
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/kernel/cpu/cpuid-d
Pte_modify() changes a PTE to 'newprot'. It doesn't use the pte_*()
helpers that a previous patch fixed up, so we need a new site.
Introduce fixup_dirty_pte() to set the dirty bits based on _PAGE_RW, and
apply the same changes to pmd_modify().
Signed-off-by: Yu-cheng Yu
---
arch/x86/include/as
Control-flow Enforcement (CET) is a new Intel processor feature that blocks
return/jump-oriented programming attacks. Details are in "Intel 64 and
IA-32 Architectures Software Developer's Manual" [1].
CET can protect applications and the kernel. This series enables only
application-level protect
The kernel allocates (and frees on thread exit) a new shadow stack for a
pthread child.
It is possible for the kernel to complete the clone syscall and set the
child's shadow stack pointer to NULL and let the child thread allocate
a shadow stack for itself. There are two issues in thi
INCSSP(Q/D) increments shadow stack pointer and 'pops and discards' the
first and the last elements in the range, effectively touches those memory
areas.
The maximum moving distance by INCSSPQ is 255 * 8 = 2040 bytes and
255 * 4 = 1020 bytes by INCSSPD. Both ranges are far from PAGE_SIZE.
Thus, p
An ELF file's .note.gnu.property indicates arch features supported by the
file. These features are extracted by arch_parse_elf_property() and stored
in 'arch_elf_state'. Introduce arch_setup_elf_property() for enabling such
features. The first use-case of this function is shadow stack.
ARM64 is
An ELF file's .note.gnu.property indicates architecture features of the
file.. Introduce feature definitions for Shadow Stack and Indirect Branch
Tracking.
Signed-off-by: Yu-cheng Yu
---
include/uapi/linux/elf.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/uapi/linux/elf.
Explain no_user_shstk/no_user_ibt kernel parameters, and introduce a new
document on Control-flow Enforcement Technology (CET).
Signed-off-by: Yu-cheng Yu
---
.../admin-guide/kernel-parameters.txt | 6 +
Documentation/x86/index.rst | 1 +
Documentation/x86/intel_cet
This patch adds basic shadow stack enabling/disabling routines. A task's
shadow stack is allocated from memory with VM_SHSTK flag and has a fixed
size of min(RLIMIT_STACK, 4GB).
Signed-off-by: Yu-cheng Yu
---
arch/x86/include/asm/cet.h | 28 +
arch/x86/include/asm/disabled-fe
Can_follow_write_pte() ensures a read-only page is COWed by checking the
FOLL_COW flag, and uses pte_dirty() to validate the flag is still valid.
Like a writable data page, a shadow stack page is writable, and becomes
read-only during copy-on-write, but it is always dirty. Thus, in the
can_follow
Account shadow stack pages to stack memory.
Signed-off-by: Yu-cheng Yu
---
arch/x86/mm/pgtable.c | 7 +++
include/linux/pgtable.h | 11 +++
mm/mmap.c | 5 +
3 files changed, 23 insertions(+)
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index a9666
Shadow Stack provides protection against function return address
corruption. It is active when the processor supports it, the kernel has
CONFIG_X86_SHADOW_STACK_USER, and the application is built for the feature.
This is only implemented for the 64-bit kernel. When it is enabled, legacy
non-shado
After the introduction of _PAGE_COW, a modified page's PTE can have either
_PAGE_DIRTY_HW or _PAGE_COW. Change _PAGE_DIRTY to _PAGE_DIRTY_BITS.
Signed-off-by: Yu-cheng Yu
Reviewed-by: Kees Cook
Cc: David Airlie
Cc: Joonas Lahtinen
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Cc: Zhen
arch_prctl(ARCH_X86_CET_STATUS, u64 *args)
Get CET feature status.
The parameter 'args' is a pointer to a user buffer. The kernel returns
the following information:
*args = shadow stack/IBT status
*(args + 1) = shadow stack base address
*(args + 2) = shadow stack size
ar
There are three possible options to create a shadow stack allocation API:
an arch_prctl, a new syscall, or adding PROT_SHSTK to mmap()/mprotect().
Each has its advantages and compromises.
An arch_prctl() is the least intrusive. However, the existing x86
arch_prctl() takes only two parameters. Mu
There was no more caller passing vm_flags to do_mmap(), and vm_flags was
removed from the function's input by:
commit 45e55300f114 ("mm: remove unnecessary wrapper function
do_mmap_pgoff()").
There is a new user now. Shadow stack allocation passes VM_SHSTK to
do_mmap(). Re-introduce vm_fla
To deliver a signal, create a shadow stack restore token and put a restore
token and the signal restorer address on the shadow stack. For sigreturn,
verify the token and restore the shadow stack pointer.
Introduce WRUSS, which is a kernel-mode instruction but writes directly to
user shadow stack.
A shadow stack page is made writable by pte_mkwrite_shstk(), which sets
_PAGE_DIRTY_HW. There are a few places that call pte_mkwrite() directly
and miss the maybe_mkwrite() fixup in the previous patch. Fix them with
maybe_mkwrite():
- do_anonymous_page() and migrate_vma_insert_page() check VM_WR
A control-protection fault is triggered when a control-flow transfer
attempt violates Shadow Stack or Indirect Branch Tracking constraints.
For example, the return address for a RET instruction differs from the copy
on the Shadow Stack; or an indirect JMP instruction, without the NOTRACK
prefix, ar
When shadow stack is introduced, [R/O + _PAGE_DIRTY_HW] PTE is reserved
for shadow stack. Copy-on-write PTEs have [R/O + _PAGE_COW].
When a PTE goes from [R/W + _PAGE_DIRTY_HW] to [R/O + _PAGE_COW], it could
become a transient shadow stack PTE in two cases:
The first case is that some processors
Shadow stack memory is writable, but its VMA has VM_SHSTK instead of
VM_WRITE. Update maybe_mkwrite() to include the shadow stack.
Signed-off-by: Yu-cheng Yu
---
arch/x86/Kconfig| 4
arch/x86/mm/pgtable.c | 18 ++
include/linux/mm.h | 2 ++
include/linux/pg
Before introducing _PAGE_COW for non-hardware memory management purposes in
the next patch, rename _PAGE_DIRTY to _PAGE_DIRTY_HW and _PAGE_BIT_DIRTY to
_PAGE_BIT_DIRTY_HW to make meanings more clear. There are no functional
changes from this patch.
Signed-off-by: Yu-cheng Yu
Reviewed-by: Kees Co
A Shadow Stack PTE must be read-only and have _PAGE_DIRTY set. However,
read-only and Dirty PTEs also exist for copy-on-write (COW) pages. These
two cases are handled differently for page faults. Introduce VM_SHSTK to
track shadow stack VMAs.
Signed-off-by: Yu-cheng Yu
Reviewed-by: Kees Cook
From: "H.J. Lu"
When Indirect Branch Tracking (IBT) is enabled, vDSO functions may be
called indirectly, and must have ENDBR32 or ENDBR64 as the first
instruction. The compiler must support -fcf-protection=branch so that it
can be used to compile vDSO.
Signed-off-by: H.J. Lu
Signed-off-by: Yu-
Introduce user-mode Indirect Branch Tracking (IBT) support. Update setup
routines to include IBT.
Signed-off-by: Yu-cheng Yu
---
arch/x86/include/asm/cet.h | 3 +++
arch/x86/include/asm/disabled-features.h | 8 +-
arch/x86/kernel/cet.c| 33 +++
Shadow stack accesses are those that are performed by the CPU where it
expects to encounter a shadow stack mapping. These accesses are performed
implicitly by CALL/RET at the site of the shadow stack pointer. These
accesses are made explicitly by shadow stack management instructions like
WRUSSQ.
Update arch_setup_elf_property() for Indirect Branch Tracking.
Signed-off-by: Yu-cheng Yu
---
arch/x86/Kconfig | 2 ++
arch/x86/kernel/process_64.c | 8
2 files changed, 10 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e27f0c19a4b3..7ee6e2957863 10064
From: "H.J. Lu"
Add ENDBR32 to __kernel_vsyscall entry point.
Signed-off-by: H.J. Lu
Signed-off-by: Yu-cheng Yu
Acked-by: Andy Lutomirski
---
arch/x86/entry/vdso/vdso32/system_call.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/entry/vdso/vdso32/system_call.S
b/arch/x86/e
From: "H.J. Lu"
Update ARCH_X86_CET_STATUS and ARCH_X86_CET_DISABLE for Indirect Branch
Tracking.
Signed-off-by: H.J. Lu
Signed-off-by: Yu-cheng Yu
---
arch/x86/kernel/cet_prctl.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cet_prctl.c b/arch/x86
There is essentially no room left in the x86 hardware PTEs on some OSes
(not Linux). That left the hardware architects looking for a way to
represent a new memory type (shadow stack) within the existing bits.
They chose to repurpose a lightly-used state: Write=0,Dirty=1.
The reason it's lightly u
Control-flow Enforcement (CET) is a new Intel processor feature that blocks
return/jump-oriented programming attacks. Details are in "Intel 64 and
IA-32 Architectures Software Developer's Manual" [1].
This is the second part of CET and enables Indirect Branch Tracking (IBT).
It is built on top of
On Tue, Nov 10, 2020 at 5:51 PM Lars Povlsen wrote:
> > On Mon, Nov 9, 2020 at 3:27 PM Lars Povlsen
> > wrote:
> >> This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
> >> (SGPIO) device used in various SoC's.
> >
> > Please, elaborate what you said previously, because now it ha
Introduce Kconfig option X86_BRANCH_TRACKING_USER.
Indirect Branch Tracking (IBT) provides protection against CALL-/JMP-
oriented programming attacks. It is active when the kernel has this
feature enabled, and the processor and the application support it.
When this feature is enabled, legacy non-
Kernel read-only PTEs are setup as _PAGE_DIRTY_HW. Since these become
shadow stack PTEs, remove the dirty bit.
Signed-off-by: Yu-cheng Yu
Cc: "H. Peter Anvin"
Cc: Kees Cook
Cc: Thomas Gleixner
Cc: Dave Hansen
Cc: Christoph Hellwig
Cc: Andy Lutomirski
Cc: Ingo Molnar
Cc: Borislav Petkov
C
Control-flow Enforcement Technology (CET) adds five MSRs. Introduce them
and their XSAVES supervisor states:
MSR_IA32_U_CET (user-mode CET settings),
MSR_IA32_PL3_SSP (user-mode Shadow Stack pointer),
MSR_IA32_PL0_SSP (kernel-mode Shadow Stack pointer),
MSR_IA32_PL1_SSP (Privilege
An indirect CALL/JMP moves the indirect branch tracking (IBT) state machine
to WAIT_ENDBR status until the instruction reaches an ENDBR opcode. If the
CALL/JMP does not reach an ENDBR opcode, the processor raises a control-
protection fault. WAIT_ENDBR status can be read from MSR_IA32_U_CET.
WAI
On 10/11/20 09:59, David Woodhouse wrote:
Hm, attempting to reproduce this shows something else. Ever since
commit be62dbf554c5 ("iommu/amd: Convert AMD iommu driver to the dma-
iommu api") in 5.5 the following stops working for me:
$ qemu-system-x86_64 -serial mon:stdio -kernel bzImage -machin
On Tue, Nov 10, 2020 at 4:20 PM Sven Van Asbroeck wrote:
>
> From: Sven Van Asbroeck
>
> This driver makes sure the underlying SPI bus is set to "mode 0"
> by assigning SPI_MODE_0 to spi->mode. Which overwrites all other
> SPI mode flags.
>
> In some circumstances, this can break the underlying S
On 10/11/20 4:05 pm, Marco Elver wrote:
> On Tue, 10 Nov 2020 at 08:21, David Gow wrote:
> [...]
The previous attempt [1] at something similar failed because it seems
we'd need to teach kunit-tool new tricks [2], too.
[1] https://lkml.kernel.org/r/20201105195503.ga2399...@elver
On Tue, 2020-11-10 at 10:17 -0600, Tom Lendacky wrote:
> Yep. The warning started triggering with:
> 47bea873cf80 ("x86/msi: Only use high bits of MSI address for DMAR unit")
>
> Here's the backtrace:
>
> [ 15.611109] [ cut here ]
> [ 15.616274] WARNING: CPU: 184 PID:
On Tue, Nov 10, 2020 at 10:21:43AM -0500, Johannes Weiner wrote:
> On Mon, Nov 09, 2020 at 05:06:15PM -0800, Roman Gushchin wrote:
> > Many kernel memory accounting paths are guarded by the
> > memcg_kmem_enabled_key static key. It changes it's state during
> > the onlining of the first non-root cg
Everything in arch/mips/include/uapi/asm/types.h is protected by
"#ifndef __KERNEL__", so it's unused for kernelspace.
Signed-off-by: Geert Uytterhoeven
---
This is a resend of a very old patch from 2013, which is still valid.
arch/mips/include/asm/types.h | 1 -
1 file changed, 1 deletion(-)
On Tue, Nov 10, 2020 at 5:17 PM Andy Shevchenko
wrote:
>
> On Tue, Nov 10, 2020 at 04:12:38PM +0100, Bartosz Golaszewski wrote:
> > On Tue, Nov 10, 2020 at 4:09 PM Andy Shevchenko
> > wrote:
> > >
> > > On Tue, Nov 10, 2020 at 05:04:47PM +0200, Andy Shevchenko wrote:
> > > > On Tue, Nov 10, 2020
Commit
d9e9a6418065 ("x86/mm/pti: Allocate a separate user PGD")
changed the PGD allocation to allocate PGD_ALLOCATION_ORDER pages, so in
the error path it should be freed using free_pages() rather than
free_page().
Commit
06ace26f4e6f ("x86/efi: Free efi_pgd with free_pages()")
fixed one inst
On Tue, Nov 10, 2020 at 03:36:02PM +0100, Christian Eggers wrote:
> On Tuesday, 10 November 2020, 02:42:34 CET, Vladimir Oltean wrote:
> > Sorry for getting back late to you. It did not compute when I read your
> > email the first time around, then I let it sit for a while.
> >
> > On Thu, Nov 05,
On Tue, 10 Nov 2020 at 17:32, Arpitha Raghunandan <98.a...@gmail.com> wrote:
>
> On 10/11/20 4:05 pm, Marco Elver wrote:
> > On Tue, 10 Nov 2020 at 08:21, David Gow wrote:
> > [...]
>
> The previous attempt [1] at something similar failed because it seems
> we'd need to teach kunit-
401 - 500 of 1567 matches
Mail list logo
