fdt_appendprop_addrrange() function adds a property, with the given name,
to the device tree at the given node offset, and also sets the address
and size of the property. This function should be used to add
"linux,ima-kexec-buffer" property to the device tree and set the address
and size of the IMA
The functions defined in "arch/powerpc/kexec/ima.c" handle setting up
and freeing the resources required to carry over the IMA measurement
list from the current kernel to the next kernel across kexec system call.
These functions do not have architecture specific code, but are
currently limited to p
Address and size of the buffer containing the IMA measurement log need
to be passed from the current kernel to the next kernel on kexec.
Any existing "linux,ima-kexec-buffer" property in the device tree
needs to be removed and its corresponding memory reservation in
the currently running kernel ne
On kexec file load Integrity Measurement Architecture (IMA) subsystem
may verify the IMA signature of the kernel and initramfs, and measure
it. The command line parameters passed to the kernel in the kexec call
may also be measured by IMA. A remote attestation service can verify
a TPM quote based o
On Thu, 17 Dec 2020 14:37:28 +0200 stef...@marvell.com wrote:
> From: Stefan Chulski
>
> During GoP port 2 Networking Complex Control mode of operation configurations,
> also GoP port 3 mode of operation was wrongly set.
> Patch removes these configurations.
> GENCONF_CTRL0_PORTX naming also fixe
delete_fdt_mem_rsv() defined in "arch/powerpc/kexec/file_load.c"
has been renamed to fdt_find_and_del_mem_rsv(), and moved to
"drivers/of/kexec.c".
Remove delete_fdt_mem_rsv() in "arch/powerpc/kexec/file_load.c".
Co-developed-by: Prakhar Srivastava
Signed-off-by: Prakhar Srivastava
Signed-off-b
create_dtb() function allocates memory for the device tree blob (DTB)
and calls fdt_open_into(). If this call fails the memory allocated
for the DTB is not freed before returning from create_dtb() thereby
leaking memory.
Call vfree() to free the memory allocated for the DTB if fdt_open_into()
fail
On Fri, 18 Dec 2020 04:36:18 +0100 Marcin Wojtas wrote:
> czw., 17 gru 2020 o 15:54 napisał(a):
> >
> > From: Stefan Chulski
> >
> > Force link UP can be enabled by bootloader during tftpboot
> > and breaks NFS support.
> > Force link UP disabled during port init procedure.
> >
> > Fixes: f84bf38
On Thu, 17 Dec 2020 18:07:58 +0200 stef...@marvell.com wrote:
> From: Stefan Chulski
>
> Patch didn't fix any issue, just improve parse flow
> and align ipv4 parse flow with ipv6 parse flow.
>
> Currently ipv4 kenguru parser first check IP protocol(TCP/UDP)
> and then destination IP address.
> P
On Thu, 17 Dec 2020 20:30:17 +0200 stef...@marvell.com wrote:
> From: Stefan Chulski
>
> Issue:
> Flow control frame used to pause GoP(MAC) was delivered to the CPU
> and created a load on the CPU. Since XOFF/XON frames are used only
> by MAC, these frames should be dropped inside MAC.
>
> Fix:
Hello,
syzbot found the following issue on:
HEAD commit:5e60366d Merge tag 'fallthrough-fixes-clang-5.11-rc1' of g..
git tree: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
usb-testing
console output: https://syzkaller.appspot.com/x/log.txt?x=17386d3750
kernel conf
Kconfig expands a macro to a string. $(error-if,...) should be expanded
to an empty string, not NULL.
Fixes: 1d6272e6fe43 ("kconfig: add 'info', 'warning-if', and 'error-if'
built-in functions")
Signed-off-by: Masahiro Yamada
---
scripts/kconfig/preprocess.c | 2 +-
1 file changed, 1 insertion
On Fri, 18 Dec 2020 12:20:19 +0800 weichenchen wrote:
> pneigh_enqueue() tries to obtain a random delay by mod
> NEIGH_VAR(p, PROXY_DELAY). However, NEIGH_VAR(p, PROXY_DELAY)
> migth be zero at that point because someone could write zero
> to /proc/sys/net/ipv4/neigh/[device]/proxy_delay after the
Hi Marco,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 3644e2d2dda78e21edd8f5415b6d7ab03f5f54f3
commit: 5106dfeaeabea73d5132daab1d89d57b57fa98b7 crypto: qat - add AES-XTS
support for QAT GEN4 devices
date: 8 da
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Thu, 17 Dec 2020 20:37:46 +0200 you wrote:
> From: Stefan Chulski
>
> Current PPPoE+IPv6 entry is jumping to 'next-hdr'
> field and not to 'DIP' field as done for IPv4.
>
> Fixes: 3f518509dedc ("ethernet: Add new driver fo
This reverts commit 14dc3983b5dff513a90bd5a8cc90acaf7867c3d0.
Macro Elver had sent a fix proper fix earlier, and also pointed out
corner cases:
"I guess what you propose is simpler, but might still have corner cases
where we still get warnings. In particular, if some file (for whatever
reason) do
On Sat, Dec 19, 2020 at 3:50 AM Linus Torvalds
wrote:
>
> On Wed, Dec 16, 2020 at 12:23 PM Kees Cook wrote:
> >
> > Hmm. Yeah, that's a bug. I think that's an existing bug, though. I feel
> > like I scratched my head on that too. I will see if there is a sensible
> > way to have Kbuild "notice" t
On Fri, Dec 18, 2020 at 11:46 PM Leizhen (ThunderTown)
wrote:
>
>
>
> On 2020/12/19 10:41, Dan Williams wrote:
> > There are multiple locations that open-code the release of the last
> > range in a device-dax instance. Consolidate this into a new
> > dev_dax_trim_range() helper.
> >
> > This also
On Sat, Dec 19, 2020 at 2:25 AM Daniel Scally wrote:
> On 18/12/2020 21:17, Andy Shevchenko wrote:
> > On Thu, Dec 17, 2020 at 11:43:37PM +, Daniel Scally wrote:
...
> >> +sensor->ep_properties[0] =
> >> PROPERTY_ENTRY_U32(sensor->prop_names.bus_type, 4);
> >
> > Does 4 has any meaning
When searching for inactive maintainers it's useful to filter
out mailing list addresses. Such "maintainers" will obviously
never feature in a "From:" line of an email or a review tag.
Since "L:" entries only provide the address of a mailing list
without a fancy name extend this pattern to "M:" en
On Wed, Dec 16, 2020 at 9:46 AM Chang S. Bae wrote:
>
> Key Locker [1][2] is a new security feature available in new Intel CPUs to
> protect data encryption keys for the Advanced Encryption Standard
> algorithm. The protection limits the amount of time an AES key is exposed
> in memory by sealing
On Sun, Dec 20, 2020 at 01:37:07AM +0800, kernel test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
> dev.2020.12.15b
> head: f895a17eec290b0038a6294d884a9cc92d7d6e80
> commit: 892f898ac8cfffe89e3c7fd483c8eaf71b3f12aa [128/134] rcutorture: Test
> r
Document bindings for the Texas Instruments TPS23861 driver.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
.../bindings/hwmon/ti,tps23861.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml
dif
Add maintainers entry for the Texas Instruments TPS23861 PoE PSE driver.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 830244166a7c..5441be7a5c26 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
Add basic monitoring support as well as port on/off control for Texas
Instruments TPS23861 PoE PSE IC.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
Changes in v2:
* Convert to devm_hwmon_device_register_with_info()
* Change license
drivers/hwmon/Kconfig| 11 +
drivers/hwmon/Makefile
On Thu, Dec 17, 2020 at 08:51:28AM +0100, Steen Hegelund wrote:
> +static struct sparx5_io_resource sparx5_iomap[] = {
This could be made const i think,.
> + { TARGET_DEV2G5, 0, 0 }, /* 0x610004000: dev2g5_0 */
> + { TARGET_DEV5G, 0x4000,0 }, /* 0x610008000:
On Fri, Dec 18, 2020 at 3:50 PM Guenter Roeck wrote:
>
> On 12/18/20 5:03 AM, Robert Marko wrote:
> > Add basic monitoring support as well as port on/off control for Texas
> > Instruments TPS23861 PoE PSE IC.
> >
> > Signed-off-by: Robert Marko
> > Cc: Luka Perkov
> > ---
> > drivers/hwmon/Kcon
Hello,
On Fri, Dec 18, 2020 at 08:30:06PM -0800, Nadav Amit wrote:
> Analyzing this problem indicates that there is a real bug since
> mmap_lock is only taken for read in mwriteprotect_range(). This might
Never having to take the mmap_sem for writing, and in turn never
blocking, in order to modif
On 12/19, Pedro Alves wrote:
>
> BTW, the problem was discovered by Simon Marchi when he tried to write
> a GDB testcase for a multi-threaded exec scenario:
OOPS! Sorry Simon, yes I forgot to add reported-by. Andrew, or Eric, if
you take this patch, could you also add
Reported-by: Simon M
Quoting Rob Herring (2020-12-18 12:13:50)
> On Thu, Dec 17, 2020 at 02:28:53AM -0800, Stephen Boyd wrote:
> > Quoting Zhen Lei (2020-12-06 20:55:27)
> > > Eliminate the following yamllint warnings:
> > > ./Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
> > > :32:13:[warning] wrong indent
Quoting Nicolas Saenz Julienne (2020-12-02 02:35:18)
> Add MODULE_DEVICE_TABLE() so as to be able to use the driver as a
> module. More precisely, for the driver to be loaded automatically at
> boot.
>
> Fixes: 1bc95972715a ("clk: bcm: Add BCM2711 DVP driver")
> Signed-off-by: Nicolas Saenz Julien
On Fri, Dec 18, 2020 at 4:57 PM Thierry Reding wrote:
>
> I didn't realize that this would show up as all new commits. The reason
> why this happens is because the first commit in the tree is a fix for an
> issue for which Uwe had sent an alternative patch to you directly for
> inclusion in v5.10.
Quoting Claudiu Beznea (2020-11-19 07:43:07)
> pmc_data_allocate() has been changed. pmc_data_free() was removed.
> Adapt the code taking this into consideration. With this the programmable
> clocks were also saved in sama7g5_pmc so that they could be later
> referenced.
>
> Fixes: cb783bbbcf54 ("
Quoting Claudiu Beznea (2020-11-19 07:43:08)
> From: Eugen Hristev
>
> Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
> PMC_TYPE_CORE clock.
>
> Suggested-by: Claudiu Beznea
> Signed-off-by: Eugen Hristev
> [claudiu.bez...@microchip.com: adapt comit message, adapt sama7g5.
Quoting Claudiu Beznea (2020-11-19 07:43:09)
> From: Eugen Hristev
>
> Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
> from phandle in DT.
>
> Suggested-by: Claudiu Beznea
> Signed-off-by: Eugen Hristev
> [claudiu.bez...@microchip.com: adapt commit message, add CPU PLL]
> S
> + /* Create a phylink for PHY management. Also handles SFPs */
> + spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
> + spx5_port->phylink_config.type = PHYLINK_NETDEV;
> + spx5_port->phylink_config.pcs_poll = true;
> +
> + /* phylink needs a valid interface mode to par
Quoting Claudiu Beznea (2020-11-19 07:43:11)
> From: Eugen Hristev
>
> This SoC has the 5th divisor for the mck0 master clock.
> Adapt the characteristics accordingly.
>
> Reported-by: Mihai Sain
> Signed-off-by: Eugen Hristev
> Signed-off-by: Claudiu Beznea
> ---
Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:10)
> From: Eugen Hristev
>
> clk-master can have 5 divisors with a field width of 3 bits
> on some products.
>
> Change the mask and number of divisors accordingly.
>
> Reported-by: Mihai Sain
> Signed-off-by: Eugen Hristev
> Signed-off-by: Claudiu Be
Quoting Claudiu Beznea (2020-11-19 07:43:12)
> Allow runtime frequency changes for PLLs registered with proper flags.
> This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
>
> Signed-off-by: Claudiu Beznea
> ---
Applied to clk-next
changes v6:
- move stats64 callback to ethtool section
- ar9331: diff. fixes
- ar9331: move stats calculation to the worker
- ar9331: extend rx/tx error counters
- use spin lock instead of u64_stats*
changes v5:
- read all stats in one regmap_bulk_read() request
- protect stats with u64_stats* hel
Add stats support for the ar9331 switch.
Signed-off-by: Oleksij Rempel
---
drivers/net/dsa/qca/ar9331.c | 163 ++-
1 file changed, 162 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/qca/ar9331.c b/drivers/net/dsa/qca/ar9331.c
index 4d49c5f2b790..896fb2
Allow DSA drivers to export stats64
Signed-off-by: Oleksij Rempel
Reviewed-by: Vladimir Oltean
---
include/net/dsa.h | 4 +++-
net/dsa/slave.c | 14 +-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 4e60d2610f20..c50abb
On Sat, Dec 19, 2020 at 4:41 AM Kirill A. Shutemov wrote:
>
> Okay, but we only win the NULL check. xas_retry() and xa_is_value() has to
> be repeated in the beginning of the loop.
Yeah.
I wonder if it might make sense to have a "xas_next_entry_rcu()"
function that does something like
while
On Fri, Dec 18, 2020 at 06:00:49PM +0200, Andy Shevchenko wrote:
> On Wed, Dec 16, 2020 at 12:42 AM Drew Fustini wrote:
> > On Tue, Dec 15, 2020 at 09:39:18PM +0200, Andy Shevchenko wrote:
> > > On Tue, Dec 15, 2020 at 9:36 PM Andy Shevchenko
> > > wrote:
> > > > On Mon, Dec 14, 2020 at 11:44 PM
On 2020-12-19 10:55, Jakub Kicinski wrote:
When searching for inactive maintainers it's useful to filter
out mailing list addresses. Such "maintainers" will obviously
never feature in a "From:" line of an email or a review tag.
Since "L:" entries only provide the address of a mailing list
withou
> + port13: port@13 {
> + reg = <13>;
> + /* Example: CU SFP, 1G speed */
> + max-speed = <1>;
One too many 0's for 1G.
> + /* 25G SFPs */
> + port56: port@56 {
> + reg = <56>;
On 03/12/2020 17:15, Coly Li wrote:
This patch is an initial effort to improve badblocks_set() for setting
bad blocks range when it covers multiple already set bad ranges in the
bad blocks table, and to do it as fast as possible.
Is this your patch, or submitted as part of the bug report?
"Hea
On Sat, Dec 19, 2020 at 4:41 AM Kirill A. Shutemov wrote:
>
> @@ -2884,19 +2966,18 @@ void filemap_map_pages(struct vm_fault *vmf,
> if (vmf->pte)
> vmf->pte += xas.xa_index - last_pgoff;
> last_pgoff = xas.xa_index;
> - if (all
Em Wed, Dec 16, 2020 at 10:58:01AM -0800, kan.li...@linux.intel.com escreveu:
> From: Kan Liang
>
> Add option --data-page-size in "perf mem" to record/report data page
> size.
>
> Here are some examples.
> perf mem --phys-data --data-page-size report -D
So I stopped at this cset, it isn't appl
Recently introduced async probe on mmc devices can shuffle block IDs.
Pin them to fixed values to ease booting in environments where UUIDs
are not practical. Use newly introduced aliases for mmcblk devices from [1].
[1] https://patchwork.kernel.org/patch/11747669/
Signed-off-by: Johan Jonker
---
The pull request you sent on Fri, 18 Dec 2020 17:04:01 +0100:
> git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git
> tags/pwm/for-5.11-rc1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/d56154c7e8ba090126a5a2cb76098628bc2216a2
Thank you!
--
The pull request you sent on Sat, 19 Dec 2020 08:06:32 +0100:
> git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git tags/i3c/for-5.11
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/190daf19206783bb16655db14e604a0d724c4bbf
Thank you!
--
Deet-doot-dot, I am a
The pull request you sent on Sat, 19 Dec 2020 00:59:10 +0100:
> ssh://g...@gitolite.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi.git
> tags/hsi-for-5.11
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/c2703b66172fff39122012e42986b44c9c6ad5f1
Thank you!
--
Deet-
The pull request you sent on Sat, 19 Dec 2020 07:31:36 +0100:
> git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git
> for-linus-5.11-rc1b-tag
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/3872f516aab34e3adeb7eda43b29c1ecd852cee1
Thank you!
--
Deet-doot-dot,
The pull request you sent on Sat, 19 Dec 2020 00:59:14 +0100:
> ssh://g...@gitolite.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git
> tags/for-v5.11
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/11c336526e2504d34c70fcf11a3642ae333a5085
Thank you!
--
The pull request you sent on Sat, 19 Dec 2020 16:58:21 +0100:
> g...@gitolite.kernel.org:pub/scm/linux/kernel/git/brauner/linux
> tags/close-range-cloexec-unshare-v5.11
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/467f8165a2b0e6accf3d0dd9c8089b1dbde29f7f
Thank you!
The pull request you sent on Sat, 19 Dec 2020 08:18:38 +0100:
> https://git.kernel.org/pub/scm/linux/kernel/git/brodo/linux.git pcmcia-next
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/651283d57eb4107f4a81af282064e597e2f9b181
Thank you!
--
Deet-doot-dot, I am a bo
Hi Linus,
could you please pull the following gfs2 changes for 5.11?
Thanks a lot,
Andreas
The following changes since commit dd0ecf544125639e54056d851e4887dbb94b6d2f:
gfs2: Fix deadlock between gfs2_{create_inode,inode_lookup} and
delete_work_func (2020-12-01 00:21:10 +0100)
are available
On Sat, 2020-12-19 at 13:57 +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.10.2 release.
> There are 16 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied,
> please
> let me know.
>
>
Am Donnerstag, 17. Dezember 2020, 04:07:30 CET schrieb yumeng:
Hi yumeng,
>
> I see in "SEC 2: Recommended Elliptic Curve Domain ParametersVersion2.0"
> that 'Recommend Elliptic Curve Domain Parameters over Fp' are secp192,
> secp224, secp256, secp384, and secp521, secp128 and secp320 are not
>
[ cc’ing some more people who have experience with similar problems ]
> On Dec 19, 2020, at 11:15 AM, Andrea Arcangeli wrote:
>
> Hello,
>
> On Fri, Dec 18, 2020 at 08:30:06PM -0800, Nadav Amit wrote:
>> Analyzing this problem indicates that there is a real bug since
>> mmap_lock is only taken
Le 18/12/2020 à 19:59, Marc Zyngier a écrit :
Hi Christophe,
On Tue, 15 Dec 2020 20:07:47 +,
Christophe JAILLET wrote:
Add a description for 'irq_create_of_mapping()' and make explicit the fact
that the resources allocated by this function can be freed by calling
'irq_dispose_mapping()'
Hi all,
On Fri, Dec 18, 2020 at 07:43:34PM +0100, Sam Ravnborg wrote:
> The sun4m and sun4d based SPARC machines was very popular in the
> 90'ties and was then replaced by the more powerful sparc64
> class of machines.
I have received a couple of mails in private.
One said it was better to sunset
On Sat, Dec 19, 2020 at 01:58:04PM +0100, Greg Kroah-Hartman wrote:
> --
> Note, I would like to make this the past, or next-to-last 5.9.y kernel
> to be released. If anyone knows of any reason they can not move to the
> 5.10.y kernel now, please let me know!
> --
>
On Sat, Dec 19, 2020 at 02:02:57PM +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.4.85 release.
> There are 34 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
Hi!
> From: Martin Blumenstingl
>
> [ Upstream commit 82ca4c922b8992013a238d65cf4e60cc33e12f36 ]
>
> The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by
> shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in
> struct clk_mux expects the mask relative to the "
On Sat, Dec 19, 2020 at 01:57:07PM +0100, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.10.2 release.
> There are 16 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
On 12/19/20 10:40 PM, Sam Ravnborg wrote:
> Please keep the inputs coming independent if you are pro or not
> for the sunset of sun4m and sun4d.
I would personally be in favor of keeping it and I should finally get
my SPARCstation 5 up and running again.
Adrian
--
.''`. John Paul Adrian Glaub
> On Dec 19, 2020, at 1:34 PM, Nadav Amit wrote:
>
> [ cc’ing some more people who have experience with similar problems ]
>
>> On Dec 19, 2020, at 11:15 AM, Andrea Arcangeli wrote:
>>
>> Hello,
>>
>> On Fri, Dec 18, 2020 at 08:30:06PM -0800, Nadav Amit wrote:
>>> Analyzing this problem indic
Hello Linus,
Here is the RTC pull request for 5.11. There is a non trivial conflict
with the tip tree in include/linux/rtc.h. This is properly solved in
linux-next, see:
https://lore.kernel.org/linux-next/20201214190704.78b44...@canb.auug.org.au/
The following changes since commit 3650b228f83add
: powerpc-randconfig-r021-20201219 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
cee1e7d14f4628d6174b33640d502bff3b54ae45)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin
Hi Pavel,
On Sat, Dec 19, 2020 at 10:51 PM Pavel Machek wrote:
[...]
> I can't say I like this one:
>
>
> > clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
> > - clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
> > - clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_M
Hi Arnd,
On Sat, Dec 19, 2020 at 03:08:14PM +0100, Arnd Bergmann wrote:
> ,On Sat, Dec 19, 2020 at 2:15 PM syzbot
> wrote:
> >
> > Hello,
> >
> > syzbot found the following issue on:
> >
> > HEAD commit:a409ed15 Merge tag 'gpio-v5.11-1' of git://git.kernel.org/..
> > git tree: upstream
Fixed a checkpatch warning:
WARNING: Block comments use * on subsequent lines
#4595: FILE: drivers/staging/rtl8188eu/core/rtw_mlme_ext.c:4595:
+/
+
The code is full of comments like this. Should the coding style
be infor
Hi Linus,
Please consider pulling,
Best regards,
- Arnaldo
The following changes since commit accefff5b547a9a1d959c7e76ad539bf2480e78b:
Merge tag 'arm-soc-omap-genpd-5.11' of
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc (2020-12-16 16:53:54
-0800)
are available in the Git
On 12/16/20 9:30 AM, tudor.amba...@microchip.com wrote:
On 12/15/20 11:46 PM, Bert Vermeulen wrote:
This driver supports the spiflash core in all RTL838x/RTL839x SoCs,
and likely some older models as well (RTL8196C).
Can we use SPIMEM and move this under drivers/spi/ instead?
I wasn't aware
On Sat 2020-12-19 23:38:25, Martin Blumenstingl wrote:
> Hi Pavel,
>
> On Sat, Dec 19, 2020 at 10:51 PM Pavel Machek wrote:
> [...]
> > I can't say I like this one:
> >
> >
> > > clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
> > > - clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_
On 19/12/2020 00:39, Laurent Pinchart wrote:
> Hi Daniel,
>
> On Fri, Dec 18, 2020 at 11:57:54PM +, Daniel Scally wrote:
>> Hi Laurent - thanks for the comments
>>
>> On 18/12/2020 16:53, Laurent Pinchart wrote:
+static void cio2_bridge_init_property_names(struct cio2_sensor *sensor)
> +void sparx5_get_stats64(struct net_device *ndev,
> + struct rtnl_link_stats64 *stats)
> +{
> + struct sparx5_port *port = netdev_priv(ndev);
> + struct sparx5 *sparx5 = port->sparx5;
> + u64 *portstats;
> +
> + if (!sparx5->stats)
> + return;
Quoting Claudiu Beznea (2020-11-19 07:43:11)
> From: Eugen Hristev
>
> This SoC has the 5th divisor for the mck0 master clock.
> Adapt the characteristics accordingly.
>
> Reported-by: Mihai Sain
> Signed-off-by: Eugen Hristev
> Signed-off-by: Claudiu Beznea
> ---
Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:12)
> Allow runtime frequency changes for PLLs registered with proper flags.
> This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
>
> Signed-off-by: Claudiu Beznea
> ---
Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:13)
> MCK0 is changed at runtime by DVFS. Due to this, since not all IPs
> are glitch free aware at MCK0 changes, remove MCK0 from parent list
> of other clocks (e.g. generic clock, programmable/system clock, MCKX).
>
> Signed-off-by: Claudiu Beznea
> ---
Quoting Claudiu Beznea (2020-11-19 07:43:15)
> Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
> than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
> 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
>
> Signed-off-by: Claudiu Beznea
> ---
Applie
Quoting Claudiu Beznea (2020-11-19 07:43:16)
> Re-factor master clock driver by splitting it into 2 clocks: prescaller
> and divider clocks. Based on registered clock flags the prescaler's rate
> could be changed at runtime. This is necessary for platforms supporting
> DVFS (e.g. SAMA7G5) where mas
Quoting Claudiu Beznea (2020-11-19 07:43:17)
> Register CPU clock as being the master clock prescaler. This would
> be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
> between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
> frequencies supported by SAMA7G5 co
Quoting Alexandre Belloni (2020-12-02 04:58:15)
> The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
> bypass.
>
> Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
> Reported-by: Claudiu Beznea
> Signed-off-by: Alexandre Belloni
> ---
Applied to clk-next
On 18/12/2020 20:29, Andy Shevchenko wrote:
>> + * Register multiple software nodes at once. If any node in the array
>> + * has it's .parent pointer set, then it's parent **must** have been
>
> it's => its in both cases?
Done, ty
>> + * registered before it is; either outside of this function o
Quoting Claudiu Beznea (2020-11-19 07:43:14)
> On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
> CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
> also changed by DVFS to avoid over/under clocking of MCK0 consumers.
> The lower limit is changed to be able to se
Quoting Kiran Gunda (2020-12-18 00:14:51)
> Convert the bindings from .txt to .yaml format.
>
> Signed-off-by: Kiran Gunda
> ---
> .../devicetree/bindings/mfd/qcom,spmi-pmic.txt | 80 -
> .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml| 127
> +
> 2 file
On 19/12/2020 18:52, Andy Shevchenko wrote:
> On Sat, Dec 19, 2020 at 2:25 AM Daniel Scally wrote:
>> On 18/12/2020 21:17, Andy Shevchenko wrote:
>>> On Thu, Dec 17, 2020 at 11:43:37PM +, Daniel Scally wrote:
>
> ...
>
+sensor->ep_properties[0] =
PROPERTY_ENTRY_U32(sensor->pro
Quoting Sascha Hauer (2020-11-30 01:10:33)
> Documentation states that SI5351_PLL_RESET_B and SI5351_PLL_RESET_A bits
> are self clearing bits, so wait until they are cleared before
> continuing.
> This fixes a case when the clock doesn't come up properly after a PLL
> reset. It worked properly whe
Quoting Kiran Gunda (2020-12-18 00:14:52)
> Add the compatibles and PMIC ids for pm6150 and pm6150l PMICs
> found on SC7180 based platforms.
>
> Signed-off-by: Kiran Gunda
> ---
Reviewed-by: Stephen Boyd
On 12/19/20 7:22 AM, Pavel Tatashin wrote:
...
Add a new test to gup_test, to verify that only "pinnable" pages are
pinned. Also, use gup/pup + FOLL_TOUCH to fault in the pages, rather
than faulting them in from user space.
OK
? But I don't know why that second point is important. Is it ac
On Sat, 2020-12-19 at 11:23 -0500, Tejun Heo wrote:
> Hello,
>
> On Sat, Dec 19, 2020 at 03:08:13PM +0800, Ian Kent wrote:
> > And looking further I see there's a race that kernfs can't do
> > anything
> > about between kernfs_refresh_inode() and fs/inode.c:update_times().
>
> Do kernfs files end
Quoting Pali Rohár (2020-11-06 02:00:39)
> From: Terry Zhou
>
> There is an error in the current code that the XTAL MODE
> pin was set to NB MPP1_31 which should be NB MPP1_9.
> The latch register of NB MPP1_9 has different offset of 0x8.
>
> Signed-off-by: Terry Zhou
> [pali: Fix pin name in c
Quoting Christophe JAILLET (2020-12-12 04:28:18)
> Some resource should be released in the error handling path of the probe
> function, as already done in the remove function.
>
> The remove function was fixed in commit bf416bd45738 ("clk: s2mps11: Add
> missing of_node_put and of_clk_del_provider
Quoting Jernej Skrabec (2020-12-02 12:38:17)
> Two clock divider tables are missing sentinel at the end. Effect of that
> is that clock framework reads past the last entry. Fix that with adding
> sentinel at the end.
>
> Issue was discovered with KASan.
>
> Fixes: 0577e4853bfb ("clk: sunxi-ng: Ad
Quoting Enrico Weigelt, metux IT consult (2020-12-02 04:34:46)
> The gpio-gate-clock / gpio-mux-clock driver isn't used much,
> just by a few ARM SoCs, so there's no need to always include
> it unconditionally.
>
> Thus make it optional, but keep it enabled by default.
>
> changes v3: default to
Quoting Paul Cercueil (2020-12-12 05:57:33)
> The previous code assumed that a higher hardware value always resulted
> in a bigger divider, which is correct for the regular clocks, but is
> an invalid assumption when a divider table is provided for the clock.
>
> Perfect example of this is the PLL
Quoting Geert Uytterhoeven (2020-12-18 04:52:53)
> Commit 45c940184b501fc6 ("dt-bindings: clk: versaclock5: convert to
> yaml") accidentally changed "idt,voltage-microvolts" to
> "idt,voltage-microvolt" in the DT bindings, while the driver still used
> the former.
>
> Update the driver to match th
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