On 4/19/21 10:50 PM, Zev Weiss wrote:
[ ... ]
> I had a glance at the enclosure driver; it looks pretty geared toward
> SES-like things (drivers/scsi/ses.c being its only usage I can see in the
> kernel at the moment) and while it could perhaps be pressed into working for
> this it seems like
On Tue, 20 Apr 2021 at 00:59, Paolo Bonzini wrote:
>
> On 19/04/21 18:32, Sean Christopherson wrote:
> > If false positives are a big concern, what about adding another pass to the
> > loop
> > and only yielding to usermode vCPUs with interrupts in the second full pass?
> > I.e. give vCPUs that
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
both implement "arm,mmu-500" in some QTI SoCs and to run through
adreno smmu specific implementation such as enabling split pagetables
support, we need to match the "qcom,adreno-smmu" compatible first
before apss smmu or else we will
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Note that dt-binding for sc7280 is already merged.
Changes in v3:
* Collect acks and reviews
* Rebase on top of for-joerg/arm-smmu/updates
Changes in
On 2021-04-19 20:08, Bjorn Andersson wrote:
On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote:
Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
both implement "arm,mmu-500" in some QTI SoCs and to run through
adreno smmu specific implementation such as enabling split
On Tue, 20 Apr 2021 at 14:02, Wanpeng Li wrote:
>
> On Tue, 20 Apr 2021 at 00:59, Paolo Bonzini wrote:
> >
> > On 19/04/21 18:32, Sean Christopherson wrote:
> > > If false positives are a big concern, what about adding another pass to
> > > the loop
> > > and only yielding to usermode vCPUs
On Mon, Apr 19, 2021 at 05:30:49PM -0700, Rajat Jain wrote:
> The current flag name "untrusted" is not correct as it is populated
> using the firmware property "external-facing" for the parent ports. In
> other words, the firmware only says which ports are external facing, so
> the field really
On Tue, Apr 20, 2021 at 07:56:18AM +0200, Greg Kroah-Hartman wrote:
> I would LOVE it if some "executives" would see the above presentations,
> because then they would maybe actually fund developers to fix bugs and
> maintain the kernel code, instead of only allowing them to add new
> features.
>
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
Add suspend_noirq and resume_noirq callback functions to implement PM
system suspend and resume hooks for the MediaTek Gen3 PCIe controller.
When the system suspends, trigger the PCIe link to enter the L2 state
and pull down the PERST# pin, gating the clocks of the MAC layer, and
then power-off
Add MSI support for MediaTek Gen3 PCIe controller.
This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:
+-+
| GIC |
+-+
^
|
Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..8050c14e6a7a 100644
--- a/MAINTAINERS
+++
From: mtk15901
These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.
Changes in v10:
1. Fix the subject line format in commit message;
2. Use EXPORT_SYMBOL_GPL() to export pci_pio_to_address().
Changes in v9:
1. Use mtk_pcie_parse_port()
Add INTx support for MediaTek Gen3 PCIe controller.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
Reviewed-by: Marc Zyngier
---
drivers/pci/controller/pcie-mediatek-gen3.c | 172
1 file changed, 172 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.
Signed-off-by: Jianjun Wang
Acked-by: Bjorn Helgaas
---
drivers/pci/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci.c
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
Reviewed-by: Rob Herring
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 181 ++
1 file changed, 181 insertions(+)
create mode 100644
On 4/19/21 9:42 PM, Robert Hancock wrote:
> Previously the XILINX_INTC config option was hidden and only
> auto-selected on the MicroBlaze platform. However, this IP can also be
> used on the Zynq and ZynqMP platforms as a secondary cascaded
> controller. Allow this option to be user-enabled on
Hi Varad,
Thanks for your review!
On Thu, Apr 15, 2021 at 02:08:32PM +0200, Varad Gautam wrote:
> Hi Joey,
>
> On 4/9/21 4:46 AM, Lee, Chun-Yi wrote:
> > This patch adds the logic for checking the CodeSigning extended
> > key usage when verifying signature of kernel module or
> > kexec PE
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git
auto-latest
branch HEAD: e48f64fea89e61301248c4be02b406d934a4bac3 Merge branch 'core/entry'
elapsed time: 1157m
configs tested: 156
configs skipped: 3
The following configs have been built successfully.
More configs
On Mon, 19 Apr 2021 at 18:39, Greg Kroah-Hartman
wrote:
>
> This is the start of the stable review cycle for the 5.11.16 release.
> There are 122 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On Mon, 19 Apr 2021 16:43:36 -0400
Sasha Levin wrote:
> This first appeared with commit e5c02cf54154 ("i2c: mv64xxx: Add runtime
> PM support").
I forgot to add Fixes: tag to this commit. But the bug first appeared with
commit
e5c02cf54154 ("i2c: mv64xxx: Add runtime PM support")
which is in
Hi Zou,
Zou Wei writes:
> The sparse tool complains as follows:
>
> tools/testing/nvdimm/test/iomap.c:65:14: warning:
> symbol '__nfit_test_ioremap' was not declared. Should it be static?
>
> This symbol is not used outside of security.c, so this
s/security.c/iomap.c/
Thanks,
Santosh
>
On 2021-04-19 20:02, Bjorn Andersson wrote:
On Mon 19 Apr 05:32 CDT 2021, schow...@codeaurora.org wrote:
On 2021-04-15 12:01, Felipe Balbi wrote:
> Hi,
>
> Souradeep Chowdhury writes:
> > diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> > index ad675a6..e7f0ccb 100644
> >
This mostly reverts commit 99bca615d895 ("MIPS: pci-legacy: use generic
pci_enable_resources"). Fixes regressions such as:
ata_piix :00:0a.1: can't enable device: BAR 0 [io 0x01f0-0x01f7] not
claimed
ata_piix: probe of :00:0a.1 failed with error -22
The only changes from the
Hi，
Just a gentle ping, hope some expert could take a look, thanks.
Best regards.
Dillon
On Thu, Apr 15, 2021 at 12:05 PM wrote:
>
> From: dillon min
>
> The DaSheng Com-9xx is and ARM based signle board computer (SBC)
> featuring:
> - i.MX6Q
> - 2GiB LPDDR3 DRAM
> - 8GiB eMMC 5.0 FLASH
> -
On Mon, Apr 19 2021 at 20:12, Maciej Żenczykowski wrote:
> On Thu, Apr 15, 2021 at 9:47 AM Thomas Gleixner wrote:
>> Run the test on a kernels with and without that commit and collect trace
>> data for both.
>>
>> That should give me a pretty clear picture what's going on.
>
> Lorenzo is trying
On Mon 19-04-21 18:44:02, Shakeel Butt wrote:
> Proposal: Provide memory guarantees to userspace oom-killer.
>
> Background:
>
> Issues with kernel oom-killer:
> 1. Very conservative and prefer to reclaim. Applications can suffer
> for a long time.
> 2. Borrows the context of the allocator which
Hi All,
Just a gentle ping, hope some expert could take a look, thanks.
Best regards.
Dillon
On Thu, Apr 15, 2021 at 12:06 PM wrote:
>
> From: dillon min
>
> On some platform(imx6q), xvclk might not switch on in advance,
> also for power save purpose, xvclk should not be always on.
> so, add
On Mon, 19 Apr 2021 at 18:49, Greg Kroah-Hartman
wrote:
>
> This is the start of the stable review cycle for the 5.10.32 release.
> There are 103 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
Christophe Leroy wrote:
For that, create a 32 bits version of patch_imm64_load_insns()
and create a patch_imm_load_insns() which calls
patch_imm32_load_insns() on PPC32 and patch_imm64_load_insns()
on PPC64.
Adapt optprobes_head.S for PPC32. Use PPC_LL/PPC_STL macros instead
of raw ld/std, opt
On Tue, 20 Apr 2021 at 08:46, dillon min wrote:
>
> Hi All,
>
> Just a gentle ping, hope some expert could take a look, thanks.
Don't ping people after 5 days. It's not gentle.
Best regards,
Krzysztof
On 20/04/21 07:45, Shivank Garg wrote:
Hi,
I'm learning about qemu KVM, looking into code and experimenting on
it. I have the following doubts regarding it, I would be grateful if
you help me to get some idea on them.
1. I observe that KVM allocates memory to guests when it needs it but
doesn't
On 18/04/21 14:43, Peter Xu wrote:
8<-
diff --git a/tools/testing/selftests/kvm/dirty_log_test.c
b/tools/testing/selftests/kvm/dirty_log_test.c
index 25230e799bc4..d3050d1c2cd0 100644
--- a/tools/testing/selftests/kvm/dirty_log_test.c
+++ b/tools/testing/selftests/kvm/dirty_log_test.c
On Tue, Apr 20, 2021 at 10:03:36AM +0800, Chen Yu wrote:
> On Mon, Apr 19, 2021 at 02:58:12PM -0500, Terry Bowman wrote:
> > Turbostat fails to correctly collect and display RAPL summary information
> > on Family 17h and 19h AMD processors. Running turbostat on these processors
> > returns
On Tue, Apr 20, 2021 at 07:33:39AM +, Y.b. Lu wrote:
> > > + /* For two-step timestamp, retrieve ptp_cmd in DSA_SKB_CB_PRIV
> > > + * and timestamp ID in clone->cb[0].
> > > + * For one-step timestamp, retrieve ptp_cmd in DSA_SKB_CB_PRIV.
> > > + */
> > > + u8 *ptp_cmd =
This patch adds the binding document for the zynqmp afi
config driver.
Signed-off-by: Nava kishore Manne
---
.../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++
1 file changed, 136 insertions(+)
create mode 100644
This patch adds zynqmp afi config driver.This is useful for
the configuration of the PS-PL interface on Zynq US+ MPSoC
platform.
Signed-off-by: Nava kishore Manne
---
drivers/misc/Kconfig | 11 ++
drivers/misc/Makefile | 1 +
drivers/misc/zynqmp-afi.c | 83
This patch adds zynq afi config driver. This is useful for
the configuration of the PS-PL interface on zynq platform.
Signed-off-by: Nava kishore Manne
---
drivers/misc/Kconfig| 11 ++
drivers/misc/Makefile | 1 +
drivers/misc/zynq-afi.c | 81 +
This patch adds afi ioctl to support dynamic PS-PL
bus width settings.
Signed-off-by: Nava kishore Manne
---
drivers/firmware/xilinx/zynqmp.c | 13 +
include/linux/firmware/xlnx-zynqmp.h | 7 +++
2 files changed, 20 insertions(+)
diff --git
From: Patrice Chotard
This fixes warnings detected when compiling in ARM64.
Introduced by 'commit 18674dee3cd6 ("spi: stm32-qspi: Add dirmap support")'
Signed-off-by: Patrice Chotard
---
drivers/spi/spi-stm32-qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 4/16/21 8:33 PM, Catalin Marinas wrote:
> On Fri, Apr 16, 2021 at 03:55:31PM +0800, He Zhe wrote:
>> The general version of is_syscall_success does not handle 32-bit
>> compatible case, which would cause 32-bit negative return code to be
>> recoganized as a positive number later and seen as
Hi Andy,
Thanks for further comments, see some answers/questions below.
thanks,
Tomas
On 4/19/21 4:55 PM, Andy Shevchenko wrote:
On Mon, Apr 19, 2021 at 4:26 PM Tomas Melin wrote:
Thanks for an update, it's getting better! My comments below.
Add initial support for Murata SCA3300 3-axis
On 15/04/21 17:53, Ashish Kalra wrote:
From: Brijesh Singh
The command is used to create an outgoing SEV guest encryption context.
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: Paolo Bonzini
Cc: Joerg Roedel
Cc: Borislav Petkov
Cc: Tom Lendacky
Cc: x...@kernel.org
Cc:
On Mon, Apr 19, 2021 at 10:18:07AM +0200, Krzysztof Kozlowski wrote:
> Remove trailing whitespaces. No functional change.
>
> Signed-off-by: Krzysztof Kozlowski
Both patches applied to drm-misc-next, thanks.
-Daniel
> ---
> drivers/gpu/drm/gma500/backlight.c| 4 +--
>
Hi,
Thanks for the fixes
On 18.04.21 12:34, Sebastian Fricke wrote:
Improve the wording of the function description to increase readability.
Fix three typos:
s/during processing a frame/while processing a frame/
s/it also update/it also updates/
s/there's not buf in shadow/there's no buffer in
Michael Kelley writes:
> When running in Azure, disks may be connected to a Linux VM with
> read/write caching enabled. If a VM panics and issues a VMbus
> UNLOAD request to Hyper-V, the response is delayed until all dirty
> data in the disk cache is flushed. In extreme cases, this flushing
>
On Mon, Apr 19, 2021 at 11:56:30AM +0100, Vincent Donnefort wrote:
> On Thu, Apr 15, 2021 at 03:32:11PM +0100, Valentin Schneider wrote:
> > On 15/04/21 10:59, Peter Zijlstra wrote:
> > > Can't make sense of what I did.. I've removed that hunk. Patch now looks
> > > like this.
> > >
> >
> > Small
On Fri 16-04-21 13:24:06, Oscar Salvador wrote:
> From: David Hildenbrand
>
> Let's have a single place (inspired by adjust_managed_page_count()) where
> we adjust present pages.
> In contrast to adjust_managed_page_count(), only memory onlining/offlining
> is allowed to modify the number of
On Tue, Apr 20, 2021 at 10:43:43AM +0100, Valentin Schneider wrote:
> On 20/04/21 10:51, Peter Zijlstra wrote:
> > I think free_kthread_struct() is ok, because a task at that point in its
> > lifetime cannot be also doing exec().
> >
>
> What if it's one of those kthreads created by directly
On Tue, Apr 20, 2021 at 10:48:33AM +0800, Bingbu Cao wrote:
> Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
> The IPU driver allocates its own page table that is not mapped
> via the DMA, and thus the Intel IOMMU driver blocks access giving
> this error:
>
> DMAR: DRHD: handling
From: Colin Ian King
The pointer mbox is being initialized with a value that is
never read and it is being updated later with a new value. The
initialization is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
On 20/04/21 01:06, Sean Christopherson wrote:
diff --git a/arch/x86/include/uapi/asm/kvm_para.h
b/arch/x86/include/uapi/asm/kvm_para.h
index 950afebfba88..f6bfa138874f 100644
--- a/arch/x86/include/uapi/asm/kvm_para.h
+++ b/arch/x86/include/uapi/asm/kvm_para.h
@@ -33,6 +33,7 @@
#define
From: Viorel Suman
Enable Daisy Chain if in TDM mode and the number of played
channels is bigger than the maximum supported number of channels.
Signed-off-by: Viorel Suman
Signed-off-by: Shengjiu Wang
---
sound/soc/codecs/ak4458.c | 47 ++-
Add a new MSR that can be used to communicate whether the page
encryption status bitmap is up to date and therefore whether live
migration of an encrypted guest is possible.
The MSR should be processed by userspace if it is going to live
migrate the guest; the default implementation does nothing.
Em Wed, Apr 14, 2021 at 11:07:39AM -0500, Rob Herring escreveu:
> x86 and arm64 can both support direct access of event counters in
> userspace. The access sequence is less than trivial and currently exists
> in perf test code (tools/perf/arch/x86/tests/rdpmc.c) with copies in
> projects such as
On Sun, Apr 18, 2021 at 11:02:33PM +0530, Saurav Girepunje wrote:
> on sdio_intf.c rtw_sdio_suspend call we have multiple
> return which can replace by goto exit. As in all the places
> return value is 0.
>
> Signed-off-by: Saurav Girepunje
> ---
> drivers/staging/rtl8723bs/os_dep/sdio_intf.c |
rsa-pkcs1pad operations that require using RSA primitives rely on
creating an akcipher child RSA transform and processing the results
in the operation-specific callback. Add helpers
rsapad_akcipher_setup_child and rsapad_akcipher_req_complete for req
setup and callback handling, and switch
Linux currently supports RSA PKCSv1.5 encoding scheme for
signing / verification. This adds support for RSASSA PSS signature
verification as described in RFC8017 [1].
Patch 1 extends the x509 certificate parser to unpack PSS signature
parameters.
Patches 2-8 pull out the common functions /
An X.509 wrapper for a RSASSA-PSS signature contains additional
signature parameters over the PKCSv.15 encoding scheme. Extend the
x509 parser to allow parsing RSASSA-PSS encoded certificates, with
the defaults taken from RFC8017.
References: https://tools.ietf.org/html/rfc8017#appendix-C
Use generic naming to share with other padding scheme implementations.
These will be moved out of rsa-pkcs1pad.c.
Signed-off-by: Varad Gautam
---
crypto/rsa-pkcs1pad.c | 62 +--
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git
The existing RSA implementation supports PKCSv1.5 style signature
paddings via rsa-pkcs1pad. A lot of the functionality implemented
for rsa-pkcs1pad can be reused across other RSA padding schemes.
Rename such functions as rsapad_* before moving them out of
rsa-pkcs1pad.c.
Signed-off-by: Varad
which can be reused by other signature padding schemes as
rsapad_akcipher_create. This will be moved out of rsa-pkcs1pad.c to
be used across rsa-*pad implementations.
Signed-off-by: Varad Gautam
---
crypto/rsa-pkcs1pad.c | 48 ++-
1 file changed, 34
Move out helpers from rsa-pkcs1pad.c which will be shared across
rsa-*pad implementations.
Signed-off-by: Varad Gautam
---
crypto/Makefile | 1 +
crypto/rsa-common.c | 76 ++
crypto/rsa-pkcs1pad.c| 97
Move helpers for setting public/private keys, RSA akcipher
instance setup, keysize querying etc. to rsa-common.c.
Signed-off-by: Varad Gautam
---
crypto/rsa-common.c | 183 +++
crypto/rsa-pkcs1pad.c| 183 ---
The RSASSA-PSS signature scheme requires knowing the RSA modulus size
in bits. The rsa akcipher_alg max_size call is insufficient for this,
as the returned keysize is rounded up to the next byte.
Since the RSA modulus is stored as an MPI accessible via
struct rsa_mpi_key, move the struct
For certain signature encoding schemes (eg. RSASSA-PSS), the
verify/sign operation behavior depends on information contained in
the signature blob. Allow passing this down to the crypto_template by
introducing a crypto_akcipher_set_sig_params() call.
Signed-off-by: Varad Gautam
---
Add a crypto_template for rsa-psspad, hidden behind
CONFIG_CRYPTO_RSASSA_PSS. Set the sign/verify/encrypt/decrypt
operations to return -EOPNOTSUPP, to be implemented in the future
Signed-off-by: Varad Gautam
---
crypto/Kconfig| 6 ++
crypto/Makefile | 1 +
Trigger RSA transform on the signature being verified from
psspad_verify, to produce intermediary data which will be handled
in the psspad_verify_complete callback.
Reference: https://tools.ietf.org/html/rfc8017#section-8.1.2
Signed-off-by: Varad Gautam
---
crypto/rsa-psspad.c | 53
This generates a "mask" byte array of size mask_len bytes as a
concatenation of digests, where each digest is calculated on a
concatenation of an input seed and a running counter to fill up
mask_len bytes - as described by RFC8017 sec B.2.1. "MGF1".
The mask is useful for RSA signing/verification
The RSA output must be processed as per the EMSA-PSS-VERIFY operation
from RFC8017, which forms the core of the PSS signature verification.
Implement the verification callback, which operates on the RSA output
buffer.
Reference: https://tools.ietf.org/html/rfc8017#section-9.1.2
Signed-off-by:
Pull out more common code from rsa-pkcs1pad into rsa-common.
Signed-off-by: Varad Gautam
---
crypto/rsa-common.c | 31 +++
crypto/rsa-pkcs1pad.c| 32
include/crypto/internal/rsa-common.h | 9
3 files
Implement akcipher_alg->set_sig_params for rsassa-psspad to receive the
salt length and MGF hash function for the signature being verified.
Signed-off-by: Varad Gautam
---
crypto/rsa-psspad.c | 21 -
include/crypto/internal/rsa-common.h | 2 ++
2 files
RSASSA-PSS verify operation needs to compute digests for its
Mask Generation Function (MGF1), and for digest comparison.
Add helpers to populate a crypto_shash and desc for use in both cases.
Signed-off-by: Varad Gautam
---
v3: Add psspad_check_hash_algo to only allow valid hash algorithms in
On 20/03/2021 09:06, Frank Wunderlich wrote:
> From: Frank Wunderlich
>
> add HWMON-support to mediateks thermanl driver to allow lm-sensors
> userspace tools read soc temperature
>
> Signed-off-by: Frank Wunderlich
> ---
> drivers/thermal/mtk_thermal.c | 22 ++
> 1 file
On Tue, Apr 20, 2021 at 03:13:54PM +0300, Mike Rapoport wrote:
> From: Mike Rapoport
>
> Add a paragraph that explains that it may happen that the counters in
> /proc/meminfo do not add up to the overall memory usage.
>
> Signed-off-by: Mike Rapoport
Ooops, forgot to add Michal's Ack, sorry.
On Mon 19-04-21 17:11:37, Johannes Weiner wrote:
> On Mon, Apr 19, 2021 at 01:26:29PM -0400, Waiman Long wrote:
[...]
> - the soft limit tree and soft limit reclaim
>
> - the threshold and oom event notification stuff
>
> - the charge moving code
>
> - remaining v1 interface files, as well as
Hi,
On Tue, Apr 20, 2021 at 12:45:57AM +0530, Deepak R Varma wrote:
> Mixed case variable names are discouraged and they result in checkpatch
> script "Avoid CamelCase" warnings. Replace such CamelCase variable names
> by lower case strings according to the coding style guidelines.
>
>
David / Joerg,
On 4/10/2021 5:03 PM, David Coe wrote:
The immediately obvious difference is the with the enormous count seen on
mem_dte_mis on the older Ryzen 2400G. Will do some RTFM but anyone with
comments and insight?
841,689,151,202,939 amd_iommu_0/mem_dte_mis/
On Sat, Apr 17, 2021 at 01:54:08PM +0200, Christian König wrote:
> Am 17.04.21 um 13:20 schrieb peter.enderb...@sony.com:
> > On 4/17/21 12:59 PM, Christian König wrote:
> > > Am 17.04.21 um 12:40 schrieb Peter Enderborg:
> > > > This adds a total used dma-buf memory. Details
> > > > can be found
From: Geert Uytterhoeven
> Sent: 20 April 2021 08:40
>
> Hi Willy,
>
> On Sat, Apr 17, 2021 at 4:49 AM Matthew Wilcox wrote:
> > Replacement patch to fix compiler warning.
> >
> > 32-bit architectures which expect 8-byte alignment for 8-byte integers
> > and need 64-bit DMA addresses (arc, arm,
On Fri, Apr 9, 2021 at 12:53 PM Hsin-Yi Wang wrote:
>
> drm_dev_register() sets connector->registration_state to
> DRM_CONNECTOR_REGISTERED and dev->registered to true. If
> drm_connector_set_panel_orientation() is first called after
> drm_dev_register(), it will fail several checks and results
On Tue 20-04-21 09:02:57, peter.enderb...@sony.com wrote:
>
> >> But that isn't really system memory at all, it's just allocated device
> >> memory.
> > OK, that was not really clear to me. So this is not really accounted to
> > MemTotal? If that is really the case then reporting it into the oom
The mux route tables take many lines for each SoC, and it will be more
instances for newly SoC, that makes the file size increase larger.
This patch only do coding style for mux route struct, by adding a new
definition and replace the structs by script which supplied by
huang...@rock-chips.com
On Tue, 20 Apr 2021 14:17:16 +0800, Jianjun Wang wrote:
> These series patches add pcie-mediatek-gen3.c and dt-bindings file to
> support new generation PCIe controller.
>
> Changes in v10:
> 1. Fix the subject line format in commit message;
> 2. Use EXPORT_SYMBOL_GPL() to export
Le 20/04/2021 à 11:16, Hans Verkuil a écrit :
On 20/04/2021 11:10, Benjamin Gaignard wrote:
Le 16/04/2021 à 17:14, Lucas Stach a écrit :
Am Freitag, dem 16.04.2021 um 15:08 +0200 schrieb Benjamin Gaignard:
Le 16/04/2021 à 12:54, Lucas Stach a écrit :
Am Mittwoch, dem 07.04.2021 um 09:35
On Mon, Apr 19, 2021 at 05:01:30PM -0700, Yury Norov wrote:
> RCU code supports an 'all' group as a special case when parsing
> rcu_nocbs parameter. This patch moves the 'all' support to the core
> bitmap_parse code, so that all bitmap users can enjoy this extension.
>
> Moving 'all' parsing to a
On 20/04/21 12:11, Peter Zijlstra wrote:
> On Tue, Apr 20, 2021 at 10:43:43AM +0100, Valentin Schneider wrote:
>> On 20/04/21 10:51, Peter Zijlstra wrote:
>
>> > I think free_kthread_struct() is ok, because a task at that point in its
>> > lifetime cannot be also doing exec().
>> >
>>
>> What if
On Tue, Apr 20, 2021 at 07:46:26AM +, HORIGUCHI NAOYA(堀口 直也) wrote:
> If you have any other suggestion, please let me know.
Looks almost ok...
> From: Tony Luck
> Date: Tue, 20 Apr 2021 16:42:01 +0900
> Subject: [PATCH 1/3] mm/memory-failure: Use a mutex to avoid memory_failure()
> races
>
On Tue, Apr 20, 2021 at 10:48:33AM +0800, Bingbu Cao wrote:
> Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
> The IPU driver allocates its own page table that is not mapped
> via the DMA, and thus the Intel IOMMU driver blocks access giving
> this error:
>
> DMAR: DRHD: handling
Hi Vladimir,
On Tue, Apr 20, 2021 at 16:27:10AM +0800, Vladimir Oltean wrote:
>
> On Tue, Apr 20, 2021 at 03:06:40AM +, Xiaoliang Yang wrote:
>> Hi Vladimir.
>>
>> On Mon, Apr 19, 2021 at 20:38PM +0800, Vladimir Oltean wrote:
>> >
>> >What is a scheduled queue? When time-aware scheduling is
On Fri, Apr 16, 2021 at 06:49:09PM +0900, Namhyung Kim wrote:
> On Thu, Apr 15, 2021 at 11:51 PM Peter Zijlstra wrote:
> > > +static void perf_update_cgroup_node(struct perf_event *event, struct
> > > cgroup *cgrp)
> > > +{
> > > + u64 delta_count, delta_time_enabled, delta_time_running;
> >
From: Dan Carpenter
> Sent: 20 April 2021 11:28
>
> On Sat, Apr 17, 2021 at 09:31:32PM +, David Laight wrote:
> > From: Mauro Carvalho Chehab
> > > Sent: 17 April 2021 19:56
> > >
> > > Em Sat, 17 Apr 2021 21:06:27 +0530
> > > Ashish Kalra escreveu:
> > >
> > > > Upon running sparse,
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 3e9a8b219e4cc897dba20e19185d0471f129f6f3
Gitweb:
https://git.kernel.org/tip/3e9a8b219e4cc897dba20e19185d0471f129f6f3
Author:Kan Liang
AuthorDate:Mon, 12 Apr 2021 07:30:59 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: f83d2f91d2590318e083d05bd7b1beda2489050e
Gitweb:
https://git.kernel.org/tip/f83d2f91d2590318e083d05bd7b1beda2489050e
Author:Kan Liang
AuthorDate:Mon, 12 Apr 2021 07:31:00 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 58ae30c29a370c09eb49e0007d881a9aed13c5a3
Gitweb:
https://git.kernel.org/tip/58ae30c29a370c09eb49e0007d881a9aed13c5a3
Author:Kan Liang
AuthorDate:Mon, 12 Apr 2021 07:30:58 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 772ed05f3c5ce722b9de6c4c2dd87538a33fb8d3
Gitweb:
https://git.kernel.org/tip/772ed05f3c5ce722b9de6c4c2dd87538a33fb8d3
Author:Kan Liang
AuthorDate:Mon, 12 Apr 2021 07:31:02 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 55bcf6ef314ae8ba81bcd74aa760247b635ed47b
Gitweb:
https://git.kernel.org/tip/55bcf6ef314ae8ba81bcd74aa760247b635ed47b
Author:Kan Liang
AuthorDate:Mon, 12 Apr 2021 07:31:01 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: d0ca946bcf84e1f9847571923bb1e6bd1264f424
Gitweb:
https://git.kernel.org/tip/d0ca946bcf84e1f9847571923bb1e6bd1264f424
Author:Kan Liang
AuthorDate:Mon, 12 Apr 2021 07:31:04 -07:00
Committer:
The following commit has been merged into the perf/core branch of tip:
Commit-ID: a9c81ccdf52dd73a20178c40bca34cf52991fdea
Gitweb:
https://git.kernel.org/tip/a9c81ccdf52dd73a20178c40bca34cf52991fdea
Author:Kan Liang
AuthorDate:Mon, 12 Apr 2021 07:30:57 -07:00
Committer:
1 - 100 of 1066 matches
Mail list logo
