On 06/19/2018 01:38 AM, Karim Eshapa wrote:
> Backward cleanups for all resources allocated in probing
> in case of failure at any regestering or allocation step.
Hi,
Thanks for the patch.
Resources that are allocated with devm_ are freed automatically in case of
an error, so this patch should
On 06/19/2018 01:38 AM, Karim Eshapa wrote:
> Backward cleanups for all resources allocated in probing
> in case of failure at any regestering or allocation step.
Hi,
Thanks for the patch.
Resources that are allocated with devm_ are freed automatically in case of
an error, so this patch should
On Tue, 19 Jun 2018 17:31:20 +1200
Chris Packham wrote:
> From the controllers point of view this is the same as no or
> software only ECC.
>
> Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
> ---
> Changes in v2:
> - New
>
> drivers/mtd/nand/raw/marvell_nand.c | 1 +
> 1 file
On Tue, 19 Jun 2018 17:31:20 +1200
Chris Packham wrote:
> From the controllers point of view this is the same as no or
> software only ECC.
>
> Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
> ---
> Changes in v2:
> - New
>
> drivers/mtd/nand/raw/marvell_nand.c | 1 +
> 1 file
On 18 June 2018 at 13:41, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.14.51 release.
> There are 189 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On 18 June 2018 at 13:41, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.14.51 release.
> There are 189 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
>
On Mon, 18 Jun 2018 22:41:03 +0200
Martin Kaiser wrote:
> The v21 version of the NAND flash controller contains a Spare Area Size
> Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> spare area size of 218 bytes. The size that is set in this register is
> used by the
On Mon, 18 Jun 2018 22:41:03 +0200
Martin Kaiser wrote:
> The v21 version of the NAND flash controller contains a Spare Area Size
> Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> spare area size of 218 bytes. The size that is set in this register is
> used by the
On 18-06-18, 13:28, Daniel Lezcano wrote:
> for this specific case, we can use the park() callback to set should_run
> to false, no ?
Yep, that can be one option. Or just iterate through all the CPUs in the mask.
--
viresh
On 18-06-18, 13:28, Daniel Lezcano wrote:
> for this specific case, we can use the park() callback to set should_run
> to false, no ?
Yep, that can be one option. Or just iterate through all the CPUs in the mask.
--
viresh
On 6/19/18 12:36 PM, Cong Wang wrote:
> On Mon, Jun 18, 2018 at 2:16 AM, Xunlei Pang wrote:
>> I noticed the group frequently got throttled even it consumed
>> low cpu usage, this caused some jitters on the response time
>> to some of our business containers enabling cpu quota.
>>
>> It's very
On 6/19/18 12:36 PM, Cong Wang wrote:
> On Mon, Jun 18, 2018 at 2:16 AM, Xunlei Pang wrote:
>> I noticed the group frequently got throttled even it consumed
>> low cpu usage, this caused some jitters on the response time
>> to some of our business containers enabling cpu quota.
>>
>> It's very
Volodymyr Babchuk writes:
> From: Volodymyr Babchuk
>
> On virtualized systems it is possible that OP-TEE will provide
> only dynamic shared memory support. So it is fine to boot
> without static SHM enabled if dymanic one is supported.
>
> Signed-off-by: Volodymyr Babchuk
> ---
>
Volodymyr Babchuk writes:
> From: Volodymyr Babchuk
>
> On virtualized systems it is possible that OP-TEE will provide
> only dynamic shared memory support. So it is fine to boot
> without static SHM enabled if dymanic one is supported.
>
> Signed-off-by: Volodymyr Babchuk
> ---
>
On Tue, 19 Jun 2018 17:31:24 +1200
Chris Packham wrote:
> Add ONFI_FEATURE_ON_DIE_ECC to the set/get features list for Micron
> NAND flash.
>
Fixes: 789157e41a06 ("mtd: rawnand: allow vendors to declare (un)supported
features")
Cc:
No need to send a new version, I'll add that when queuing
From: Sayali Lokhande
Add support to use the new compatible string "qcom,sdhci-msm-v5".
Based on the msm variant, pick the relevant variant data and
use it for register read/write to msm specific registers.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
Reviewed-by: Evan Green
On Tue, 19 Jun 2018 17:31:24 +1200
Chris Packham wrote:
> Add ONFI_FEATURE_ON_DIE_ECC to the set/get features list for Micron
> NAND flash.
>
Fixes: 789157e41a06 ("mtd: rawnand: allow vendors to declare (un)supported
features")
Cc:
No need to send a new version, I'll add that when queuing
From: Sayali Lokhande
Add support to use the new compatible string "qcom,sdhci-msm-v5".
Based on the msm variant, pick the relevant variant data and
use it for register read/write to msm specific registers.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
Reviewed-by: Evan Green
From: Sayali Lokhande
For SDCC version 5.0.0 and higher, new compatible string
"qcom,sdhci-msm-v5" is added.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 7 ++-
1 file changed, 6
From: Sayali Lokhande
For SDCC version 5.0.0 and higher, new compatible string
"qcom,sdhci-msm-v5" is added.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 7 ++-
1 file changed, 6
In addition to offsets of certain registers changing, the registers in
core_mem have been shifted to HC mem as well. To access these
registers, define msm version specific functions. These functions can
be loaded into the function pointers at the time of probe based on
the msm version detected.
In addition to offsets of certain registers changing, the registers in
core_mem have been shifted to HC mem as well. To access these
registers, define msm version specific functions. These functions can
be loaded into the function pointers at the time of probe based on
the msm version detected.
From: Sayali Lokhande
For SDCC version 5.0.0, MCI registers are removed from SDCC
interface and some registers are moved to HC.
Define a new data structure where we can statically define
the address offsets for the registers in different SDCC versions.
Signed-off-by: Sayali Lokhande
With SDCC5, the MCI register space got removed and the offset/order of
several registers have changed. Based on SDCC version used and the register,
we need to pick the base address and offset.
Depends on patch series: "[PATCH V5 0/2] mmc: sdhci-msm: Configuring IO_PAD
support for sdhci-msm"
From: Sayali Lokhande
For SDCC version 5.0.0, MCI registers are removed from SDCC
interface and some registers are moved to HC.
Define a new data structure where we can statically define
the address offsets for the registers in different SDCC versions.
Signed-off-by: Sayali Lokhande
With SDCC5, the MCI register space got removed and the offset/order of
several registers have changed. Based on SDCC version used and the register,
we need to pick the base address and offset.
Depends on patch series: "[PATCH V5 0/2] mmc: sdhci-msm: Configuring IO_PAD
support for sdhci-msm"
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/raw/nand_base.c | 4
include/linux/mtd/rawnand.h | 1 +
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/raw/nand_base.c | 4
include/linux/mtd/rawnand.h | 1 +
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/raw/marvell_nand.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/raw/marvell_nand.c
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
---
This is now qualified on vendor == MICRON. I
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/raw/marvell_nand.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/raw/marvell_nand.c
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
---
This is now qualified on vendor == MICRON. I
Hi,
I'm looking at adding support for the Micron MT29F1G08ABAFAWP-ITE:F chip
to one of our boards which uses the Marvell NFCv2 controller.
This particular chip is a bit odd in that the datasheet states support
for ONFI 1.0 but the revision number field is 00 00. It also is marked
ABAFA but
Hi,
I'm looking at adding support for the Micron MT29F1G08ABAFAWP-ITE:F chip
to one of our boards which uses the Marvell NFCv2 controller.
This particular chip is a bit odd in that the datasheet states support
for ONFI 1.0 but the revision number field is 00 00. It also is marked
ABAFA but
Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
per 512 bytes. Add support for this combination.
Signed-off-by: Chris Packham
---
This seems deceptively easy so I've probably missed something. I have
tested with running some of the ubifs stress tests from mtd-utils and
things
Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
per 512 bytes. Add support for this combination.
Signed-off-by: Chris Packham
---
This seems deceptively easy so I've probably missed something. I have
tested with running some of the ubifs stress tests from mtd-utils and
things
The MT29F1G08ABAFAWP-ITE:F chip has 2048 byte pages and requires a
minimum ECC strength of 8-bits. Allow for this combination of
requirements using the marvell_nand controller.
Signed-off-by: Chris Packham
---
I've tried to follow the recommended AN-379 from Marvell. They do seem
to have
The MT29F1G08ABAFAWP-ITE:F chip has 2048 byte pages and requires a
minimum ECC strength of 8-bits. Allow for this combination of
requirements using the marvell_nand controller.
Signed-off-by: Chris Packham
---
I've tried to follow the recommended AN-379 from Marvell. They do seem
to have
Add ONFI_FEATURE_ON_DIE_ECC to the set/get features list for Micron
NAND flash.
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/raw/nand_micron.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_micron.c
Add ONFI_FEATURE_ON_DIE_ECC to the set/get features list for Micron
NAND flash.
Signed-off-by: Chris Packham
---
Changes in v2:
- New
drivers/mtd/nand/raw/nand_micron.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_micron.c
On Tue, Jun 19, 2018 at 6:42 AM, Steven Rostedt wrote:
> On Mon, 18 Jun 2018 13:58:09 +0900
> Byungchul Park wrote:
>
>> Hello Steven,
>>
>> I've changed the code a little bit to avoid a compile warning caused by
>> 'const' args of find_cpu(). Can I keep your Reviewed-by?
>>
>> BEFORE:
>> static
On Mon 18 Jun 06:37 PDT 2018, Raju P L S S S N wrote:
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index 39d3a05..cb6300f 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
>
On Tue, Jun 19, 2018 at 6:42 AM, Steven Rostedt wrote:
> On Mon, 18 Jun 2018 13:58:09 +0900
> Byungchul Park wrote:
>
>> Hello Steven,
>>
>> I've changed the code a little bit to avoid a compile warning caused by
>> 'const' args of find_cpu(). Can I keep your Reviewed-by?
>>
>> BEFORE:
>> static
On Mon 18 Jun 06:37 PDT 2018, Raju P L S S S N wrote:
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index 39d3a05..cb6300f 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
>
A lot of memory can be consumed by the events generated for the huge or
unlimited queues if there is either no or slow listener. This can cause
system level memory pressure or OOMs. So, it's better to account the
fsnotify kmem caches to the memcg of the listener.
There are seven fsnotify kmem
A lot of memory can be consumed by the events generated for the huge or
unlimited queues if there is either no or slow listener. This can cause
system level memory pressure or OOMs. So, it's better to account the
fsnotify kmem caches to the memcg of the listener.
There are seven fsnotify kmem
The buffer_head can consume a significant amount of system memory and
is directly related to the amount of page cache. In our production
environment we have observed that a lot of machines are spending a
significant amount of memory as buffer_head and can not be left as
system memory overhead.
Introduce the memcg variant for kmalloc[_node] and
kmem_cache_alloc[_node]. For kmem_cache_alloc, the kernel switches the
root kmem cache with the memcg specific kmem cache for __GFP_ACCOUNT
allocations to charge those allocations to the memcg. However, the memcg
to charge is extracted from the
This patchset introduces memcg variant memory allocation functions. The
caller can explicitly pass the memcg to charge for kmem allocations.
Currently the kernel, for __GFP_ACCOUNT memory allocation requests,
extract the memcg of the current task to charge for the kmem allocation.
This patch
The buffer_head can consume a significant amount of system memory and
is directly related to the amount of page cache. In our production
environment we have observed that a lot of machines are spending a
significant amount of memory as buffer_head and can not be left as
system memory overhead.
Introduce the memcg variant for kmalloc[_node] and
kmem_cache_alloc[_node]. For kmem_cache_alloc, the kernel switches the
root kmem cache with the memcg specific kmem cache for __GFP_ACCOUNT
allocations to charge those allocations to the memcg. However, the memcg
to charge is extracted from the
This patchset introduces memcg variant memory allocation functions. The
caller can explicitly pass the memcg to charge for kmem allocations.
Currently the kernel, for __GFP_ACCOUNT memory allocation requests,
extract the memcg of the current task to charge for the kmem allocation.
This patch
Thanks Bart,
applied to the configfs tree for 4.19.
Thanks Bart,
applied to the configfs tree for 4.19.
On Mon, Jun 18, 2018 at 9:08 PM Jason A. Donenfeld wrote:
>
> On Tue, Jun 19, 2018 at 5:59 AM Shakeel Butt wrote:
> > Hi Jason, yes please do send me the test suite with the kernel config.
>
> $ git clone https://git.zx2c4.com/WireGuard
> $ cd WireGuard/src
> $ [[ $(gcc -v 2>&1) =~ gcc\ version\
On Mon, Jun 18, 2018 at 9:08 PM Jason A. Donenfeld wrote:
>
> On Tue, Jun 19, 2018 at 5:59 AM Shakeel Butt wrote:
> > Hi Jason, yes please do send me the test suite with the kernel config.
>
> $ git clone https://git.zx2c4.com/WireGuard
> $ cd WireGuard/src
> $ [[ $(gcc -v 2>&1) =~ gcc\ version\
Modern assemblers may take the ISA into account when resolving local
symbols. This can result in bad address calculations when using badr
in the wrong location since the offset + 1 may be added twice, resulting
in an even address target for THUMB instructions. This in turn results
in an exception
Modern assemblers may take the ISA into account when resolving local
symbols. This can result in bad address calculations when using badr
in the wrong location since the offset + 1 may be added twice, resulting
in an even address target for THUMB instructions. This in turn results
in an exception
Export pnv_idle_states and nr_pnv_idle_states so that its accessible to
cpuidle driver. Use properties from pnv_idle_states structure for powernv
cpuidle_init.
Signed-off-by: Akshay Adiga
---
arch/powerpc/include/asm/cpuidle.h | 2 ++
drivers/cpuidle/cpuidle-powernv.c | 49
Export pnv_idle_states and nr_pnv_idle_states so that its accessible to
cpuidle driver. Use properties from pnv_idle_states structure for powernv
cpuidle_init.
Signed-off-by: Akshay Adiga
---
arch/powerpc/include/asm/cpuidle.h | 2 ++
drivers/cpuidle/cpuidle-powernv.c | 49
On Sun, Jun 17, 2018 at 11:31:41AM +0300, Avi Kivity wrote:
> This reverts commit 4d572d9f46507be8cfe326aa5bc3698babcbdfa7. It is
> superceded by the more general
> 2739b807b0885a09996659be82f813af219c7360 ("aio: only return events
> requested in poll_mask() for IOCB_CMD_POLL"). Unfortunately, hch
Device-tree parsing happens in twice, once while deciding idle state to
be used for hotplug and once during cpuidle init. Hence, parsing the
device tree and caching it will reduce code duplication. Parsing code
has been moved to pnv_parse_cpuidle_dt() from pnv_probe_idle_states().
Setting up
On 18-06-18, 16:46, Rohit kumar wrote:
> +struct sdm845_snd_data {
> + struct snd_soc_card *card;
> + struct regulator *vdd_supply;
> + struct snd_soc_dai_link dai_link[];
> +};
> +
> +static struct mutex pri_mi2s_res_lock;
> +static struct mutex quat_tdm_res_lock;
any reason why the
On Mon, May 21, 2018 at 03:25:04PM +0100, Quentin Perret wrote:
> + if (cpumask_test_cpu(prev_cpu, >cpus_allowed))
> + prev_energy = best_energy = compute_energy(p, prev_cpu);
> + else
> + prev_energy = best_energy = ULONG_MAX;
> +
> +
On Sun, Jun 17, 2018 at 11:31:41AM +0300, Avi Kivity wrote:
> This reverts commit 4d572d9f46507be8cfe326aa5bc3698babcbdfa7. It is
> superceded by the more general
> 2739b807b0885a09996659be82f813af219c7360 ("aio: only return events
> requested in poll_mask() for IOCB_CMD_POLL"). Unfortunately, hch
Device-tree parsing happens in twice, once while deciding idle state to
be used for hotplug and once during cpuidle init. Hence, parsing the
device tree and caching it will reduce code duplication. Parsing code
has been moved to pnv_parse_cpuidle_dt() from pnv_probe_idle_states().
Setting up
On 18-06-18, 16:46, Rohit kumar wrote:
> +struct sdm845_snd_data {
> + struct snd_soc_card *card;
> + struct regulator *vdd_supply;
> + struct snd_soc_dai_link dai_link[];
> +};
> +
> +static struct mutex pri_mi2s_res_lock;
> +static struct mutex quat_tdm_res_lock;
any reason why the
On Mon, May 21, 2018 at 03:25:04PM +0100, Quentin Perret wrote:
> + if (cpumask_test_cpu(prev_cpu, >cpus_allowed))
> + prev_energy = best_energy = compute_energy(p, prev_cpu);
> + else
> + prev_energy = best_energy = ULONG_MAX;
> +
> +
On Mon, Jun 18, 2018 at 09:47:48PM -0700, Christoph Hellwig wrote:
> On Tue, Jun 19, 2018 at 02:05:23PM +1000, NeilBrown wrote:
> > From: NeilBrown
> > Date: Tue, 19 Jun 2018 13:59:16 +1000
> > Subject: [PATCH] kbuild/xfs: example modobj-m conversion
> >
> > This is a demonstration patch to show
On Mon, Jun 18, 2018 at 09:47:48PM -0700, Christoph Hellwig wrote:
> On Tue, Jun 19, 2018 at 02:05:23PM +1000, NeilBrown wrote:
> > From: NeilBrown
> > Date: Tue, 19 Jun 2018 13:59:16 +1000
> > Subject: [PATCH] kbuild/xfs: example modobj-m conversion
> >
> > This is a demonstration patch to show
So the TIP tree was named for “Thomas, Ingo, Peter”. Need to add an “A” for
Andy. Maybe it should be the PITA tree :-)
-Tony
> On Jun 18, 2018, at 14:41, Andy Lutomirski wrote:
>
> And update my email address.
>
> Cc: Ingo Molnar
> Cc: Thomas Gleixner
> Cc: "H. Peter Anvin"
> Cc: Linus
So the TIP tree was named for “Thomas, Ingo, Peter”. Need to add an “A” for
Andy. Maybe it should be the PITA tree :-)
-Tony
> On Jun 18, 2018, at 14:41, Andy Lutomirski wrote:
>
> And update my email address.
>
> Cc: Ingo Molnar
> Cc: Thomas Gleixner
> Cc: "H. Peter Anvin"
> Cc: Linus
On Mon, Jun 4, 2018 at 10:47 PM, Souptick Joarder wrote:
> Use new return type vm_fault_t for fault handler. For
> now, this is just documenting that the function returns
> a VM_FAULT value rather than an errno. Once all instances
> are converted, vm_fault_t will become a distinct type.
>
> Ref->
On Tue, Jun 19, 2018 at 6:08 AM, Jason A. Donenfeld wrote:
> On Tue, Jun 19, 2018 at 5:59 AM Shakeel Butt wrote:
>> Hi Jason, yes please do send me the test suite with the kernel config.
>
> $ git clone https://git.zx2c4.com/WireGuard
> $ cd WireGuard/src
> $ [[ $(gcc -v 2>&1) =~ gcc\ version\
On Mon, Jun 4, 2018 at 10:47 PM, Souptick Joarder wrote:
> Use new return type vm_fault_t for fault handler. For
> now, this is just documenting that the function returns
> a VM_FAULT value rather than an errno. Once all instances
> are converted, vm_fault_t will become a distinct type.
>
> Ref->
On Tue, Jun 19, 2018 at 6:08 AM, Jason A. Donenfeld wrote:
> On Tue, Jun 19, 2018 at 5:59 AM Shakeel Butt wrote:
>> Hi Jason, yes please do send me the test suite with the kernel config.
>
> $ git clone https://git.zx2c4.com/WireGuard
> $ cd WireGuard/src
> $ [[ $(gcc -v 2>&1) =~ gcc\ version\
Hi Chris,
On Tue, 19 Jun 2018 01:44:24 +
Chris Packham wrote:
> On 19/06/18 12:35, Chris Packham wrote:
> > On 19/06/18 01:15, Miquel Raynal wrote:
> >> Hi Chris,
> >>
> >> On Mon, 18 Jun 2018 16:52:53 +1200, Chris Packham
> >> wrote:
> >>
> >>> Hi,
> >>>
> >>> I'm looking at adding
The early console code for mps2-uart assumes that the serial hardware is
enabled for transmit when the system boots. However, this is not the case
after reset. This results in a hang in mps2_early_putchar() if the serial
transmitter is not enabled by a boot loader or ROM monitor.
Signed-off-by:
Hi Chris,
On Tue, 19 Jun 2018 01:44:24 +
Chris Packham wrote:
> On 19/06/18 12:35, Chris Packham wrote:
> > On 19/06/18 01:15, Miquel Raynal wrote:
> >> Hi Chris,
> >>
> >> On Mon, 18 Jun 2018 16:52:53 +1200, Chris Packham
> >> wrote:
> >>
> >>> Hi,
> >>>
> >>> I'm looking at adding
The early console code for mps2-uart assumes that the serial hardware is
enabled for transmit when the system boots. However, this is not the case
after reset. This results in a hang in mps2_early_putchar() if the serial
transmitter is not enabled by a boot loader or ROM monitor.
Signed-off-by:
Hi all,
Today's linux-next merge of the userns tree got conflicts in:
fs/proc/inode.c
fs/proc/root.c
between commits:
0223e0999be2 ("procfs: Move proc_fill_super() to fs/proc/root.c")
83cd45075c36 ("proc: Add fs_context support to procfs")
from the vfs tree and commit:
cc8cda3af2ba
Hi all,
Today's linux-next merge of the userns tree got conflicts in:
fs/proc/inode.c
fs/proc/root.c
between commits:
0223e0999be2 ("procfs: Move proc_fill_super() to fs/proc/root.c")
83cd45075c36 ("proc: Add fs_context support to procfs")
from the vfs tree and commit:
cc8cda3af2ba
Hi Tony,
> Am 19.06.2018 um 06:34 schrieb Tony Lindgren :
>
> * H. Nikolaus Schaller [180618 18:33]:
So code just needs group cleanup on failed probing and fixing the mutex
around pinctrl_generic_add_group().
I think we need the mutex because a race still can happen when
On Mon, 2018-06-18 at 21:50 -0400, Nicolas Pitre wrote:
> On Tue, 19 Jun 2018, Andy Shevchenko wrote:
[]
> > > + /*
> > > +* Make sure our unicode screen translates into the same glyphs
> > > +* as the actual screen. This is brutal indeed.
> > > +*/
> > > + p =
Hi Tony,
> Am 19.06.2018 um 06:34 schrieb Tony Lindgren :
>
> * H. Nikolaus Schaller [180618 18:33]:
So code just needs group cleanup on failed probing and fixing the mutex
around pinctrl_generic_add_group().
I think we need the mutex because a race still can happen when
On Mon, 2018-06-18 at 21:50 -0400, Nicolas Pitre wrote:
> On Tue, 19 Jun 2018, Andy Shevchenko wrote:
[]
> > > + /*
> > > +* Make sure our unicode screen translates into the same glyphs
> > > +* as the actual screen. This is brutal indeed.
> > > +*/
> > > + p =
On 2018/6/19 3:56, Borislav Petkov wrote:
On Mon, Jun 04, 2018 at 08:16:51AM +, Zhenzhong Duan wrote:
Intel spec says: 'The processor flags in the 48-byte header and the
processor flags field associated with the extended processor signature
structures may have multiple bits set.'
Make sure
On 2018/6/19 3:56, Borislav Petkov wrote:
On Mon, Jun 04, 2018 at 08:16:51AM +, Zhenzhong Duan wrote:
Intel spec says: 'The processor flags in the 48-byte header and the
processor flags field associated with the extended processor signature
structures may have multiple bits set.'
Make sure
On Tue, Jun 19, 2018 at 02:05:23PM +1000, NeilBrown wrote:
> From: NeilBrown
> Date: Tue, 19 Jun 2018 13:59:16 +1000
> Subject: [PATCH] kbuild/xfs: example modobj-m conversion
>
> This is a demonstration patch to show how
> xfs can be changed to make use of the proposed modobj-m=
>
On Tue, Jun 19, 2018 at 02:05:23PM +1000, NeilBrown wrote:
> From: NeilBrown
> Date: Tue, 19 Jun 2018 13:59:16 +1000
> Subject: [PATCH] kbuild/xfs: example modobj-m conversion
>
> This is a demonstration patch to show how
> xfs can be changed to make use of the proposed modobj-m=
>
On Mon, Jun 18, 2018 at 2:16 AM, Xunlei Pang wrote:
> I noticed the group frequently got throttled even it consumed
> low cpu usage, this caused some jitters on the response time
> to some of our business containers enabling cpu quota.
>
> It's very easy to reproduce:
> mkdir
On Mon, Jun 18, 2018 at 2:16 AM, Xunlei Pang wrote:
> I noticed the group frequently got throttled even it consumed
> low cpu usage, this caused some jitters on the response time
> to some of our business containers enabling cpu quota.
>
> It's very easy to reproduce:
> mkdir
On 18-06-18, 13:33, Srinivas Kandagatla wrote:
> This patch fixes below kerneldoc warnings
>
> qcom_smd.c:141: warning: Function parameter or member 'dev' not described in
> 'qcom_smd_edge'
> qcom_smd.c:141: warning: Function parameter or member 'name' not described in
> 'qcom_smd_edge'
>
On 18-06-18, 13:33, Srinivas Kandagatla wrote:
> This patch fixes below kerneldoc warnings
>
> qcom_smd.c:141: warning: Function parameter or member 'dev' not described in
> 'qcom_smd_edge'
> qcom_smd.c:141: warning: Function parameter or member 'name' not described in
> 'qcom_smd_edge'
>
* H. Nikolaus Schaller [180618 18:33]:
> >> So code just needs group cleanup on failed probing and fixing the mutex
> >> around pinctrl_generic_add_group().
> >>
> >> I think we need the mutex because a race still can happen when
> >> create_pinctrl() is calling pcs_dt_node_to_map()
> >> and
* H. Nikolaus Schaller [180618 18:33]:
> >> So code just needs group cleanup on failed probing and fixing the mutex
> >> around pinctrl_generic_add_group().
> >>
> >> I think we need the mutex because a race still can happen when
> >> create_pinctrl() is calling pcs_dt_node_to_map()
> >> and
On 14-06-18, 09:37, Sinan Kaya wrote:
> I'm no longer with QCOM. I am still interested in maintaining or reviewing
> PCI/DMA engine patches. Update email-id to an active one.
Applied, thanks
--
~Vinod
On 14-06-18, 09:37, Sinan Kaya wrote:
> I'm no longer with QCOM. I am still interested in maintaining or reviewing
> PCI/DMA engine patches. Update email-id to an active one.
Applied, thanks
--
~Vinod
From: Russ Dill
Deep enough power saving mode can result into losing context of the clock
registers also, and they need to be restored once coming back from the power
saving mode. Hence add functions to save/restore clock context.
Signed-off-by: Keerthy
Signed-off-by: Russ Dill
---
From: Russ Dill
Deep enough power saving mode can result into losing context of the clock
registers also, and they need to be restored once coming back from the power
saving mode. Hence add functions to save/restore clock context.
Signed-off-by: Keerthy
Signed-off-by: Russ Dill
---
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