Realtek single-port 2.5Gbps Ethernet PHYs are list as below:
RTL8226-CG: the 1st generation 2.5Gbps single port PHY
RTL8226B-CG/RTL8221B-CG: the 2nd generation 2.5Gbps single port PHY
RTL8221B-VB-CG: the 3rd generation 2.5Gbps single port PHY
RTL8221B-VM-CG: the 2.5Gbps single port PHY with MACsec
> From: Lu Baolu
> Sent: Friday, October 30, 2020 12:58 PM
>
> The aux-domain apis were designed for macro driver where the subdevices
> are created and used inside a device driver. Use the device's bus iommu
> ops instead of that in iommu domain for various callbacks.
IIRC there are only two
All the items in the TODO list were addressed, uapi was reviewed,
documentation written, checkpatch errors fixed, several bugs fixed.
There is no big reason to keep this driver in staging, so move it out.
Signed-off-by: Helen Koike
---
.../media/v4l/pixfmt-meta-rkisp1.rst | 2 +-
Hello,
I think it is time to move this driver out of staging.
Thanks all who contributed, specially to Dafna, who put a lot of
effort addressing all the items in the TODO list, fixing bugs,
cleaning the code, addressing past comments and testing.
Please, review the driver, see if there is any
From: Shunqian Zheng
Add the Rockchip ISP1 specific processing parameter format
V4L2_META_FMT_RK_ISP1_PARAMS and metadata format
V4L2_META_FMT_RK_ISP1_STAT_3A for 3A.
Signed-off-by: Shunqian Zheng
Signed-off-by: Jacob Chen
Signed-off-by: Helen Koike
Reviewed-by: Laurent Pinchart
---
Hello,
On Thu, Oct 29, 2020 at 7:34 PM David Gow wrote:
>
> On Wed, Oct 21, 2020 at 7:32 AM Daniel Latypov wrote:
> >
> > For simplcity, strip all trailing whitespace from parsed output.
> > I imagine no one is printing out meaningful trailing whitespace via
> > KUNIT_FAIL() or similar, and that if
On 10/29/20 7:45 PM, Hemant Kumar wrote:
> diff --git a/drivers/bus/mhi/Kconfig b/drivers/bus/mhi/Kconfig
> index e841c10..476cc55 100644
> --- a/drivers/bus/mhi/Kconfig
> +++ b/drivers/bus/mhi/Kconfig
> @@ -20,3 +20,16 @@ config MHI_BUS_DEBUG
> Enable debugfs support for use with the MHI
When perf data is in a pipe, it reads each event separately using
read(2) syscall. This is a huge performance bottleneck when
processing large data like in perf inject. Also perf inject needs to
use write(2) syscall for the output.
So convert it to use buffer I/O functions in stdio library for
I typically build cifs.ko for testing using the latest Ubuntu mainline
build - but building a module in the 5.10-rc1 kernel - while booted to
the 5.10-rc1 ubuntu mainlinekerel - e.g. "make C=1 -C
/usr/src/linux-headers-`uname -r` M=`pwd` modules
CF=-D__CHECK_ENDIAN__"
which has worked for years -
The Corsair digital power supplies of the series RMi, HXi and AXi include
a small micro-controller with a lot of sensors attached. The sensors can
be accessed by an USB connector from the outside.
This micro-controller provides the data by a simple proprietary USB HID
protocol. The data consist
Hi Jiri,
On Thu, Oct 29, 2020 at 8:57 PM Jiri Olsa wrote:
>
> On Wed, Oct 28, 2020 at 05:56:32PM +0900, Namhyung Kim wrote:
> > When perf data is in a pipe, it reads each event separately using
> > read(2) syscall. This is a huge performance bottleneck when
> > processing large data like in
From: Ramuthevar Vadivel Murugan
Add compatible for Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
Documentation/devicetree/bindings/spi/cadence-quadspi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
From: Ramuthevar Vadivel Murugan
Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/spi/cadence-quadspi.txt| 67 -
Add QSPI controller support for Intel LGM SoC.
Note from Vignesh(mtd subsystem maintainer):
This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
that intended to move
cadence-quadspi driver to spi-mem
From: Ramuthevar Vadivel Murugan
Add QSPI controller support for Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
drivers/spi/Kconfig | 2 +-
drivers/spi/spi-cadence-quadspi.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig
From: Ramuthevar Vadivel Murugan
Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.
Signed-off-by: Ramuthevar Vadivel Murugan
---
drivers/spi/spi-cadence-quadspi.c | 16
1 file changed, 16 insertions(+)
diff --git
From: Ramuthevar Vadivel Murugan
On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).
This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfer.
Signed-off-by: Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan
Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to
Documentation/devicetree/bindings/spi/
Signed-off-by: Ramuthevar Vadivel Murugan
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt | 0
1 file
Hi,
Is the community not interested in these two patches?
The second one also appears in the LBR patch set and
will benefit other PMU features later, such as PEBS.
Thanks,
Like Xu
On 2020/10/20 22:57, Like Xu wrote:
On Intel platforms, software may uses IA32_MISC_ENABLE[7]
bit to detect
Hello,
On Thu, Oct 8, 2020 at 6:38 PM Mark Wielaard wrote:
>
> Hi,
>
> On Thu, 2020-10-08 at 09:02 +0200, Peter Zijlstra wrote:
> > Some time ago, I had my intern pursue the other 2 approaches for
> > > symbolization. The one I see as most promising is by using the DWARF
> > > information (no
On Thu, Oct 29, 2020 at 7:56 PM David Gow wrote:
>
> On Thu, Oct 22, 2020 at 6:08 AM Daniel Latypov wrote:
> >
> > The code uses annotations, but they aren't accurate.
> > Note that type checking in python is a separate process, running
> > `kunit.py run` will not check and complain about
On 2020-10-28 17:16, Robert Marko wrote:
If the watchdog hardware is enabled/running during boot, e.g.
due to a boot loader configuring it, we must tell the
watchdog framework about this fact so that it can ping the
watchdog until userspace opens the device and takes over
control.
Do so using
Andreas Schwab writes:
> On Okt 01 2020, Christophe Leroy wrote:
>
>> At the time being, an early hash table is set up when
>> CONFIG_KASAN is selected.
>>
>> There is nothing wrong with setting such an early hash table
>> all the time, even if it is not used. This is a statically
>> allocated
On 10/30/2020 2:18 AM, m...@chromium.org wrote:
On Thu, Oct 29, 2020 at 01:37:19PM +0530, Akhil P Oommen wrote:
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
Reviewed-by: Matthias Kaehlcke
Wait, I did not
With the IOMMU driver registering iommu_ops for the mdev_bus, the IOMMU
operations on an mdev could be done in the same way as any normal device
(for example, PCI/PCIe). There's no need to distinguish an mdev from
others for iommu operations. Remove the unnecessary code.
Signed-off-by: Lu Baolu
Hi Joerg and Alex,
A description of purpose for this series could be found here.
https://lore.kernel.org/linux-iommu/20200901033422.22249-1-baolu...@linux.intel.com/
The previous version was posted here.
https://lore.kernel.org/linux-iommu/20200922061042.31633-1-baolu...@linux.intel.com/
This
The aux-domain apis were designed for macro driver where the subdevices
are created and used inside a device driver. Use the device's bus iommu
ops instead of that in iommu domain for various callbacks.
Signed-off-by: Lu Baolu
---
drivers/iommu/iommu.c | 16 ++--
1 file changed, 10
Move mdev bus registration earlier than IOMMU probe processing so that
the IOMMU drivers could be able to set iommu_ops for the mdev bus. This
only applies when vfio-mdev module is setected to be built-in.
Signed-off-by: Lu Baolu
---
drivers/vfio/mdev/mdev_core.c | 4
1 file changed, 4
So that they could be used in other files as well. No functional changes.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 74 +++--
include/linux/intel-iommu.h | 49
2 files changed, 62 insertions(+), 61 deletions(-)
diff --git
The iommu_ops will only take effect when INTEL_IOMMU_SCALABLE_IOV kernel
option is selected. It applies to any device passthrough framework which
implements an underlying bus for the subdevices.
- Subdevice probe:
When a subdevice is created and added to the bus, iommu_probe_device()
will be
On Wed, Oct 28, 2020 at 10:41:02AM -0500, Tyler Hicks wrote:
> Mimic the pre-existing ACPI and Device Tree event log behavior by not
> creating the binary_bios_measurements file when the EFI TPM event log is
> empty.
>
> This fixes the following NULL pointer dereference that can occur when
>
On Fri, 30 Oct 2020 at 04:28, Andrew Jeffery wrote:
>
> Hi Billy,
>
> On Tue, 27 Oct 2020, at 19:14, Billy Tsai wrote:
> > Some gpio pin at aspeed soc is input only and the prefix name of these
> > pin is "GPI" only. This patch fine-tune the condition of GPIO check from
> > "GPIO" to "GPI".
> >
>
[AMD Official Use Only - Internal Distribution Only]
Other used APIs should be also dropped together.
navi10_i2c_func()
navi10_i2c_xfer()
navi10_i2c_write_data()
navi10_i2c_read_data()
Regards,
Evan
-Original Message-
From: amd-gfx On Behalf Of Zou Wei
Sent: Thursday, October 29, 2020
The USB Power Delivery specification Section 6.2.1.1.5 outlines
revision backward compatibility requirements starting from Revision 3.0.
The Port, the Cable Plug, and the Port Partner may support either revision
2 or revision 3 individually, and communication between ports, partners,
and cables
Hi all,
In commit
65d437b83b2b ("drm/amdgpu/pm: fix the fan speed in fan1_input in manual mode
for navi1x")
Fixes tag
Fixes: 3033e9f1c2de ("drm/amdgpu/swsmu: handle manual fan readback on SMU11")
has these problem(s):
- Target SHA1 does not exist
Mayne you meant
Fixes: f6eb433954bf
Hello, This is Hyungjae Im from Samsung Electronics.
Let me answer your questions inline.
>On Thu, Oct 29, 2020 at 10:27:47PM +0900, HyungJae Im wrote:
>> From: "hj2.im"
>> Date: Thu, 29 Oct 2020 22:11:24 +0900
>> Subject: [PATCH v2] input: add 2 kind of switch
>
>Why is this in the body of
Hi Billy,
On Tue, 27 Oct 2020, at 19:14, Billy Tsai wrote:
> Some gpio pin at aspeed soc is input only and the prefix name of these
> pin is "GPI" only. This patch fine-tune the condition of GPIO check from
> "GPIO" to "GPI".
>
> Signed-off-by: Billy Tsai
I'd like it if we were a bit more
Hi Kuogee,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 07e0887302450a62f51dba72df6afb5fabb23d1c
commit: 8ede2ecc3e5ee327923f6e3cfe52761ce73607d1 drm/msm/dp: Add DP compliance
tests on Snapdragon Chipsets
date:
I found a bug in the recursion protection that prevented function
tracing from running in NMI context. Applying this fix to 5.9 worked
fine (tested by running perf record and function tracing at the same
time). But when I applied the patch to 5.10-rc1, it blew up with a
stack overflow:
perf:
Pages in active areas shouldn’t be swapped out only those in inactive areas. So
it’s a bit like seminary rock.
Sent from my iPhone
On 29-10-20, 09:40, Viresh Kumar wrote:
> Thanks a lot. I was a bit worried about the crazy idea I had to solve
> this :)
Hmm, I thought this is the other patch where I had that crazy idea.
This one was quite straight forward :)
--
viresh
I have an issue on my laptop which is old but with 2.5gb of ram an ssd hdd and
using zram compression I believe.
When ever it hits swap the system completely locks up and I have to reboot.
This only started occurring in .51
I only have access to my phone at the moment though I’ve looked at the
Applied. Thanks!
Alex
On Thu, Oct 29, 2020 at 9:17 AM Bhaskar Chowdhury wrote:
>
> Correct spelling in one of the comment.
>
> s/defalut/default/p
>
> Signed-off-by: Bhaskar Chowdhury
> ---
> CCing Greg becasue it touched drivers file. Trivial though.
>
>
Hi all,
Changes since 20201029:
The drm-misc tree gained a build failure so I used the version from
next-20201029.
The pinctrl tree gained a build failure so I reverted a commit.
Non-merge commits (relative to Linus' tree): 1997
2411 files changed, 324993 insertions(+), 49232 deletions
Move MHI to a firmware download error state for a failure to find
the firmware files or to load SBL or EBL image using BHI/BHIe. This
helps detect an error state sooner and shortens the wait for a
synchronous power up timeout.
Signed-off-by: Bhaumik Bhatt
---
drivers/bus/mhi/core/boot.c | 35
MHI client drivers can request a device wake even if the device
may be in an error state or undergoing a shutdown. To prevent
unnecessary device wake processing, check for the device state
and bail out early so that the clients are made aware of the
device state sooner.
Signed-off-by: Bhaumik
mhi_fw_load_sbl() function is currently used to transfer SBL or EDL
images over BHI (Boot Host Interface). Same goes with mhi_fw_load_amss()
which uses BHIe. However, the contents of these functions do not
indicate support for a specific set of images. Since these can be used
for any image
Bug fixes and improvements for MHI powerup and shutdown handling.
Firmware load function names are updated to accurately reflect their purpose.
Closed certain design gaps where the host (MHI bus) would allow clients to
operate after a power down or error detection.
Move to an error state sooner
mhi_power_down() does not ensure that the PM state is moved to an
inaccessible state soon enough as the system can encounter
scheduling delays till mhi_pm_disable_transition() gets called.
Additionally, if an MHI controller decides that the device is now
inaccessible and issues a power down, the
If an mhi_power_down() is initiated after the device has entered
RDDM and a status callback was provided for it, it is possible
that another BHI interrupt fires while waiting for the MHI
RESET to be cleared. If that happens, MHI host would have moved
a "disabled" execution environment and the
If the host receives a mission mode event and by the time it can get
to processing it, the register accesses fail implying a connectivity
error, MHI should move to an error state. This helps avoid longer wait
times from a synchronous power up perspective and accurately reflects
the MHI execution
Currently, there exist a set of if...else statements in the
mhi_pm_disable_transition() function which make handling system
error and disable transitions differently complex. To make that
cleaner and facilitate differences in behavior, separate these
two transitions for MHI host.
Signed-off-by:
While powering down, the device may or may not acknowledge an MHI
RESET issued by host for a graceful shutdown scenario and end up
sending an incoming data packet after tasklets have been killed.
If a rogue device sends this interrupt for a data transfer event
ring update, it can result in a
Correct the "error_read" label to say "error_ready_state" as that
is the appropriate usage of the label.
Signed-off-by: Bhaumik Bhatt
---
drivers/bus/mhi/core/boot.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/bus/mhi/core/boot.c
MHI work is currently scheduled on the global/system workqueue and can
encounter delays on a stressed system. To avoid those unforeseen
delays which can hamper bootup or shutdown times, use a dedicated high
priority workqueue instead of the global/system workqueue.
Signed-off-by: Bhaumik Bhatt
In some cases, the entry of device to RDDM execution environment
can occur after a significant amount of time has elapsed and a
SYS_ERROR state change event has already arrived. This can result
in scenarios where MHI controller and client drivers are unaware
of the error state of the device.
Current design allows a controller to register with MHI successfully
without the need to have any IRQs available for use. If no IRQs are
available, power up requests to MHI can fail after a successful
registration with MHI. Improve the design by checking for the number
of IRQs available sooner
From: Daeho Jeong
Added a new F2FS_IOC_GET_COMPRESS_OPTION ioctl to get file compression
option of a file.
struct f2fs_comp_option {
u8 algorithm; => compression algorithm
=> 0:lzo, 1:lz4, 2:zstd, 3:lzorle
u8 log_cluster_size; => log scale cluster size
From: Daeho Jeong
Added a new F2FS_IOC_SET_COMPRESS_OPTION ioctl to change file
compression option of a file.
struct f2fs_comp_option {
u8 algorithm; => compression algorithm
=> 0:lzo, 1:lz4, 2:zstd, 3:lzorle
u8 log_cluster_size; => log scale cluster
在 2020/10/29 16:02, Tiezhu Yang 写道:
Loongson 3A4000+ CPU has per-core Mail_Send register to send mail,
there is no need to maintain register address of each core and node,
just simply specify cpu number.
Signed-off-by: Lu Zeng
Signed-off-by: Jianmin Lv
Signed-off-by: Tiezhu Yang
---
This is a Chinese translated version of
Documentation/arm64/perf.rst
Signed-off-by: Bailu Lin
---
Changes in v2:
- Modify a translation of 'guest/host/blackout window' as Alex sugguested.
---
Documentation/arm64/perf.rst | 2 +
.../translations/zh_CN/arm64/index.rst|
On Thu, Oct 29, 2020 at 7:48 PM Hillf Danton wrote:
> On Thu, 29 Oct 2020 15:28:34 -0700 John Stultz wrote:
> > On Thu, Oct 29, 2020 at 12:10 AM Hillf Danton wrote:
> > > On Thu, 29 Oct 2020 00:16:24 + John Stultz wrote:
> > > > @@ -194,6 +210,9 @@ static int system_heap_mmap(struct dma_buf
Use kmemdup() for instructions using kmalloc() + memcpy(). More
information here: https://lwn.net/Articles/198928/
Issue reported by coccinelle script: scripts/coccinelle/api/memdup.cocci
Signed-off-by: Deepak R Varma
---
Changes since v1:
- Update patch subject and log message to match
在 2020/10/29 16:02, Tiezhu Yang 写道:
The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
write operations are meaningless, remove them.
Signed-off-by: Tiezhu Yang
---
arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8
arch/mips/loongson64/numa.c
Hi Coiby,
After removing CONFIG_PM_SLEEP, sprd_pmic_suspend/resume() would not
be built into symbol table with clang compiler though, that would
cause clang compiler report warnings of "unused function" if
CONFIG_PM_SLEEP is not set. So I also prefer to add a __maybe_unused
instead as other
In addition to DEBUGCTLMSR_LBR, any KVM trap caused by LBR msrs access
will result in a creation of guest LBR event per-vcpu.
If the guest LBR event is scheduled on with the corresponding vcpu context,
KVM will pass-through all LBR records msrs to the guest. The LBR callstack
mechanism
The vPMU uses GUEST_LBR_IN_USE_IDX (bit 58) in 'pmu->pmc_in_use' to
indicate whether a guest LBR event is still needed by the vcpu. If the
vcpu no longer accesses LBR related registers within a scheduling time
slice, and the enable bit of LBR has been unset, vPMU will treat the
guest LBR event as
Hi All,
PMU features matter. Please help review this rebased version for the
next kernel release and with this patch set, the following error will be
gone forever and cloud developers can better understand their
programs with less profiling overhead:
$ perf record -b lbr ${WORKLOAD}
or $
When vcpu sets DEBUGCTLMSR_LBR in the MSR_IA32_DEBUGCTLMSR, the KVM handler
would create a guest LBR event which enables the callstack mode and none of
hardware counter is assigned. The host perf would schedule and enable this
event as usual but in an exclusive way.
The guest LBR event will be
When the LBR records msrs has already been pass-through, there is no
need to call vmx_update_intercept_for_lbr_msrs() again and again, and
vice versa.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/pmu_intel.c | 13 +
arch/x86/kvm/vmx/vmx.h | 3 +++
2 files changed, 16
Userspace could enable guest LBR feature when the exactly supported
LBR format value is initialized to the MSR_IA32_PERF_CAPABILITIES
and the LBR is also compatible with vPMU version and host cpu model.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/capabilities.h | 9 -
The current vPMU only supports Architecture Version 2. According to
Intel SDM "17.4.7 Freezing LBR and Performance Counters on PMI", if
IA32_DEBUGCTL.Freeze_LBR_On_PMI = 1, the LBR is frozen on the virtual
PMI and the KVM would emulate to clear the LBR bit (bit 0) in
IA32_DEBUGCTL. Also, guest
To make code responsibilities clear, we may resue and invoke the
vmx_set_intercept_for_msr() in other vmx-specific files (e.g. pmu_intel.c),
so expose it to passthrough LBR msrs later.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/vmx.c | 2 +-
arch/x86/kvm/vmx/vmx.h | 2 ++
2 files changed, 3
The LBR could be enabled on the guest if host perf supports LBR
(checked via x86_perf_get_lbr()) and the vcpu model is compatible
with the host one.
If LBR is disabled on the guest, the bits [0, 5] of the read-only
MSR_IA32_PERF_CAPABILITIES which tells about the record format
stored in the LBR
SVM already has specific handlers of MSR_IA32_DEBUGCTLMSR in the
svm_get/set_msr, so the x86 common part can be safely moved to VMX.
Add vmx_supported_debugctl() to refactor the throwing logic of #GP.
Signed-off-by: Like Xu
---
arch/x86/kvm/vmx/capabilities.h | 5 +
arch/x86/kvm/vmx/vmx.c
On Intel platforms, KVM agent could configure MSR_IA32_PERF_CAPABILITIES
(such as unmask some vmx-supported bits in vcpu->arch.perf_capabilities)
to adjust the visibility of guest PMU features for vPMU-enabled guests.
Once MSR_IA32_PERF_CAPABILITIES is changed via vmx_set_msr() validly,
the
On Mon, Oct 26, 2020 at 5:01 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> gcc -Wextra warns about a function taking an enum argument
> being called with a bool:
>
> drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c: In
> function 'apply_degamma_for_user_regamma':
>
Hi Peter,
On Wed, Oct 28, 2020 at 08:59:10PM +0100, Peter Zijlstra wrote:
> On Wed, Oct 28, 2020 at 08:42:09PM +0100, Peter Zijlstra wrote:
> > On Wed, Oct 28, 2020 at 05:40:48PM +, Chris Wilson wrote:
> > > Quoting Chris Wilson (2020-10-27 16:34:53)
> > > > Quoting Peter Zijlstra (2020-10-27
On 10/28/2020 7:54 PM, Chunfeng Yun wrote:
> Use devm_platform_ioremap_resource(_byname) to simplify code
>
> Cc: Al Cooper
> Signed-off-by: Chunfeng Yun
Reviewed-by: Florian Fainelli
--
Florian
From: Chunyan Zhang
The hardware spinlock devices are defined in the DT, there's no need for
init calls order, remove boilerplate code by using module_platform_driver.
Signed-off-by: Chunyan Zhang
---
drivers/hwspinlock/sprd_hwspinlock.c | 13 +
1 file changed, 1 insertion(+), 12
On Thu, 29 Oct 2020 at 06:28, Dylan Hung wrote:
>
> The HVI3C shall be a group of I3C function, not an independent function.
> Correct the function name from "HVI3C" to "I3C".
>
> Signed-off-by: Dylan Hung
Fixes: f510f04c8c83 ("ARM: dts: aspeed: Add AST2600 pinmux nodes")
I have a few device
From: Chunyan Zhang
Changes since v1:
* Change to add __maybe_unsed rather than not use of_match_ptr().
Chunyan Zhang (2):
hwspinlock: sprd: fixed warning of unused variable
'sprd_hwspinlock_of_match'
hwspinlock: sprd: use module_platform_driver() instead postcore
initcall
From: Chunyan Zhang
The macro function of_match_ptr() is NULL if CONFIG_OF is not set, then
Clang compiler would complain the of_device_id variable is unused.
But using of_match_ptr() is space saving, for this case, the unused structure
'sprd_hwspinlock_of_match' would be not built into symbol
On Thu, 2020-10-29 at 09:24 +0100, Remi Pommarel wrote:
> Hi,
>
> On Thu, Oct 29, 2020 at 10:54:24AM +0800, Chunfeng Yun wrote:
> > Use devm_platform_ioremap_resource to simplify code
> >
> > Signed-off-by: Chunfeng Yun
> > ---
> > drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c | 4 +---
Applied. Thanks!
Alex
On Mon, Oct 26, 2020 at 5:01 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> core_link_write_dpcd() returns enum dc_status, not ddc_result:
>
> display/dc/core/dc_link_dp.c: In function 'dp_set_panel_mode':
> display/dc/core/dc_link_dp.c:4237:11: warning: implicit
ARC HSDK platform stopped booting on released v5.10-rc1, getting stuck
in startup of non master SMP cores.
This was bisected to upstream commit 7fef431be9c9ac25
"(mm/page_alloc: place pages to tail in __free_pages_core())"
That commit itself is harmless, it just exposed a subtle assumption in
our
Applied. Thanks!
Alex
On Tue, Oct 27, 2020 at 4:07 PM wrote:
>
> From: Tom Rix
>
> A semicolon is not needed after a switch statement.
>
> Signed-off-by: Tom Rix
> ---
> drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 2 +-
> drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
Applied. I dropped the first hunk as that fix had already been
submitted by someone else.
Alex
On Tue, Oct 27, 2020 at 3:07 PM wrote:
>
> From: Tom Rix
>
> A semicolon is not needed after a switch statement.
>
> Signed-off-by: Tom Rix
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 2 +-
>
Using DEFINE_DEBUGFS_ATTRIBUTE macro with debugfs_create_file_unsafe()
function in place of the debugfs_create_file() function will make the
file operation struct "reset" aware of the file's lifetime. Additional
details here: https://lists.archive.carbon60.com/linux/kernel/2369498
Issue reported
Using DEFINE_DEBUGFS_ATTRIBUTE macro with debugfs_create_file_unsafe()
function in place of the debugfs_create_file() function will make the
file operation struct "reset" aware of the file's lifetime. Additional
details here: https://lists.archive.carbon60.com/linux/kernel/2369498
Issue reported
syzbot suspects this issue was fixed by commit:
commit 1d0e850a49a5b56f8f3cb51e74a11e2fedb96be6
Author: David Howells
Date: Fri Oct 16 12:21:14 2020 +
afs: Fix cell removal
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=164fdca850
start commit: fb0155a0 Merge tag
Using DEFINE_DEBUGFS_ATTRIBUTE macro with debugfs_create_file_unsafe()
function in place of the debugfs_create_file() function will make the
file operation struct "reset" aware of the file's lifetime. Additional
details here: https://lists.archive.carbon60.com/linux/kernel/2369498
Issue reported
On Thu, Oct 29, 2020 at 7:34 PM Hillf Danton wrote:
> On Thu, 29 Oct 2020 12:34:51 -0700 John Stultz wrote:
> > As for your comment on HPAGE_PMD_ORDER (9 on arm64/arm) and
> > PAGE_ALLOC_COSTLY_ORDER(3), I'm not totally sure I understand your
> > question? Are you suggesting those values would be
Using DEFINE_DEBUGFS_ATTRIBUTE macro with debugfs_create_file_unsafe()
function in place of the debugfs_create_file() function will make the
file operation struct "reset" aware of the file's lifetime. Additional
details here: https://lists.archive.carbon60.com/linux/kernel/2369498
Issue reported
On Fri, Oct 30, 2020 at 2:46 AM Atish Patra wrote:
>
> On Thu, Oct 29, 2020 at 9:06 AM Guo Ren wrote:
> >
> > On Thu, Oct 29, 2020 at 10:34 AM Zong Li wrote:
> > >
> > > On Thu, Oct 29, 2020 at 8:23 AM Atish Patra wrote:
> > > >
> > > > On Wed, Oct 28, 2020 at 8:44 AM Guo Ren wrote:
> > > > >
> From: Colin King
> Sent: Friday, October 30, 2020 6:40 AM
>
> Pointer np is being initialized with a value that is never read and it is
> being
> updated with a value later on. The initialization is redundant and can be
> removed.
>
> Addresses-Coverity: ("Unused value")
> Signed-off-by:
Opps, I missed this.
We need v7... lol
2020년 10월 30일 (금) 오전 11:37, Chao Yu 님이 작성:
>
> On 2020/10/29 15:24, Chao Yu wrote:
> > On 2020/10/29 12:15, Daeho Jeong wrote:
>
> >> +inode_lock(inode);
> >
> > It's minor,
> >
> > inode_lock_shared()?
> >
> >> +
> >> +if
Support ECM mode based on cdc_ether with relative mii functions,
when CONFIG_USB_RTL8152 is not set, or the device is not supported
by r8152 driver.
Signed-off-by: Hayes Wang
---
v2:
Add include/linux/usb/r8152.h to avoid the warning about
no previous prototype for rtl8152_get_version.
On Thu, Oct 29, 2020 at 05:28:11PM -0700, Nick Desaulniers wrote:
>
> We already know that -fno-asynchronous-unwind-tables get dropped,
> hence this patch.
On arm64 only. Not on x86
> And we know -fomit-frame-pointer or
> -fno-omit-frame-pointer I guess gets dropped, hence your ask.
yep.
Using DEFINE_DEBUGFS_ATTRIBUTE macro with debugfs_create_file_unsafe()
function in place of the debugfs_create_file() function will make the
file operation struct "reset" aware of the file's lifetime. Additional
details here: https://lists.archive.carbon60.com/linux/kernel/2369498
Issue reported
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