across the context switch by locking the
hwspinlock in Linux and releasing it in the firmware.
Do not force the caller of __hwspin_trylock() to acquire a kernel
spinlock before acquiring the hwspinlock.
Cc: Jeffrey Hugo
Cc: Ohad Ben-Cohen
Cc: Suman Anna
Cc: Andy Gross
Signed-off-by: Lina Iyer
On Fri, May 01 2015 at 11:27 -0600, Jeffrey Hugo wrote:
On 5/1/2015 11:06 AM, Lina Iyer wrote:
diff --git a/drivers/hwspinlock/qcom_hwspinlock.c
b/drivers/hwspinlock/qcom_hwspinlock.c
index 93b62e0..043c62c 100644
--- a/drivers/hwspinlock/qcom_hwspinlock.c
+++ b/drivers/hwspinlock
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
SoCs.
Based on initial effort by Kumar Gala
Signed-off-by: Bjorn Andersson
---
[...]
+#include "hwspinlock_internal.h"
+
+#define QCOM_MUTEX_APPS_PROC_ID
---
drivers/hwspinlock/qcom_hwspinlock.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/hwspinlock/qcom_hwspinlock.c
b/drivers/hwspinlock/qcom_hwspinlock.c
index 93b62e0..7642524 100644
--- a/drivers/hwspinlock/qcom_hwspinlock.c
+++ b/drivers/hwspinlo
On Thu, Mar 12 2015 at 13:43 -0600, Andy Gross wrote:
On Thu, Mar 12, 2015 at 01:31:50PM -0600, Lina Iyer wrote:
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
>Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
>SoCs.
>
>Based on initial effort b
On Thu, Mar 12 2015 at 14:35 -0600, Stephen Boyd wrote:
On 03/12/15 12:38, Lina Iyer wrote:
---
sign off?
:) I was just hacking it to make it easier to understand. Sure.
drivers/hwspinlock/qcom_hwspinlock.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff
On Thu, Mar 12 2015 at 14:49 -0600, Andy Gross wrote:
On Thu, Mar 12, 2015 at 01:38:28PM -0600, Lina Iyer wrote:
static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
{
struct regmap_field *field = lock->priv;
u32 lock_owner;
int ret;
+ u32 proc
On Thu, Mar 12 2015 at 15:12 -0600, Stephen Boyd wrote:
On 03/12/15 13:48, Lina Iyer wrote:
On Thu, Mar 12 2015 at 14:35 -0600, Stephen Boyd wrote:
On 03/12/15 12:38, Lina Iyer wrote:
---
sign off?
:) I was just hacking it to make it easier to understand. Sure.
drivers/hwspinlock
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
SoCs.
Based on initial effort by Kumar Gala
Signed-off-by: Bjorn Andersson
+config HWSPINLOCK_QCOM
+ tristate "Qualcomm Hardware Spinlock device"
+ depend
On Wed, Mar 18 2015 at 09:56 -0600, Bjorn Andersson wrote:
On Thu 12 Mar 12:31 PDT 2015, Lina Iyer wrote:
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
>Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
>SoCs.
>
>Based on initial effort by Kumar Gal
On Wed, Mar 18 2015 at 10:12 -0600, Bjorn Andersson wrote:
On Thu 12 Mar 15:29 PDT 2015, Lina Iyer wrote:
On Fri, Feb 27 2015 at 15:30 -0700, Bjorn Andersson wrote:
>Add driver for Qualcomm Hardware Mutex block found in many Qualcomm
>SoCs.
>
>Based on initial effort by Kumar Gal
On Fri, Mar 13 2015 at 14:02 -0600, Andy Gross wrote:
On Thu, Mar 12, 2015 at 04:16:00PM -0600, Lina Iyer wrote:
>It looks like the remote side unlocks it too? It doesn't seem like this
>will work with the framework very well. The framework has a kernel
>spinlock attached to
On Tue, Feb 03 2015 at 12:20 -0700, Eduardo Valentin wrote:
On Tue, Feb 03, 2015 at 10:32:11AM -0700, Lina Iyer wrote:
>
>Well, I am not convinced drivers really need to be aware of these trip
>types. Which kind of drivers are we talking? Thermal zone drivers?
>cooling device dr
On Wed, Jan 28 2015 at 14:42 -0700, Javi Merino wrote:
The power allocator governor is a thermal governor that controls system
and device power allocation to control temperature. Conceptually, the
implementation divides the sustainable power of a thermal zone among
all the heat sources in that z
On Tue, Feb 03 2015 at 08:30 -0700, Eduardo Valentin wrote:
On Tue, Feb 03, 2015 at 01:03:37PM +, Javi Merino wrote:
On Mon, Feb 02, 2015 at 11:51:20PM +, Lina Iyer wrote:
> On Wed, Jan 28 2015 at 14:42 -0700, Javi Merino wrote:
> >The power allocator governor is a thermal gove
On Tue, Feb 03 2015 at 02:59 -0700, Stanimir Varbanov wrote:
Hi Gilad,
Thanks for the patch.
On 01/31/2015 02:46 AM, Gilad Avidov wrote:
Qualcomm PMIC Arbiter version-2 changes from version-1 are:
- Some different register offsets.
- New channel register space, one per PMIC peripheral (ppid).
On Sat, Jun 27 2015 at 05:25 -0600, Ohad Ben-Cohen wrote:
Hi Lina,
On Sat, Jun 27, 2015 at 6:05 AM, Lina Iyer wrote:
Hi Ohad,
Any comments?
Sorry, I was under the impression the discussion with Bjorn is still open.
I am of the opinion that the platform driver and the framework should
Hi Marc,
Thanks for rebasing on top of my latest series.
On Tue, Oct 06 2015 at 08:27 -0600, Marc Titinger wrote:
Devices may register an intermediate retention state into the domain upon
I may agree with the usability of dynamic adding a state to the domain,
but I dont see why a device attac
On Tue, Oct 06 2015 at 08:27 -0600, Marc Titinger wrote:
This patch allows cluster-level C-states to being soaked in as generic
domain power states, in order for the domain governor to chose the most
efficient power state compatible with the device constraints. Similarly,
devices can register pow
On Fri, Oct 09 2015 at 03:39 -0600, Marc Titinger wrote:
On 08/10/2015 18:11, Lina Iyer wrote:
Hi Marc,
Thanks for rebasing on top of my latest series.
On Tue, Oct 06 2015 at 08:27 -0600, Marc Titinger wrote:
Devices may register an intermediate retention state into the domain upon
I may
Thanks for the review Rob.
On Fri, Mar 15 2019 at 17:37 -0600, Rob Herring wrote:
On Wed, Mar 13, 2019 at 03:18:40PM -0600, Lina Iyer wrote:
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
routed to the PDC as interrupts that can be used to wake the system up
from deep
PDC when the IRQ is masked and unmasked, instead
use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE
register at the PDC. The PDC's IRQ_ENABLE register is only used during
the monitoring mode when the system is asleep and is not needed for
active mode detection.
Signed-off-by: Lina
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index be0022e09465
Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 83 ++-
1 file changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl
parent.
Co-developed-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 104 ---
include/linux/soc/qcom/irq.h | 34
2 files changed, 129 insertions(+), 9 deletions(-)
create mode 100644 include/linux/soc/qcom/irq.h
diff
Enable PDC interrupt controller for SDM845 devices. The interrupt
controller can detect wakeup capable interrupts when the SoC is in a low
power state.
Signed-off-by: Lina Iyer
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b
Replace gpiochip_irqchip_add() and gpiochip_set_chained_irqchip() calls
by populating the gpio_irq_chip data structures instead.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a
From: Maulik Shah
On certain QTI chipsets some GPIOs are direct-connect interrupts
to the GIC.
Even when GPIOs are not used for interrupt generation and interrupt
line is disabled, it does not prevent interrupt to get pending at
GIC_ISPEND. When drivers call enable_irq unwanted interrupt occures
From: Maulik Shah
Add irqchip calls to set/get interrupt status from the parent interrupt
controller.
Signed-off-by: Maulik Shah
---
drivers/irqchip/qcom-pdc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
ind
Some interrupt controllers in a SoC, are always powered on and have a
select interrupts routed to them, so that they can wakeup the SoC from
suspend. Add wakeup-parent DT property to refer to these interrupt
controllers.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings
PDC always-on interrupt controller can detect certain GPIOs even when
the TLMM interrupt controller is powered off. Link the PDC as TLMM's
wakeup parent.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boo
hen the GPIO is enabled
as an interrupt.
Please consider reviewing these patches.
Thanks,
Lina
Lina Iyer (12):
irqdomain: add bus token DOMAIN_BUS_WAKEUP
drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask
drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs
of
differently. So, in
addition to configuring the PDC, configure the interface registers as
well.
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 93 ++
1 file changed, 93 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index
with the wakeup interrupt controller
and ensure the wakeup GPIOs are handled correctly.
Signed-off-by: Maulik Shah
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 114 +
drivers/pinctrl/qcom/pinctrl-msm.h | 16
2 files changed, 130 insertions
firmware using the SCM interface. Add a flag to indicate if the
register is to be written using SCM interface.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/interrupt-controller/qcom,pdc.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff
quot;
that indicates the wake-up domain. This slightly abuses the notion of
bus, but also radically simplifies the design of such a driver. Between
two evils, we choose the least damaging.
Suggested-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
include/linux/irqdomain.h | 1 +
1 file changed, 1 insertio
On Fri, Aug 30 2019 at 08:50 -0600, Marc Zyngier wrote:
[Please use my kernel.org address in the future. The days of this
arm.com address are numbered...]
Sure, will update and repost.
On 29/08/2019 19:11, Lina Iyer wrote:
Introduce a new domain for wakeup capable GPIOs. The domain can be
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
On 02/09/2019 14:38, Rob Herring wrote:
On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
In addition to configuring the PDC, additional registers that interface
the GIC have to be configured to match the GPIO type. The registers
On Wed, Sep 11 2019 at 04:05 -0600, Linus Walleij wrote:
On Thu, Aug 29, 2019 at 8:47 PM Lina Iyer wrote:
+- qcom,scm-spi-cfg:
+ Usage: optional
+ Value type:
+ Definition: Specifies if the SPI configuration registers have to be
+ written from the firmware
On Thu, Sep 05 2019 at 18:39 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-08-29 11:11:51)
When an interrupt is to be serviced, the convention is to mask the
interrupt at the chip and unmask after servicing the interrupt. Enabling
and disabling the interrupt at the PDC irqchip causes an
On Wed, Sep 11 2019 at 04:19 -0600, Linus Walleij wrote:
On Thu, Aug 29, 2019 at 7:35 PM Lina Iyer wrote:
Replace gpiochip_irqchip_add() and gpiochip_set_chained_irqchip() calls
by populating the gpio_irq_chip data structures instead.
Signed-off-by: Lina Iyer
This is mostly fixed upstream
Sorry, I couldn't get to this earlier.
On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-03 10:07:22)
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
>On 02/09/2019 14:38, Rob Herring wrote:
>> On Thu, Aug 29, 2019 at 12:11:54PM -0600, L
quot;
that indicates the wake-up domain. This slightly abuses the notion of
bus, but also radically simplifies the design of such a driver. Between
two evils, we choose the least damaging.
Suggested-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
include/linux/irqdomain.h | 1 +
1 file changed, 1 insertio
PDC when the IRQ is masked and unmasked, instead
use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE
register at the PDC. The PDC's IRQ_ENABLE register is only used during
the monitoring mode when the system is asleep and is not needed for
active mode detection.
Signed-off-by: Lina
firmware using the SCM interface. Add a flag to indicate if the
register is to be written using SCM interface.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 13 -
1 file changed, 12 insertions(+), 1 deletion
na
[1].
https://lore.kernel.org/linux-gpio/20190808123242.5359-1-linus.wall...@linaro.org/
[2]. https://lkml.org/lkml/2019/5/7/1173
[3]. https://lore.kernel.org/r/20190819084904.30027-1-linus.wall...@linaro.org
[4]. https://lore.kernel.org/r/20190724083828.7496-1-linus.wall...@linaro.org
Lina Iyer (12):
Newer SoCs have increased the number of interrupts routed to the PDC
interrupt controller. Update the definition of max PDC interrupts.
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/qcom-pdc.c b
with the wakeup interrupt controller
and ensure the wakeup GPIOs are handled correctly.
Signed-off-by: Maulik Shah
Signed-off-by: Lina Iyer
Changes in RFC v2:
- Define irq_domain_qcom_handle_wakeup()
- Rebase on top of GPIO hierarchy support in linux-next
- Set the
y to clear the interrupt before enabling the
interrupt.
Signed-off-by: Maulik Shah
[updated commit text and minor code fixes]
Signed-off-by: Lina Iyer
---
Changes in RFC v2 -
- Rephrase commit text
- Address code review comments
---
include/linux/irq.h | 6 ++
kernel/irq/chi
Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC.
Signed-off-by: Lina Iyer
---
Changes in RFC v2:
- Rearranged GPIO wakeup parent map
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git
parent.
Co-developed-by: Stephen Boyd
Signed-off-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in RFC v2:
- Move irq_domain_qcom_handle_wakeup to the patch where it is
used
- Replace #define definitons
- Add Signed-off-by and other minor changes
was
used as a GPIO.
Signed-off-by: Maulik Shah
[updated commit text]
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index affb0bfa..2b49e70 100644
--- a
Enable PDC interrupt controller for SDM845 devices. The interrupt
controller can detect wakeup capable interrupts when the SoC is in a low
power state.
Signed-off-by: Lina Iyer
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index be0022e..41455b8 100644
Some interrupt controllers in a SoC, are always powered on and have a
select interrupts routed to them, so that they can wakeup the SoC from
suspend. Add wakeup-parent DT property to refer to these interrupt
controllers.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
Reviewed-by: Rob
differently. So, in
addition to configuring the PDC, configure the interface registers as
well.
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 93 ++
1 file changed, 93 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom
PDC always-on interrupt controller can detect certain GPIOs even when
the TLMM interrupt controller is powered off. Link the PDC as TLMM's
wakeup parent.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boo
Adding Sibi
On Fri, Sep 13 2019 at 13:53 -0600, Lina Iyer wrote:
Sorry, I couldn't get to this earlier.
On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-03 10:07:22)
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
On 02/09/2019 14:38, Rob He
On Fri, Sep 20 2019 at 16:22 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-11 09:15:57)
On Thu, Sep 05 2019 at 18:39 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-08-29 11:11:51)
>> When an interrupt is to be serviced, the convention is to mask the
>> interrupt
On Tue, Jul 16 2019 at 08:47 -0600, Sudeep Holla wrote:
On Mon, May 13, 2019 at 09:22:59PM +0200, Ulf Hansson wrote:
From: Lina Iyer
In the hierarchical layout, we are creating power domains around each CPU
and describes the idle states for them inside the power domain provider
node. Note
On Thu, Jul 18 2019 at 10:55 -0600, Ulf Hansson wrote:
On Thu, 18 Jul 2019 at 15:31, Lorenzo Pieralisi
wrote:
On Thu, Jul 18, 2019 at 12:35:07PM +0200, Ulf Hansson wrote:
> On Tue, 16 Jul 2019 at 17:53, Lorenzo Pieralisi
> wrote:
> >
> > On Mon, May 13, 2019 at 09:22:56PM +0200, Ulf Hansson w
Do this by explicitly switch to Platform Coordinated mode during boot.
> >
> > Finally, the actual initialization of the PM domain data structures, is
> > done via calling the new shared function, psci_dt_init_pm_domains().
> > However, this is implemented by subsequent cha
On Thu, Jul 25 2019 at 09:44 -0600, Doug Anderson wrote:
Hi,
On Thu, Jul 25, 2019 at 8:18 AM Lina Iyer wrote:
On Wed, Jul 24 2019 at 17:28 -0600, Doug Anderson wrote:
>Hi,
>
>On Wed, Jul 24, 2019 at 1:36 PM Lina Iyer wrote:
>>
>> On Wed, Jul 24 2019 at 13:38 -060
On Thu, Dec 20 2018 at 13:03 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-12-19 14:11:03)
+
+static int msm_gpio_domain_alloc(struct irq_domain *domain, unsigned int virq,
+unsigned int nr_irqs, void *arg)
+{
+ int ret;
+ irq_hw_number_t hwirq
atch, but
that may be a more complicated change because it looks like
tcs_tx_done() just iterates through the indices of the queue and
completes each message instead of tracking the last inserted message and
completing that first.
Cc: Lina Iyer
Cc: "Raju P.L.S.S.S.N"
Cc: Matthias Kaehlcke
Cc: Ev
parent.
Also, provide the map of the PDC pins for the GPIOs for SDM845.
Co-developed-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in v2:
- Remove separate file for PDC GPIO map data
- Error checks and return
- Whitespace fixes
---
drivers/irqchip/qcom-pdc.c
Enable PDC interrupt controller for SDM845 devices. The interrupt
controller can detect wakeup capable interrupts when the SoC is in a low
power state.
Signed-off-by: Lina Iyer
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Use updated address specification in reg
- Rename to pdc_intc
- Sort per address in DT
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9
Add new bus token to describe domains that are wakeup capable.
Suggested-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
include/linux/irqdomain.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
index 35965f41d7be..05055bc992ab 100644
be a
parent to other interrupt controllers and program additional registers
when an IRQ has its wake capability enabled or disabled.
Signed-off-by: Thierry Reding
Signed-off-by: Lina Iyer
---
drivers/gpio/gpiolib.c | 15 +++
include/linux/gpio/driver.h | 6 ++
2 files
-off-by tags
- Enable QCOM_PDC in defconfig
Do note that this patch uses the register address convention updated by Bjorn
per [3].
Thanks,
Lina
[1]. https://lkml.org/lkml/2018/12/19/807
[2]. https://lkml.org/lkml/2018/12/19/813
[3]. https://lkml.org/lkml/2019/1/17/924
Lina Iyer (7
Setup PDC wakeup parent for TLMM for SDM845 SoC.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index e55100c2705e..89982f6ee147 100644
--- a/arch
ve as well as the
TLMM and therefore the GPIOs need to be masked at TLMM to avoid
duplicate interrupts. To enable both these configurations to exist,
allow the parent irqchip to dictate the TLMM irqchip's behavior when
masking/unmasking the interrupt.
Co-developed-by: Stephen Boyd
Signed-of
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
routed to the PDC as interrupts that can be used to wake the system up
from deep low power modes and suspend.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../devicetree/bindings/pinctrl/qcom,sdm845
On Mon, Mar 18 2019 at 11:54 -0600, Marc Zyngier wrote:
On Wed, 13 Mar 2019 15:18:37 -0600
Lina Iyer wrote:
Please do Cc Rob when posting DT related patches.
Some interrupt controllers in a SoC, are always powered on and have a
select interrupts routed to them, so that they can wakeup the
On Wed, Apr 17 2019 at 07:59 -0600, Linus Walleij wrote:
On Thu, Mar 21, 2019 at 10:54 PM Stephen Boyd wrote:
Quoting Marc Zyngier (2019-03-16 04:39:48)> > On Fri, 15 Mar 2019 09:28:31 -0700
> Stephen Boyd wrote:
>
> > Quoting Lina Iyer (2019-03-13 14:18:41)
> > > @
ve as well as the
TLMM and therefore the GPIOs need to be masked at TLMM to avoid
duplicate interrupts. To enable both these configurations to exist,
allow the parent irqchip to dictate the TLMM irqchip's behavior when
masking/unmasking the interrupt.
Co-developed-by: Stephen Boyd
Signed-of
be a
parent to other interrupt controllers and program additional registers
when an IRQ has its wake capability enabled or disabled.
Signed-off-by: Thierry Reding
Signed-off-by: Lina Iyer
---
drivers/gpio/gpiolib.c | 15 +++
include/linux/gpio/driver.h | 6 ++
2 files
ask and copy the
output interrupt specifier from the map to irq_fwspec per the mask in
irqdomain-map-pass-thru property for the matched interrupt.
Signed-off-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in v5:
- Fix returning 0 when no match is found
Changes in v4:
- F
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Use updated address specification in reg
- Rename to pdc_intc
- Sort per address in DT
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9
parent.
Co-developed-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in v5:
- Define invalid wakeup interrupt
Changes in v4:
- Remove vestigial changes from v2
Changes in v3:
- Remove PDC GPIO map data (moved to DT)
- hwirq passed in .alloc() is a PDC pin now
RQ.
Signed-off-by: Lina Iyer
---
drivers/gpio/gpiolib.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 4a9a6d4afe6e..77317435e2b2 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1825,6 +1825,19 @@ EX
needs to exist to associate the same interrupt line on multiple
interrupt controllers. Providing this map in every driver is cumbersome.
Let's add this in the device tree and document the properties to map the
interrupt specifiers
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina
quot;
that indicates the wake-up domain. This slightly abuses the notion of
bus, but also radically simplifies the design of such a driver. Between
two evils, we choose the least damaging.
Suggested-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in v4:
- Update commit text
---
inc
Enable PDC interrupt controller for SDM845 devices. The interrupt
controller can detect wakeup capable interrupts when the SoC is in a low
power state.
Signed-off-by: Lina Iyer
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b
interrupt map.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 79 ++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
b/Documentation/devicetree
fwspec.
The solution to this problem is still at large and I would like to
solicit feedback on this.
Appreciate your time.
Thanks,
Lina
[1]. https://patchwork.kernel.org/cover/10851807/
Lina Iyer (9):
gpio: allow gpio_to_irq to use OF variants for gpiochips
irqdomain: add bus token DOMAIN_BUS_
Setup PDC wakeup parent for TLMM for SDM845 SoC.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Provide irqdomain-map for GPIOs that map to PDC
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts
On Wed, Jul 24 2019 at 13:38 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-24 07:52:51)
On Tue, Jul 23 2019 at 14:11 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-22 14:53:38)
>> Avoid locking in the interrupt context to improve latency. Since we
>> don't l
On Wed, Jul 24 2019 at 17:28 -0600, Doug Anderson wrote:
Hi,
On Wed, Jul 24, 2019 at 1:36 PM Lina Iyer wrote:
On Wed, Jul 24 2019 at 13:38 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-24 07:52:51)
>> On Tue, Jul 23 2019 at 14:11 -0600, Stephen Boyd wrote:
>> >
On Mon, Jul 29 2019 at 14:56 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-29 12:01:39)
On Thu, Jul 25 2019 at 09:44 -0600, Doug Anderson wrote:
>On Thu, Jul 25, 2019 at 8:18 AM Lina Iyer wrote:
>>
>> On Wed, Jul 24 2019 at 17:28 -0600, Doug Anderson wrote:
>> >
On Fri, Jul 19 2019 at 12:20 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-01 08:29:06)
From: "Raju P.L.S.S.S.N"
tcs->lock was introduced to serialize access with in TCS group. But
even without tcs->lock, drv->lock is serving the same purpose. So
use a single drv
On Mon, Jul 22 2019 at 12:18 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-22 09:20:03)
On Fri, Jul 19 2019 at 12:20 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-01 08:29:06)
>> From: "Raju P.L.S.S.S.N"
>>
>> tcs->lock was introduced to seria
ides the all necessary
synchronization. So remove locking around TCS group and simply use the
drv->lock instead.
Signed-off-by: Raju P.L.S.S.S.N
[ilina: split patch into multiple files, update commit text]
Signed-off-by: Lina Iyer
---
Changes in v2:
- Split the patches into multiple
Since drv->tcs_in_use is updated when the DRV_STATUS is updated, we
could simply use the former to determine if the TCS is idle or not.
Therefore, remove redundant TCS register read.
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 3 +--
1 file changed, 1 insertion(+), 2 deleti
e TCS.
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index 5ede8d6de3ad..694ba881624e 100644
--- a/drivers/soc/qcom/rpmh-rsc.c
+++ b/drivers/soc/qcom/rpmh-
.N
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh-internal.h | 4 ++--
drivers/soc/qcom/rpmh-rsc.c | 2 +-
drivers/soc/qcom/rpmh.c | 21 -
3 files changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/soc/qcom/rpmh-internal.h b/drivers/soc
On Tue, Jul 23 2019 at 12:22 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-22 14:53:37)
From: "Raju P.L.S.S.S.N"
The tcs->lock was introduced to serialize access with in TCS group. But,
drv->lock is still needed to synchronize core aspects of the
communication. This pu
On Tue, Jul 23 2019 at 14:11 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-22 14:53:38)
Avoid locking in the interrupt context to improve latency. Since we
don't lock in the interrupt context, it is possible that we now could
race with the DRV_CONTROL register that writes the e
On Tue, Jul 23 2019 at 14:19 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-23 12:21:59)
On Tue, Jul 23 2019 at 12:22 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-22 14:53:37)
>> From: "Raju P.L.S.S.S.N"
>>
>> The tcs->lock was introduced to
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