On Wed, 2013-10-02 at 17:35 +0200, Michal Simek wrote:
>
> Through firmware interface:
> cat /sys/class/fpga_manager/fpga0/name
> echo -n fpga.bin > /sys/class/fpga_manager/fpga0/firmware
>
> Through sysfs bin file:
> cat /sys/class/fpga_manager/fpga0/fpga_config_state
> echo -n write_init > /sy
On Fri, 2013-10-04 at 19:44 +0200, Michal Simek wrote:
> On 10/04/2013 06:46 PM, H. Peter Anvin wrote:
> > On 10/04/2013 07:28 AM, Michal Simek wrote:
> >> On 10/04/2013 04:21 PM, H. Peter Anvin wrote:
> >>> Yes; I never got too corner Greg ;)
> >>>
> >>> Greg Kroah-Hartman wrote:
> On Fri, O
On Fri, 2013-10-04 at 17:27 +0200, Michal Simek wrote:
> Hi,
>
> On 10/03/2013 11:46 PM, Alan Tull wrote:
> > On Wed, 2013-10-02 at 17:35 +0200, Michal Simek wrote:
> >
> >>
> >> Through firmware interface:
> >> cat /sys/class/fpga_manag
On Fri, 2013-10-04 at 18:28 +0200, Michal Simek wrote:
> On 10/02/2013 07:46 PM, Jason Gunthorpe wrote:
> > On Wed, Oct 02, 2013 at 05:35:58PM +0200, Michal Simek wrote:
> >
> >> +What: /sys/class/fpga_manager/fpga/fpga_config_state
> >> +Date: October 2013
> >> +KernelVers
On Wed, 2013-09-18 at 14:32 -0600, Jason Gunthorpe wrote:
> On Wed, Sep 18, 2013 at 03:15:17PM -0400, Jason Cooper wrote:
>
> > + Jason Gunthorpe
>
> Thanks, looks interesting, we could possibly use this interface if it
> met our needs..
>
> > On Wed, Sep 18, 2013 at 05:56:39PM +0200, Michal S
On Thu, 2013-09-19 at 07:18 -0700, Greg KH wrote:
> On Thu, Sep 19, 2013 at 04:10:46PM +0200, Michal Simek wrote:
> > On 09/19/2013 04:06 PM, Greg KH wrote:
> > > On Thu, Sep 19, 2013 at 02:52:37PM +0200, Pavel Machek wrote:
> > >> On Thu 2013-09-19 13:22:00, Michal Simek wrote:
> > >>> On 09/19/20
> >> +/**
> >> + * fpga_mgr_attr_read - Read data from fpga
> >> + * @dev: Pointer to the device structure
> >> + * @attr: Pointer to the device attribute structure
> >> + * @buf: Pointer to the buffer location
> >> + *
> >> + * Function reads fpga bitstream and copy them to output buffer
> >> + *
On Tue, 2013-10-08 at 15:00 +0200, Michal Simek wrote:
> On 10/07/2013 05:07 PM, H. Peter Anvin wrote:
> > Special soft IP presenting a PCI device to the host.
>
> ok. It means that you should need just different backend for this device
> which is able to communicate over PCI.
>
> I still can't s
On Fri, 2013-10-04 at 16:33 -0700, Greg Kroah-Hartman wrote:
> On Fri, Oct 04, 2013 at 11:12:13AM -0700, H. Peter Anvin wrote:
> > On 10/04/2013 10:44 AM, Michal Simek wrote:
> > >
> > > If you look at it in general I believe that there is wide range of
> > > applications which just contain one b
On Thu, 2013-09-19 at 13:02 +0200, Michal Simek wrote:
> On 09/19/2013 12:08 PM, Pavel Machek wrote:
> > Hi!
> >
> >> The firmware approach is interesting. It might be less flexible
> >> compared with my original code (see link to git below) that this is
> >
> > On the other hand... that's the i
> I have ported the altera fpga manager driver to work with your version
> of the fpga manager framework. It works fine if I use the
> firmware_class.c's built-in support to load the firmware, but not with a
> userspace helper.
>
Hi Michal,
I cleaned up my udev rules and now I see the userspa
On Tue, 2013-09-24 at 17:58 +0200, Michal Simek wrote:
> Hi,
>
> On 09/24/2013 05:55 PM, Alan Tull wrote:
> >
> >> I have ported the altera fpga manager driver to work with your version
> >> of the fpga manager framework. It works fine if I use the
> >&
> >
> > * Add this udev rule:
> >SUBSYSTEM=="firmware", ACTION=="add", RUN+="/lib/udev/hotplug-script"
> >
> > * Check that there aren't other 'firmware' udev rules to get in the
> > way.
>
> Hm, don't do that, all "modern" distros will not do firmware loading
> through udev anymore, so pl
> >
> > For the Zynq based product I am working on, we encourage the end user to
> > create their own bitstreams to customize their application. So we need
> > an easy way for the user to load a bitstream. cat foo.bin > /dev/xdevcfg
> > works well for us.
>
> You probably don't care if this will
On Wed, 2012-11-07 at 09:06 +0100, Pantelis Antoniou wrote:
> Hi Grant,
>
> On Nov 6, 2012, at 9:45 PM, Grant Likely wrote:
>
> > On Tue, Nov 6, 2012 at 7:34 PM, Pantelis Antoniou
> > wrote:
> >> On Nov 6, 2012, at 12:14 PM, Grant Likely wrote:
> >>> On Tue, Nov 6, 2012 at 10:30 AM, Pantelis Ant
mework for AFU, including
> device file operation framework.
>
> Signed-off-by: Tim Whisonant
> Signed-off-by: Enno Luebbers
> Signed-off-by: Shiva Rao
> Signed-off-by: Christopher Rauer
> Signed-off-by: Xiao Guangrong
> Signed-off-by: Wu Hao
Acked-by: Alan Tull
> --
(AFU) driver.
>
> Signed-off-by: Tim Whisonant
> Signed-off-by: Enno Luebbers
> Signed-off-by: Shiva Rao
> Signed-off-by: Christopher Rauer
> Signed-off-by: Xiao Guangrong
> Signed-off-by: Wu Hao
Acked-by: Alan Tull
> ---
> v2: rebased
> ---
> drivers/fpg
stopher Rauer
> Signed-off-by: Xiao Guangrong
> Signed-off-by: Wu Hao
Acked-by: Alan Tull
> ---
> v2: switched to GPLv2 license.
> ---
> Documentation/ioctl/ioctl-number.txt | 1 +
> drivers/fpga/intel-fme-main.c| 12 +
> include/uapi/linux/intel-fpga.h | 5
o
> Signed-off-by: Christopher Rauer
> Signed-off-by: Wu Hao
Acked-by: Alan Tull
> ---
> drivers/fpga/Kconfig | 7
> drivers/fpga/Makefile| 1 +
> drivers/fpga/intel-fpga-fme-br.c | 77
>
> 3 file
hat. I hope to post the next
version in a couple weeks.
Alan
>
> On Thu, Jul 6, 2017 at 11:47 AM, Alan Tull wrote:
>> The FPGA manager has been simplified to have a single
>> fpga_mgr_load function which replaces the three
>> fpga_mgr_*load* functions.
>>
>> Th
On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao wrote:
Hi Hao,
> For FPGA Management Engine (FME), it requires fpga_for_each_port callback
> for actions on ports, so export this function from PCIe driver by adding
> the callback to the platform data.
>
> Signed-off-by: Tim Whisonant
> Signed-off-by: En
t I'll comment
>> here for now. I'm trying to keep track of everything that resets the
>> port. The port gets reset in afu_probe, fme_probe, the AFU file
>> release, and intel-pcie.c after parsing the features. Also the port
>> is esentially reset after d
Get the FPGA manager during region creation.
This is a baby step in refactoring the FPGA region code to
separate out common FPGA region code from FPGA region
Device Tree overlay support.
Signed-off-by: Alan Tull
---
v2: split out from another patch
v3: no change to this patch in this version of
* of_fpga_region_notify_post_remove
* of_fpga_region_notify
* of_fpga_region_probe
* of_fpga_region_remove
Create two new functions with some code from fpga_region_init/exit.
* of_fpga_region_init
* of_fpga_region_exit
Signed-off-by: Alan Tull
---
v2: split out code changes into other patches, only move code here
v3: updated to
Tree overlay support.
Signed-off-by: Alan Tull
---
v2: split out from another patch
v3: update comments
minor changes in flow
v4: no change to this patch in this version of patchset
v5: no change to this patch in this version of patchset
---
drivers/fpga/fpga-region.c | 122
The FPGA may already have a static image programmed when
Linux boots. In that case a DT overlay may be used to add
the devices that already exist. This commit allows that
by shuffling the order of some checks.
Signed-off-by: Alan Tull
---
v4: Patch added to patchset in v4
v5: no change to this
* Create fpga-region.h.
* Export fpga_region_program_fpga.
* Move struct fpga_region and other things to the header.
This is a step in separating FPGA region common code
from Device Tree support.
Signed-off-by: Alan Tull
---
v2: split out from another patch
update author email
v3: changes
to the region struct
* use region->info in of_fpga_region_get_bridges
Signed-off-by: Alan Tull
---
v2: split out from another patch
v3: use region->info, remove info param where applicable
v4: no change to this patch in this version of patchset
v5: add back in fpga_mgr_
of the region.
* of_fpga_region_get_bridges
change second parameter to FPGA image info.
Export of_fpga_region_find as well.
Signed-off-by: Alan Tull
---
v2: split out from another patch
v3: no changes in patch for this version of patchset
v4: no change to this patch in this version of patchset
v5: no change to
Add a function for searching the fpga-region class. This
will be useful when device tree code is no longer in the
same file that declares the fpga-region class. Another
step in separating common FPGA region code from device
tree support.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
<*> Technologic Systems TS-73xx SBC FPGA Manager
<*> FPGA Bridge Framework
<*> Altera SoCFPGA FPGA Bridges
<*> Altera FPGA Freeze Bridge
<*> Xilinx LogiCORE PR Decoupler
<*> FPGA Region
<*> FPGA Region De
Use FPGA image info (region->info) when region code is
programming the FPGA to pass in multiple parameters.
This is a baby step in refactoring the FPGA region code to
separate out common FPGA region code from FPGA region
Device Tree overlay support.
Signed-off-by: Alan Tull
---
v2: split
-off-by: Alan Tull
---
v4: Patch added to patchset in v4
v5: no change to this patch in this version of patchset
---
drivers/fpga/fpga-bridge.c | 1 +
drivers/fpga/fpga-mgr.c | 1 +
drivers/fpga/fpga-region.c | 1 +
include/linux/fpga/fpga-bridge.h | 2 ++
include/linux/fpga
hat overlays that make DT changes
without reprogramming the FPGA are exempt from this restriction.
Signed-off-by: Alan Tull
---
v2: split out from another patch
v3: better explanation in header
v4: no change to this patch in this version of patchset
v5: no change to this patch in this version of patch
FPGA region
Device Tree overlay support.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
v2: split out from another patch
v3: s/dev/®ion->dev/ in one place
add Moritz' ack
v4: no change to this patch in this version of patchset
v5: no change to this patch in this version of
_info.
API documentation has been updated and a new document for
FPGA region has been added.
Signed-off-by: Alan Tull
---
v2: add fpga_image_info_alloc/free
update copyright and author email
v3: fix bisectibility
v4: fix return value of fpga_image_info_alloc()
save device in struct fpga_image
Remove of_node_get/put in fpga_region_get/put. Not
needed and will get in the way when I separate out
the common FPGA region code from Device Tree support
code.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
v2: split out from another patch
v3: Add Moritz' ack
v4: no change to
move #ifndef before #includes in headers
* Spelling fixes and other nits
Alan Tull (18):
fpga: bridge: support getting bridge from device
fpga: mgr: API change to replace fpga load functions with single
function
fpga: mgr: separate getting/locking FPGA manager
fpga: region: use dev_err inste
Use dev_err messages instead of pr_err.
Also s/®ion->dev/dev/ in two places where we already
have dev = ®ion->dev.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
v2: new in this version of the patchset
v3: for bisectability some changes moved to earlier patches
v4: no change t
.
Signed-off-by: Alan Tull
---
v2: use list_for_each_entry
static the bridge_list_lock
update copyright and author email
v3: no change to this patch in this version of patchset
v4: no change to this patch in this version of patchset
v5: fpga-bridge.h - move #ifndef before #includes
make
e use:
* fpga_mgr_lock
* fpga_mgr_unlock
The following functions no longer lock an FPGA manager's mutex:
* of_fpga_mgr_get
* fpga_mgr_get
* fpga_mgr_put
Signed-off-by: Alan Tull
---
v2: add static for __fpga_mgr_get
function documentation corrections
use dev_err
v3: bisectibility fix
v4: a
On Mon, Aug 21, 2017 at 10:16 AM, Rob Herring wrote:
Hi Rob,
> With dependencies on a statically allocated full path name converted to
> use %pOF format specifier, we can store just the basename of node, and
> the unflattening of the FDT can be simplified.
>
> This commit will affect the remaini
.
However PCIe based devices may have multiple FPGA mgr/bridge/regions
under one PCIe device. Without these changes, the PCIe solution has
to create an extra device for each child mgr/bridge/region to hold
drvdata.
Signed-off-by: Alan Tull
Reported-by: Jiuyue Ma
---
drivers/fpga/fpga-region.c| 1
, or region per platform device.
However PCIe based devices may have multiple FPGA mgr/bridge/regions
under one pcie device. Without these changes, the PCIe solution has
to create an extra device for each child mgr/bridge/region to hold
drvdata.
Signed-off-by: Alan Tull
Reported-by: Jiuyue Ma
manager, bridge, or region per platform device.
However PCIe based devices may have multiple FPGA mgr/bridge/regions
under one pcie device. Without these changes, the PCIe solution has
to create an extra device for each child mgr/bridge/region to hold
drvdata.
Signed-off-by: Alan Tull
Reported-by
r can set drvdata if desired.
Alan
Alan Tull (3):
fpga: region: don't use drvdata in common fpga code
fpga: manager: don't use drvdata in common fpga code
fpga: bridge: don't use drvdata in common fpga code
Documentation/fpga/fpga-mgr.txt | 23 ---
On Tue, Oct 31, 2017 at 3:59 PM, Moritz Fischer wrote:
> On Tue, Oct 31, 2017 at 08:42:14PM +0000, Alan Tull wrote:
>> Changes to the fpga manager code to not use drvdata in common
>> code.
>>
>> Change fpga_mgr_register to not set or use drvdata.
>>
>>
On Tue, Oct 31, 2017 at 3:42 PM, Alan Tull wrote:
> Changes to the fpga bridge code to not use drvdata in common code.
>
> Change fpga_bridge_register to not set drvdata.
>
> Change the register/unregister functions parameters to take the
> bridge struct:
> * int fpga_b
On Tue, Oct 31, 2017 at 8:34 PM, Moritz Fischer wrote:
> On Tue, Oct 31, 2017 at 04:45:54PM -0500, Alan Tull wrote:
>> On Tue, Oct 31, 2017 at 3:59 PM, Moritz Fischer wrote:
>> > On Tue, Oct 31, 2017 at 08:42:14PM +, Alan Tull wrote:
>> >> Changes to the fpga m
On Tue, Oct 31, 2017 at 9:22 PM, Alan Tull wrote:
Any further comments on v5? I'm getting ready to send v6. If I do it
today, most of these patches will have no changes (again), the only
changes will be in the patches that move drvdata out of the common
code.
I've gone to a lot of
On Tue, Oct 17, 2017 at 6:51 PM, Frank Rowand wrote:
> On 10/17/17 14:46, Rob Herring wrote:
>> On Tue, Oct 17, 2017 at 4:32 PM, Alan Tull wrote:
>>> On Mon, Aug 21, 2017 at 10:16 AM, Rob Herring wrote:
>>>
>>> Hi Rob,
>>>
>>>> W
Hi Rob,
I've noticed a problem compiling DT overlays and traced it back to
beginning in next-20171009
That tag adds the following in scripts/dtc
e9480c1 2017-10-09 16:17:32 +0100 : Mark Brown : Merge remote-tracking
branch 'devicetree/for-next'
4201d05 2017-10-03 15:03:47 -0500 : Rob Herring : s
On Wed, Oct 18, 2017 at 10:53 AM, Pantelis Antoniou
wrote:
> On Wed, 2017-10-18 at 10:44 -0500, Rob Herring wrote:
>> On Wed, Oct 18, 2017 at 10:12 AM, Alan Tull wrote:
>> > On Tue, Oct 17, 2017 at 6:51 PM, Frank Rowand
>> > wrote:
>> >> On 10/17/17 14:46
On Wed, Oct 18, 2017 at 5:34 PM, Frank Rowand wrote:
> On 10/18/17 13:16, Rob Herring wrote:
>> Use devicetree-compiler list for dtc issues please.
>>
>> On Wed, Oct 18, 2017 at 2:33 PM, Frank Rowand wrote:
>>> Hi Rob, Alan,
>>>
>>> On 10/18/17 08:
On Tue, Oct 17, 2017 at 6:36 PM, wrote:
> static int overlay_notify(struct overlay_changeset *ovcs,
> enum of_overlay_notify_action action)
> {
> @@ -86,8 +109,14 @@ static int overlay_notify(struct overlay_changeset *ovcs,
>
> ret = blocking_notifier_call_chain
ure to do that to stop their
> reference counters getting out of whack.
>
> Fixes: 0fa20cdfcc1f ("fpga: fpga-region: device tree control for FPGA")
> Cc: # 4.10+
> Signed-off-by: Ian Abbott
Signed-off-by: Alan Tull
> ---
> drivers/fpga/fpga-region.c | 13 ++--
On Thu, Oct 26, 2017 at 6:02 PM, Gustavo A. R. Silva
wrote:
Hi Gustavo,
Thanks for pointing that out. There's also a similar thing in
fpga-bridge.c that I need to fix.
Alan
> Notice that mgr = to_fpga_manager(dev); expands to:
>
> mgr = container_of(dev, struct fpga_manager, dev);
>
> and con
On Fri, Oct 27, 2017 at 2:09 PM, Gustavo A. R. Silva
wrote:
> Hi Alan,
>
> Quoting Alan Tull :
>
>> On Thu, Oct 26, 2017 at 6:02 PM, Gustavo A. R. Silva
>> wrote:
>>
>> Hi Gustavo,
>>
>> Thanks for pointing that out. There's also a
>
>> and container_of is never null, so this null check is
>> unnecessary.
>>
>> Addresses-Coverity-ID: 1397912
>> Reported-by: Alan Tull
>> Signed-off-by: Gustavo A. R. Silva
> Reviewed-by: Moritz Fischer
Signed-off-by: Alan Tull
>> -
On Thu, Jun 21, 2018 at 8:13 AM, Federico Vaga wrote:
Hi Federico,
Thanks for the analysis. I'll probably not be able to look into this
very much until next week. A few notes below.
> Hello,
>
> I believe that this patch
>
> fpga: manager: change api, don't use drvdata
> 7085e2a94f7df5f419e3c
DesignWare I2C controller was observed running at 105.93kHz rather
than the specified 100kHz. Adjust device tree settings to bring it
within spec (a slightly conservative 98 MHz).
Signed-off-by: Alan Tull
---
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
1 file changed, 2
Fischer
Acked-by: Alan Tull
> ---
> drivers/fpga/of-fpga-region.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
> index 35fabb8083fb..8c6120e30930 100644
> --- a/drivers/fpga/of-fpg
On Fri, Aug 24, 2018 at 10:26 AM Moritz Fischer wrote:
>
> Use platform_get_drvdata() in remove() function of
> the platform driver rather than dev_get_drvdata()
> to match the platform_set_drvdata in the probe().
>
> Signed-off-by: Moritz Fischer
Acked-by: Alan T
On Thu, Jun 28, 2018 at 2:50 AM, Federico Vaga wrote:
> On Wednesday, 27 June 2018 23:23:07 CEST Alan Tull wrote:
>> On Wed, Jun 27, 2018 at 4:25 AM, Federico Vaga
> wrote:
>> > Hi Alan,
>> >
>> > On Tuesday, 26 June 2018 23:00:46 CEST Alan Tull wrote
On Mon, Jul 9, 2018 at 4:39 PM, Alan Tull wrote:
On Mon, Jul 9, 2018 at 4:39 PM, Alan Tull wrote:
This patch is now outdated and would break the upstream. I currently
doubt that this change is needed or would be helpful. The discussion
on whether this patch is needed is on a separate thread
On Wed, Jul 18, 2018 at 2:25 AM, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to two spelling mistakes
> "execeeded" -> "exceeded"
> "Invaild" -> "Invalid"
>
> Signed-off-by: Colin Ian King
Acked-by: Al
On Fri, Jul 27, 2018 at 1:22 AM, Appana Durga Kedareswara rao
wrote:
Hi Appana,
There should be some documentation for the debugfs added under
Documentation/driver-api/fpga/
Also there are a lot of #ifdefs that were added due to the
CONFIG_FPGA_MGR_DEBUG_FS. This has caused a kernel robot comp
On Tue, Jul 31, 2018 at 8:08 AM, Nava kishore Manne wrote:
>
> +Alan Tull,
+ linux-fpga mailing list
Hi Nava,
Thanks for submitting.
This should be on the linux-fpga mailing list. The
linux/scripts/get_maintainer.pl script would tell you that.
Also, did you run checkpatch.pl on these?
On Wed, Aug 1, 2018 at 12:49 AM, Nava kishore Manne wrote:
> Hi Alan Tull,
>
> Thanks for the quick response.
> Please find my Comments inline...
>
>> -Original Message-----
>> From: Alan Tull [mailto:at...@kernel.org]
>> Sent: Tuesday, July 31, 2018 8:52 PM
On Tue, Jul 24, 2018 at 1:31 PM, Appana Durga Kedareswara Rao
wrote:
> Hi Moritz,
>
> Thanks for the review...
>
>
>> Can you please make the commit message such that you have full sentences?
>>
>> "Add support for readback of FPGA configuration data and registers" of
>> example.
>
> Sure
On Tue, Jul 24, 2018 at 9:17 AM, Appana Durga Kedareswara rao
wrote:
Hi Appana,
Another minor thing.
> +
> +//
Let's keep the coding style consistent by not having
'***'
> +/**
> + *
Also, you
On Wed, Jul 25, 2018 at 4:12 AM, Appana Durga Kedareswara Rao
wrote:
> Hi Alan,
>
> Thanks for the review...
>
>
>> >
>> >
>> >> > +static bool readback_type;
>> >> > +module_param(readback_type, bool, 0644);
>> >> > +MODULE_PARM_DESC(readback_type,
>> >> > + "readback_type
On Wed, Jul 11, 2018 at 10:59 AM, Alan Tull wrote:
> On Wed, Jul 11, 2018 at 7:38 AM, Federico Vaga wrote:
>
> Hi Federico,
>
>> Hi Alan,
>>
>> I have another point that I would like to discuss. It is about the
>> usage of 'fpga_mgr_free()' w
Clarify when fpga_(mgr|bridge|region)_free functions should be used.
The class's dev_release will handle cleanup when the device is released
so once the mgr/brige/region has been successfully registered, it
would be a bug to call fpga_(mgr|bridge|region)_free.
Signed-off-by: Alan Tull
Sugg
The FPGA region class's dev_release handles freeing the struct
fpga_region when fpga_region_unregister() unregisters the device. A
couple drivers were accessing the region struct after it had been
freed. Save off the pointer to the mgr before the region struct gets
freed.
Signed-off-by:
On Wed, Jul 11, 2018 at 7:38 AM, Federico Vaga wrote:
Hi Federico,
> Hi Alan,
>
> I have another point that I would like to discuss. It is about the
> usage of 'fpga_mgr_free()' which does not look like consistent.
>
> This function, according to the current implementation, can be used by
> an F
On Mon, Jul 9, 2018 at 4:39 PM, Alan Tull wrote:
> Change fpga_mgr_get() function to take manager as the parameter
> instead of dev.
Todo: if this approach seems good, I'm going to do the same thing in
fpga-bridge.c for fpga_bridge_get, taking the bridge struct as a
parameter instea
Add a comment to the header of fpga_region_program_fpga()
regarding locking of the bridges.
Signed-off-by: Alan Tull
---
drivers/fpga/fpga-region.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
index edab2a2..cb0603e 100644
On Thu, Jan 25, 2018 at 1:09 PM, Moritz Fischer wrote:
> Hi Alan,
>
> looks good.
>
Thanks, Moritz!
> On Thu, Jan 25, 2018 at 09:39:22AM -0600, Alan Tull wrote:
>> Add a comment to the header of fpga_region_program_fpga()
>> regarding locking of the bridges.
>
On Mon, Jan 29, 2018 at 6:35 PM, Frank Rowand wrote:
Hi Frank,
> Hi Alan,
>
> In this patch series one of the changes was to change some
> devicetree unittest overlay source to use the new sugar syntax to
> specify overlay nodes instead of hand coding the fragment nodes.
>
> One reviewer reminde
> Signed-off-by: Xiao Guangrong
> Signed-off-by: Wu Hao
Acked-by: Alan Tull
ed-off-by: Enno Luebbers
> Signed-off-by: Shiva Rao
> Signed-off-by: Christopher Rauer
> Signed-off-by: Wu Hao
Acked-by: Alan Tull
> diff --git a/drivers/fpga/fpga-dfl-fme-br.c b/drivers/fpga/fpga-dfl-fme-br.c
> new file mode 100644
> index 000..db2603b
> --- /dev/nu
Enno Luebbers
> Signed-off-by: Shiva Rao
> Signed-off-by: Christopher Rauer
> Signed-off-by: Xiao Guangrong
> Signed-off-by: Wu Hao
Acked-by: Alan Tull
> diff --git a/include/uapi/linux/fpga-dfl.h b/include/uapi/linux/fpga-dfl.h
> new file mode 100644
> index 000..b46d
On Mon, Dec 4, 2017 at 9:36 PM, Wu Hao wrote:
> On Mon, Dec 04, 2017 at 02:26:14PM -0600, Alan Tull wrote:
>> On Wed, Nov 29, 2017 at 12:11 AM, Moritz Fischer wrote:
>> > Hi Hao,
>> >
>> > On Mon, Nov 27, 2017 at 02:42:09PM +0800, Wu Hao wrote:
>> >&
; Signed-off-by: Enno Luebbers
> Signed-off-by: Shiva Rao
> Signed-off-by: Christopher Rauer
> Signed-off-by: Wu Hao
Acked-by: Alan Tull
> diff --git a/drivers/fpga/fpga-dfl-fme-region.c
> b/drivers/fpga/fpga-dfl-fme-region.c
> new file mode 100644
> index 000..0b9
On Fri, Dec 22, 2017 at 2:45 AM, Wu Hao wrote:
>> > >
>> > > I see that the port code is included as part of the enumeration code.
>> > > This is not very future-proofed, if a different port needs to be
>> > > supported.
>> > >
>> > > The port is a FPGA fabric based bridge with expanded functiona
On Tue, Dec 5, 2017 at 11:30 PM, Wu Hao wrote:
> On Tue, Dec 05, 2017 at 11:00:22AM -0600, Alan Tull wrote:
>> On Mon, Dec 4, 2017 at 9:33 PM, Wu Hao wrote:
>> > On Mon, Dec 04, 2017 at 01:46:59PM -0600, Alan Tull wrote:
>> >> On Mon, Nov 27, 2017 at 9:15 PM, Wu H
On Mon, Nov 27, 2017 at 12:42 AM, Wu Hao wrote:
Hi Hao,
A few comments below. Besides that, looks good.
> This patch adds fpga manager driver for FPGA Management Engine (FME). It
> implements fpga_manager_ops for FPGA Partial Reconfiguration function.
>
> Signed-off-by: Tim Whisonant
> Signe
On Sun, Mar 11, 2018 at 11:29 PM, Wu Hao wrote:
> On Sun, Mar 11, 2018 at 01:09:31PM -0700, matthew.gerl...@linux.intel.com
> wrote:
>>
>> Hi Hao,
>>
>> I do think we should consider different hw implementations with this code
>> because it does look like most of it is generic. Specifically, I
On Thu, Mar 1, 2018 at 12:17 AM, Wu Hao wrote:
> On Wed, Feb 28, 2018 at 04:55:15PM -0600, Alan Tull wrote:
>> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
>>
>> Hi Hao,
>
> Hi Alan,
>
> Thanks for the review.
>
>>
>> > This patch introdu
ers
> Signed-off-by: Shiva Rao
> Signed-off-by: Christopher Rauer
> Signed-off-by: Kang Luwei
> Signed-off-by: Xiao Guangrong
> Signed-off-by: Wu Hao
> ---
> v2: moved the code to drivers/fpga folder as suggested by Alan Tull.
> switched to GPLv2 license.
> re
On Mon, Mar 5, 2018 at 8:08 PM, Wu Hao wrote:
> On Mon, Mar 05, 2018 at 04:46:02PM -0600, Alan Tull wrote:
>> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
>>
>> Hi Hao,
>
> Hi Alan,
>
> Thanks for the comments.
>
>>
>> We are going to want
On Wed, Mar 7, 2018 at 1:47 PM, Rob Herring wrote:
> On Thu, Mar 01, 2018 at 06:19:32PM -0600, richard.g...@linux.intel.com wrote:
>> From: Alan Tull
>>
>> Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager.
>>
>> Signed-off-by: Alan Tull
>
On Thu, Mar 22, 2018 at 11:33 PM, Wu Hao wrote:
>> > +
>> > +/*
>> > + * This function resets the FPGA Port and its accelerator (AFU) by
>> > function
>> > + * __fpga_port_disable and __fpga_port_enable (set port soft reset bit and
>> > + * then clear it). Userspace can do Port reset at any time
Replace GPLv2 boilerplate with SPDX in FPGA code that came from me or
from Altera.
Signed-off-by: Alan Tull
---
drivers/fpga/altera-fpga2sdram.c | 13 +
drivers/fpga/altera-freeze-bridge.c| 13 +
drivers/fpga/altera-hps2fpga.c | 13
From: Paolo Pisati
This patch adds support to the FPGA manager for programming
MachXO2 device’s internal flash memory, via slave SPI.
Signed-off-by: Paolo Pisati
[at...@kernel.org: use existing FPGA mgr API]
Signed-off-by: Alan Tull
---
drivers/fpga/Kconfig | 7 +
drivers/fpga
From: Paolo Pisati
Add dt binding documentation details for Lattice MachXO2 FPGA configuration
over Slave SPI interface.
Signed-off-by: Paolo Pisati
Acked-by: Rob Herring
Acked-by: Moritz Fischer
Acked-by: Alan Tull
---
.../bindings/fpga/lattice-machxo2-spi.txt | 29
This is Paolo's v10 with a minor fixup. I had asked him to rebase his
patch on a branch with a new FPGA manager API. That API change ended
up not going upstream, so I've fixed it for the current API. This patch
applies cleanly on the current linux-next.
Paolo Pisati (2):
dt: bindings: fpga: a
);
Update the drivers that call fpga_mgr_register with the new API.
Signed-off-by: Alan Tull
Reported-by: Jiuyue Ma
---
v2: change fpga_mgr_register to not need parent device param
v3: minor changes to make diffs smaller and more obviously correct
rebased to current next branch
v4: reworked
fpga_bridge *br);
Update the drivers that call fpga_bridge_register with the new API.
Signed-off-by: Alan Tull
Reported-by: Jiuyue Ma
---
v2: change fpga_bridge_register to not need parent device param
fix undeclared - s/dev/&pdev->dev/
v3: minor changes to make diffs smaller and more ob
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