On Thu, Oct 31, 2013 at 04:46:21PM -0500, Andy Gross wrote:
On Thu, Oct 31, 2013 at 10:29:48PM +0530, Vinod Koul wrote:
On Fri, Oct 25, 2013 at 03:24:02PM -0500, Andy Gross wrote:
This should be sent to dmaeng...@vger.kernel.org
I'll add the list when I send the second iteration
On Wed, Nov 13, 2013 at 06:48:12PM +0530, Vinod Koul wrote:
On Thu, Nov 07, 2013 at 05:03:17PM -0600, Andy Gross wrote:
On Thu, Oct 31, 2013 at 04:46:21PM -0500, Andy Gross wrote:
On Thu, Oct 31, 2013 at 10:29:48PM +0530, Vinod Koul wrote:
On Fri, Oct 25, 2013 at 03:24:02PM -0500, Andy
On Mon, Feb 24, 2014 at 01:03:32PM -0600, Joel Fernandes wrote:
Hi folks,
Just wanted your thoughts/suggestions on how we can avoid overhead in the EDMA
dmaengine driver. I am seeing a lots of performance drop specially for small
transfers with EDMA versus before raw EDMA was moved to
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add device tree binding
dmaengine: add Qualcomm BAM dma driver
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
On Tue, Feb 25, 2014 at 08:07:13AM -0800, Bjorn Andersson wrote:
[snip]
The v2 model will get BAM (DMAEngine) support soon, v1 uses an
older DMA core. So there's a difference. I'm not aware what differences
there are between 2.1.1 and 2.2.1.
Difference between 2.1.1 and 2.2.1:
- high speed
On Wed, Feb 26, 2014 at 06:51:55PM +0200, Stanimir Varbanov wrote:
+ /* read revision and configuration information */
+ val = readl_relaxed(bdev-regs + BAM_REVISION) NUM_EES_MASK;
+
The ees shit is not zero and you got wrong ee. Could you add the line
below or something similar:
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
in favor of standard types.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add device tree binding
dmaengine: add Qualcomm BAM dma driver
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41 +
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
On Sat, Mar 08, 2014 at 12:29:49AM +0200, Stanimir Vabanov wrote:
+#define BAM_IRQ_SRCS_EE(pipe) (0x0800 + ((pipe) * 0x80))
+#define BAM_IRQ_SRCS_MSK_EE(pipe) (0x0804 + ((pipe) * 0x80))
s/pipe/ee ?
Ah good catch. I'll fix that.
+struct bam_chan {
+ struct
On Mon, Mar 03, 2014 at 09:38:03AM +, Shevchenko, Andriy wrote:
snip
+ if (IS_ERR(bdev-bamclk))
+ return PTR_ERR(bdev-bamclk);
+
+ ret = clk_prepare_enable(bdev-bamclk);
+ if (ret) {
+ dev_err(bdev-dev, failed to prepare/enable clock\n);
+
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41
1 file changed, 41 insertions(+)
create mode 100644
.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add device tree binding
dmaengine: add Qualcomm BAM
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala ga...@codeaurora.org
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48
1 file changed, 48 insertions(+)
create mode 100644
and returns residuals
- Removed proprietary slave config. Removed associated include file.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy
On Fri, Feb 21, 2014 at 09:26:57AM +, Mark Rutland wrote:
On Fri, Feb 21, 2014 at 06:43:04AM +, Andy Gross wrote:
Add device tree binding support for the QCOM BAM DMA driver.
[snip]
+Required properties:
+- compatible: Must be qcom,bam-v1.4.0 for MSM8974 V1
On Fri, Feb 21, 2014 at 09:33:52AM +, Mark Rutland wrote:
On Fri, Feb 21, 2014 at 06:43:05AM +, Andy Gross wrote:
[snip]
+ bdev-bamclk = devm_clk_get(bdev-dev, bam_clk);
The binding document should describe the bam_clk string in the
clock-names description.
OK
On Fri, Feb 21, 2014 at 05:36:47PM +, Mark Rutland wrote:
[snip]
Yes only a single interrupt. I can remove the s.
Please don't, the interrupts proeprty is standard and shouldn't change.
I was only asking to ensure that all interrupts were described in the
binding, which they are.
On Mon, Feb 10, 2014 at 06:55:02PM +0200, Ivan T. Ivanov wrote:
[]
Bail here?
I don't know. What will be the consequences if controller continue to
operate on its default rate?
It is unclear. But if you can't set the rate that is configured or if
there is
a
On Tue, Feb 11, 2014 at 11:00:48PM +0530, Vinod Koul wrote:
On Tue, Feb 04, 2014 at 02:42:35PM -0600, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA
controller
found in the MSM 8x74 platforms.
[.]
+ * QCOM BAM DMA engine driver
supports FIFO mode (for low bandwidth applications) and block mode (interrupt
generated for each block-size data transfer).
snip
Looks good.
Reviewed-by: Andy Gross agr...@codeaurora.org
--
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc
On Tue, Oct 29, 2013 at 10:56:03AM -0700, Stephen Boyd wrote:
On 10/25, Andy Gross wrote:
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f238cfd..a71b415 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -364,4 +364,13 @@ config DMATEST
Simple DMA test
On Thu, Oct 31, 2013 at 10:29:48PM +0530, Vinod Koul wrote:
On Fri, Oct 25, 2013 at 03:24:02PM -0500, Andy Gross wrote:
This should be sent to dmaeng...@vger.kernel.org
I'll add the list when I send the second iteration or should I send it over mid
stream?
Add the DMA engine driver
will only support slave DMA operations
between system memory and peripherals.
Andy Gross (2):
dmaengine: add msm bam dma driver
dmaengine: msm_bam_dma: Add device tree binding
.../devicetree/bindings/dma/msm_bam_dma.txt| 49 ++
drivers/dma/Kconfig
the peripheral and system memory (System mode) or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree probe support for the MSM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/msm_bam_dma.txt| 49
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/msm_bam_dma.txt
On Fri, May 09, 2014 at 10:37:00AM +0200, Linus Walleij wrote:
On Fri, May 2, 2014 at 6:44 AM, Andy Gross agr...@codeaurora.org wrote:
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm,
gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted
pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
On Fri, May 09, 2014 at 01:08:25PM -0500, Kumar Gala wrote:
Drop underscore in spdif_groups to match all other groups.
Signed-off-by: Kumar Gala ga...@codeaurora.org
Reviewed-by: Andy Gross agr...@codeaurora.org
snip
--
sent by an employee of the Qualcomm Innovation Center, Inc
On Mon, May 19, 2014 at 11:07:38AM +0300, Ivan T. Ivanov wrote:
snip
+- num-cs: total number of chipselects
My understanding is that num-cs have to be parsed by
master driver, not by core SPI driver.
Right. I need to parse it and check vs the max cs and use that value to set the
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/spi/qcom,spi-qup.txt |6 +++-
drivers/spi/spi-qup.c | 36
2 files changed, 27 insertions(+), 15
This patch removes the chip select function. Chip select should instead be
supported using GPIOs, defining the DT entry cs-gpios, and letting the SPI
core assert/deassert the chip select as it sees fit.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/spi/qcom,spi
, IPQ8064, and MSM8960).
Andy Gross (3):
spi: qup: Remove chip select function
spi: qup: Fix order of spi_register_master
spi: qup: Add support for v1.1.1
.../devicetree/bindings/spi/qcom,spi-qup.txt | 12 ++-
drivers/spi/spi-qup.c | 80
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm. If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.
Signed-off-by: Andy Gross agr...@codeaurora.org
Acked-by: Ivan T. Ivanov iiva...@mm-sol.com
On Thu, May 22, 2014 at 11:40:49AM +0530, Vinod Koul wrote:
snip
I have 3 different IRQs that can be asserted based on the bit I set in the
hardware descriptor. The normal IRQ is the INT bit. However, in some
cases the
peripheral protocol requires the use of the EOT or EOB
On Thu, May 22, 2014 at 04:27:05PM +0100, Srinivas Kandagatla wrote:
snip
The EOT is not used for every transaction. It is part of a handshaking
protocol with the attached peripheral, much like the NWD (notify when done).
As
near as I can tell today, no peripheral depends on the EOB, so
On Fri, May 02, 2014 at 01:08:27PM -0500, Andy Gross wrote:
On Fri, May 02, 2014 at 09:58:41PM +0530, Vinod Koul wrote:
On Thu, Apr 17, 2014 at 05:04:02PM -0500, Andy Gross wrote:
This patch adds APIs that allow for BAM hardware flags to be set per
descriptor. Each one of the new flags
DMA_PREP_FENCE to enable this flag.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/qcom_bam_dma.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index e01c2d106..4635224 100644
--- a/drivers
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk, pdm, gcc clk, cci_timer,
cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings
to be called after the runtime
pm is initialized.
The last patch adds support for V1.1.1 of the QUP. This version of the
controller is present in earlier devices (APQ8064, IPQ8064, and MSM8960).
Andy Gross (4):
spi: qup: Remove chip select function
spi: qup: Correct selection of FIFO/Block mode
This patch removes the chip select function. Chip select should instead be
supported using GPIOs, defining the DT entry cs-gpios, and letting the SPI
core assert/deassert the chip select as it sees fit.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/spi/qcom,spi
This patch fixes the calculation for determining whether to use FIFO or BLOCK
mode.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index ea7017b
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm. If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c | 11 +++
1
On Tue, May 13, 2014 at 03:08:45PM -0700, Stephen Boyd wrote:
On 05/13, Andy Gross wrote:
@@ -488,7 +491,7 @@ static int spi_qup_probe(struct platform_device *pdev)
struct resource *res;
struct device *dev;
void __iomem *base;
- u32 data, max_freq, iomode;
+ u32 data
On Tue, Jun 10, 2014 at 11:25:23AM -0700, Bjorn Andersson wrote:
In general, it all looks good. I only have 2 areas of concern. The first is a
nit and it has to do with alternate pins for functions. There really isn't a
need for a separate function name. That would only be required if the
This patch adds the BUS_HOLD (Keeper) bias option for pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/pinctrl/pinctrl-msm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
index e43fbce..9aa2839 100644
On Fri, Jan 24, 2014 at 02:24:27PM +0100, Lars-Peter Clausen wrote:
On 01/24/2014 12:16 PM, Srikanth Thokala wrote:
Hi Lars,
On Thu, Jan 23, 2014 at 4:55 PM, Lars-Peter Clausen l...@metafoo.de wrote:
On 01/22/2014 05:52 PM, Srikanth Thokala wrote:
[...]
+/**
+ *
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma
.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: add Qualcomm BAM dma driver
dmaengine: qcom_bam_dma: Add device tree binding
On Tue, Feb 04, 2014 at 12:58:25PM +0100, Lars-Peter Clausen wrote:
On 02/04/2014 12:04 AM, Andy Gross wrote:
[...]
+static int bam_dma_remove(struct platform_device *pdev)
+{
+struct bam_device *bdev = platform_get_drvdata(pdev);
+u32 i;
+
+dma_async_device_unregister(bdev
of standard types.
Andy Gross (2):
dmaengine: add Qualcomm BAM dma driver
dmaengine: qcom_bam_dma: Add device tree binding
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48 +
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 52
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma
file.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: add Qualcomm BAM dma driver
dmaengine: qcom_bam_dma: Add
the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig|9 +
drivers/dma/Makefile
On Tue, Jan 28, 2014 at 10:05:35AM +0100, Lars-Peter Clausen wrote:
On 01/28/2014 07:27 AM, Andy Gross wrote:
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 52
On Tue, Jan 28, 2014 at 10:16:53AM +0100, Arnd Bergmann wrote:
On Tuesday 28 January 2014 10:05:35 Lars-Peter Clausen wrote:
+
+Clients must use the format described in the dma.txt file, using a three
cell
+specifier for each channel.
+
+The three cells in order are:
+ 1. A
On Tue, Jan 28, 2014 at 10:16:53AM +0100, Arnd Bergmann wrote:
On Tuesday 28 January 2014 10:05:35 Lars-Peter Clausen wrote:
+
+Clients must use the format described in the dma.txt file, using a three
cell
+specifier for each channel.
+
+The three cells in order are:
+ 1. A
This patch adds pin definitiones for the MSM8x74 TLMM. New definitions
include:
BLSP devices (I2C, UART, UART flow control, SPI, and UIM), mi2s, gp clk, pdm,
gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif, sdc3, sdc4, and other assorted
pins.
Signed-off-by: Andy Gross agr...@codeaurora.org
On Fri, May 02, 2014 at 09:58:41PM +0530, Vinod Koul wrote:
On Thu, Apr 17, 2014 at 05:04:02PM -0500, Andy Gross wrote:
This patch adds APIs that allow for BAM hardware flags to be set per
descriptor. Each one of the new flags informs the attached peripheral of a
special behavior
This patch corrects the error check on the call to pm_runtime_get_sync.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/i2c/busses/i2c-qup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 1b4cf14
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross agr
Add device tree binding support for the QCOM GSBI driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78
include/dt-bindings/soc/qcom,gsbi.h| 26 +++
2 files changed, 104 insertions
Add placeholder Kconfig and linkage for driver/soc.
The first patch set that implemented this was authored by Santosh Shilimkar:
https://lkml.org/lkml/2014/2/28/567
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/Kconfig |2 ++
drivers/Makefile|4
drivers/soc
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/tty/serial/msm_serial.c | 48 ++-
drivers/tty/serial/msm_serial.h |5
mode setting for the ports and keep the children
from accessing the GSBI directly.
Changes from v1:
- Add dt-bindings file containing definitions for MUX values
- Fix code comments
- Removed unnecessary code
Andy Gross (4):
soc: Placeholder files for drivers/soc
soc: qcom
Fix copy/paste error in pinctrl_pin_desc for pin 0.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/pinctrl/pinctrl-ipq8064.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-ipq8064.c
b/drivers/pinctrl/pinctrl-ipq8064.c
index 1700b49
On Fri, Apr 18, 2014 at 02:01:19AM +0300, Stanimir Vabanov wrote:
snip
static const struct of_device_id bam_of_match[] = {
+ { .compatible = qcom,bam-v1.3.0, },
{ .compatible = qcom,bam-v1.4.0, },
you could use the of_device_id::data field to switch between different
mode setting for the ports and keep the children
from accessing the GSBI directly.
Andy Gross (4):
soc: Placeholder files for drivers/soc
soc: qcom: Add GSBI driver
soc: qcom: Add device tree binding for GSBI
tty: serial: msm: Remove direct access to GSBI
.../devicetree/bindings/soc/qcom
Add placeholder Kconfig and linkage for driver/soc.
The first patch set that implemented this was authored by Santosh Shilimkar:
https://lkml.org/lkml/2014/2/28/567
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/Kconfig |2 ++
drivers/Makefile|4
drivers/soc
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross agr
Add device tree binding support for the QCOM GSBI driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/tty/serial/msm_serial.c | 48 ++-
drivers/tty/serial/msm_serial.h |5
On Mon, Apr 21, 2014 at 09:48:16AM -0400, Christopher Covington wrote:
snip
In that thread, Olof wrote, The code [going into drivers/soc] isn't the pure
drivers. Those we find homes for.
Right. I see this as glue for the most part. You could argue it's a small
pinctrl, but this doesn't
On Mon, Apr 21, 2014 at 11:54:00AM -0500, Josh Cartwright wrote:
snip
+
+struct gsbi_dev {
+ struct device *dev;
+ void __iomem*base;
You don't really need these.
Old habits die hard. I'll remove.
snip
+ if (of_property_read_u32(node, qcom,mode, mode)) {
+
Add missing PINCTRL selection. This enables selection of pinctrollers for
Qualcomm processors.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
arch/arm/mach-qcom/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index
ARCH_QCOM
platforms. This allows for selection of pinctrl support via a make menuconfig.
Andy Gross (3):
pinctrl: qcom: Add definitions for IPQ8064
dt: Document Qualcomm IPQ8064 pinctrl binding
ARM: qcom: Select PINCTRL by default for ARCH_QCOM
.../bindings/pinctrl/qcom,ipq8064
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm IPQ8064 platform.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/pinctrl/Kconfig |8 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-ipq8064.c | 653
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the
IPQ8064.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../bindings/pinctrl/qcom,ipq8064-pinctrl.txt | 95
1 file changed, 95 insertions(+)
create mode 100644
Documentation/devicetree
Add the device tree binding support for the v1.3.0 version of the QCOM BAM DMA
driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree
different offsets and multipliers that are
specific to that version of the IP block.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add v1.3.0 driver support
dmaengine: qcom_bam_dma: Add binding for v1.3.0
.../devicetree/bindings/dma/qcom_bam_dma.txt |4 +-
drivers/dma/qcom_bam_dma.c
registers changed
as well.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/qcom_bam_dma.c | 177
1 file changed, 114 insertions(+), 63 deletions(-)
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index 82c9231..02f7fef
that the descriptor payload contains
command descriptors and not data descriptors.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/qcom_bam_dma.c | 48 --
include/linux/dma/qcom_bam_dma.h | 23 ++
2 files changed, 69 insertions(+), 2
for transactions to/from peripheral devices.
The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/dma/Kconfig| 10 +
drivers/dma/Makefile
(client rate
control interface) is supported and can be configured via device tree
configuration. Flow control usage is required for some peripheral devices.
Andy Gross (2):
dmaengine: Add QCOM ADM DMA driver
dmaengine: qcom_adm: Add device tree binding
Documentation/devicetree/bindings/dma
Add device tree binding support for the QCOM ADM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
Documentation/devicetree/bindings/dma/qcom_adm.txt | 60
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
On Sat, Jun 21, 2014 at 11:13:03AM +0100, Mark Brown wrote:
On Thu, Jun 12, 2014 at 02:34:10PM -0500, Andy Gross wrote:
This patch removes the chip select function. Chip select should instead be
supported using GPIOs, defining the DT entry cs-gpios, and letting the SPI
core assert/deassert
This patch adds DMA capabilities to the spi-qup driver. If DMA channels are
present, the QUP will use DMA instead of block mode for transfers to/from SPI
peripherals for transactions larger than the length of a block.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings
On Fri, Jun 27, 2014 at 11:50:57AM +0100, Mark Brown wrote:
On Thu, Jun 26, 2014 at 04:06:21PM -0500, Andy Gross wrote:
+ if (xfer-rx_buf) {
+ rx_dma = dma_map_single(controller-dev, xfer-rx_buf,
+ xfer-len, DMA_FROM_DEVICE);
It would be better to use
On Fri, Jun 27, 2014 at 05:24:11PM +0100, Russell King - ARM Linux wrote:
snip
It would be better to use the core DMA mapping code rather than open
coding. This code won't work for vmalloc()ed addresses, or physically
non-contiguous addresses unless there's an IOMMU fixing things up.
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Andy
-by: Andy Gross agr...@codeaurora.org
---
drivers/usb/phy/Kconfig | 11 ++
drivers/usb/phy/Makefile |2 +
drivers/usb/phy/phy-qcom-hsusb.c | 348 ++
drivers/usb/phy/phy-qcom-ssusb.c | 385 ++
4 files changed
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