loni
Acked-by: Boris Brezillon
> ---
> Daniel,
>
> I think this should go through the at91 tree as the patch introducing that
> issue
> went there.
>
> drivers/clocksource/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clocksour
hanges (in all clock drivers and in the
core infrastructure), but I really think we should not mix error codes
and clock frequencies (even if we decide to move to a 64 bits rate
approach).
Anyway, IMHO the only alternative to this solution is solution #3,
because #1 implies re-introducing another bug
Hi Mike,
On Sun, 12 Apr 2015 21:37:25 -0700
Michael Turquette wrote:
> Quoting Boris Brezillon (2015-03-28 18:53:43)
> > The PLL impose a certain input range to work correctly, but it appears that
> > this input range does not apply on the input clock (or parent clock) but
&
Hi Mike,
Oops, it seems I should have answered to this email before answering to
the previous one :-(.
On Sun, 12 Apr 2015 16:50:21 -0700
Michael Turquette wrote:
> Quoting Boris Brezillon (2015-03-26 16:40:54)
> > Hello,
> >
> > I recently had a problem with the at91 cl
On Mon, 13 Apr 2015 14:56:12 +0200
Gaël PORTAY wrote:
> Hi,
>
> Here are two patches to bring support for a new hardware based on SAM9G25 SoC.
>
> The first one adds the PIN controller definition for PWM0.
> The second defines the new board.
To the whole series,
Acked-b
> Signed-off-by: Gaël PORTAY
Acked-by: Boris Brezillon
> ---
> arch/arm/boot/dts/at91-sama5d3_xplained.dts | 6 --
> arch/arm/boot/dts/at91sam9rlek.dts | 6 --
> arch/arm/boot/dts/sama5d3xcm.dtsi | 6 --
> 3 files changed, 18 deletions(-)
>
&
ype to return 0 or an error code, and pass
the requested rate as a pointer so that it can be adjusted depending on
hardware capabilities.
Signed-off-by: Boris Brezillon
---
CC: Jonathan Corbet
CC: Tony Lindgren
CC: Ralf Baechle
CC: "Emilio López"
CC: Maxime Ripard
CC: Tero K
return 0 or an error code, and pass the
requested rate as a pointer so that it can be adjusted depending on
hardware capabilities.
Signed-off-by: Boris Brezillon
---
CC: Jonathan Corbet
CC: Shawn Guo
CC: ascha Hauer
CC: David Brown
CC: Daniel Walker
CC: Bryan Huntsman
CC: Tony Lindgren
CC
DRIVER depends
on !NEW_DRIVER).
I don't know how to make it a runtime check without adding new
compatible strings for the kirkwood, dove and orion platforms, and I'm
sure sure this is a good idea.
Do you have any ideas ?
Regards,
Boris
--
Boris Brezillon, Free Electrons
Embedde
On Fri, 17 Apr 2015 10:33:56 +0200
Boris Brezillon wrote:
> Hi Jason,
>
> On Mon, 13 Apr 2015 20:11:46 +
> Jason Cooper wrote:
>
> > >
> > > > I'd appreciate if we'd look into it. I understand from on-list and
> > > > off-list di
On Mon, 27 Apr 2015 21:52:38 +0900
Krzysztof Kozlowski wrote:
> The irq_domain_ops are not modified by the driver and the irqdomain core
> code accepts pointer to a const data.
>
> Signed-off-by: Krzysztof Kozlowski
Acked-by: Boris Brezillon
> ---
> drivers/clk/at91/pmc.
main: mainck {
> + clock-frequency = <1200>;
The main clock driver has been reworked in 3.16, and this
clock-frequency property is no longer needed (this value is taken
from the main_xtal definition).
Apart from that this patch looks
{
> + model = "Overkiz Kizbox 2";
> + compatible = "overkiz,kizbox2", "atmel,sama5d31ek", "atmel,sama5d31",
> "atmel,sama5d3", "atmel,sama5";
Oh, and as Alexandre noticed in your other patch series, you should
just define:
intensive crypto usage
> > - new algorithms: SHA256, DES and 3DES
> >
> [...]
> > Boris Brezillon (2):
> >crypto: add new driver for Marvell CESA
> >crypto: marvell/CESA: update DT bindings documentation
>
> IMHO, the patch set should be split u
driver adds support for:
- new armada SoCs (up to 38x) while keeping support for older ones (Orion
and Kirkwood)
- DMA mode to offload the CPU in case of intensive crypto usage
- new algorithms: SHA256, DES and 3DES
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers
Document new compatible strings, document the new method to reference the
crypto SRAM and deprecate the old one and document the the 'clocks' and
'clock-names' properties.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/mv_cesa.txt | 50 ++
On Tue, 21 Apr 2015 14:05:11 +0200
Gaël PORTAY wrote:
> *** BLURB HERE ***
We usually replace this line by a description ;-).
Anyway, to the whole series:
Acked-by: Boris Brezillon
>
> Gaël PORTAY (7):
> ARM: at91/dt: kizbox: rename to at91-kizbox
> ARM: at91/dt: at91-k
o be
scheduled. ITOH, the tasklet approach provide slightly performances (I
don't recall the exact numbers, but Arnaud did some tests).
On Thu, 9 Apr 2015 16:58:41 +0200
Boris Brezillon wrote:
> Hello,
>
> This is an attempt to replace the mv_cesa driver by a new one to address
&g
r provided mode is preferred
over the simple panel ones, which might result in unpredictable behavior.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/panel/panel-simple.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/p
drm_display_mode_from_videomode() is already calling drm_mode_set_name() on
the provided mode.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/panel/panel-simple.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
linux-me...@vger.kernel.org
CC: rtc-li...@googlegroups.com
Boris Brezillon (2):
clk: change clk_ops' ->round_rate() prototype
clk: change clk_ops' ->determine_rate() prototype
Documentation/clk.txt| 8 +--
arch/arm/mach-imx/clk-busy.c
return 0 or an error code, and pass the
requested rate as a pointer so that it can be adjusted depending on
hardware capabilities.
Signed-off-by: Boris Brezillon
Tested-by: Heiko Stuebner
Tested-by: Mikko Perttunen
Reviewed-by: Heiko Stuebner
---
CC: Jonathan Corbet
CC: Shawn Guo
CC: ascha Hau
ype to return 0 or an error code, and pass
the requested rate as a pointer so that it can be adjusted depending on
hardware capabilities.
Signed-off-by: Boris Brezillon
Tested-by: Mikko Perttunen
---
CC: Jonathan Corbet
CC: Tony Lindgren
CC: Ralf Baechle
CC: "Emilio L??pez"
CC: M
Hi Gregory,
On Fri, 17 Apr 2015 15:01:01 +0200
Gregory CLEMENT wrote:
> Hi Boris,
>
> On 17/04/2015 10:39, Boris Brezillon wrote:
> > On Fri, 17 Apr 2015 10:33:56 +0200
> > Boris Brezillon wrote:
> >
> >> Hi Jason,
> >>
> >> On Mo
Hi Heiko,
On Sun, 19 Apr 2015 14:13:04 +0200
Heiko Stübner wrote:
> Hi Boris,
>
> Am Freitag, 17. April 2015, 09:29:28 schrieb Boris Brezillon:
> > Clock rates are stored in an unsigned long field, but ->round_rate()
> > (which returns a rounded rate from a reque
s file
- use stdout-path
- sanitize bootargs
- led related changes (rename + pwm-leds)
- gpio-key related changes (rename + fix level)
Best Regards,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
--
To unsubscribe from this list: send the
On Tue, 21 Apr 2015 12:03:58 +0200
Gaël PORTAY wrote:
> On 21/04/2015 09:11, Boris Brezillon wrote:
> > Hi Gael,
> >
> > On Mon, 20 Apr 2015 11:13:38 +0200
> > Gaël PORTAY wrote:
> >
> >> Sort nodes, rename to match Atmel naming convention
> >
several crypto algorithms, provided support for armada-370 and tested
the driver on different platforms, hence the SoB and dual MODULE_AUTHOR
in the driver code.
Best Regards,
Boris
Boris Brezillon (2):
crypto: add new driver for Marvell CESA
crypto: marvell/CESA: update DT bindings docum
wl_lock);
> +
> + err = 0;
> + }
Nitpick, but checkpatch complains about 'else' or 'else if' statements
that are not on the '}' line.
> + }
> + else {
> + /*
> + * Ignore read errors as
se = true;
} else if (ubi->move_to == e || ubi->move_from == e) {
ensure_wl = true;
} else {
ubi_schedule_fm_work(ubi);
}
if (scrub)
wl_tree_add(e, &ubi->scr
>> + }
> >
> > I'm nitpicking again, but I like to have a single place where spinlocks
> > are locked and unlocked, so here is a rework suggestion for the code
> > inside the 'if (err == UBI_IO_BITFLIPS)' statement:
>
> A single lock/unloc
On Sun, 12 Apr 2015 18:09:23 +0200
Richard Weinberger wrote:
> Am 12.04.2015 um 16:12 schrieb Boris Brezillon:
> > Hi Richard,
> >
> > Sorry for the late reply.
> >
> > On Sun, 29 Mar 2015 14:13:17 +0200
> > Richard Weinberger wrote:
> >
>
t_work);
> + schedule_bitrot_check(ubi, e);
> + }
> + }
Do we really need to create a ubi_work per PEB ?
Couldn't we create a single work being rescheduled inside the worker
function (after updating the ubi_wl_entry of course).
I'm pretty sure I
On Sun, 12 Apr 2015 19:09:11 +0200
Richard Weinberger wrote:
> Am 12.04.2015 um 19:01 schrieb Boris Brezillon:
> > Hi Richard,
> >
> > After the 'coding style related'/'useless' comments, now comes a real
> > question related to the approach you&#
sts into? mtd-utils?
I guess so, but I'll let Brian answer that one.
How about dispatching them in mtd-utils' tests/ directory (some of them
are NAND related tests, so creating a tests/nand would make sense,
and others are more generic).
Best Regards,
Boris
--
Boris Brezillon, Free Electr
On Sun, 12 Apr 2015 21:53:12 +0200
Richard Weinberger wrote:
> Am 12.04.2015 um 21:20 schrieb Boris Brezillon:
> > Unless I'm missing something, it should be pretty easy to implement:
> > adding the following lines at the end of bitrot_check_worker() should do
> > th
heck) without risking to trigger a new action...
> >>
> >> Why would they care?
> >
> > I think is always useful to give some additional information in userspace,
> > from both debugging and diagnostic point of view.
>
> The question is, why does
On Thu, 28 May 2015 15:07:21 +0200
Nicolas Ferre wrote:
> Trivial fix that prevents to compile this pmc clock driver if h32mx clock is
> present but smd clock isn't.
>
> Signed-off-by: Nicolas Ferre
Acked-by: Boris Brezillon
> Fixes: bcc5fd49a0fd ("clk: at91: a
Hi Thierry,
Could you have a look at this patch (a.k.a. ping) ?
Best Regards,
Boris
On Thu, 30 Apr 2015 16:39:30 +0200
Boris Brezillon wrote:
> All modes exposed by simple panels should be tagged as driver defined
> modes.
> Moreover, if a panel supports only one mode, this mode is
On Thu, 30 Apr 2015 16:38:36 +0200
Boris Brezillon wrote:
> drm_display_mode_from_videomode() is already calling drm_mode_set_name() on
> the provided mode.
ping
>
> Signed-off-by: Boris Brezillon
> ---
> drivers/gpu/drm/panel/panel-simple.c | 1 -
> 1 file changed, 1
Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/marvell-cesa.txt| 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/marvell-cesa.txt
diff
their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 -
drivers/crypto/mv_cesa.c | 4 +++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
From: Arnaud Ebalard
Add support for Triple-DES operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 147
3
DES support
crypto: marvell/CESA: add MD5 support
crypto: marvell/CESA: add SHA256 support
crypto: marvell/CESA: add support for Kirkwood and Dove SoCs
Boris Brezillon (10):
crypto: mv_cesa: document the clocks property
crypto: mv_cesa: use gen_pool to reserve the SRAM memory region
From: Arnaud Ebalard
Add the Kirkwood and Dove SoC descriptions, and control the allhwsupport
module parameter to avoid probing the CESA IP when the old CESA driver is
enabled (unless it is explicitly requested to do so).
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
explicitly requested to do
so).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 42 +++---
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index c7e25a0..bd54973
From: Arnaud Ebalard
Add support for MD5 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 170 +-
3 files changed
Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/marvell-cesa.txt| 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/marvell-cesa.txt
diff
explicitly requested to do
so).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 42 +++---
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index c7e25a0..bd54973
From: Arnaud Ebalard
Add support for Triple-DES operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 147
3
From: Arnaud Ebalard
Add the Kirkwood and Dove SoC descriptions, and control the allhwsupport
module parameter to avoid probing the CESA IP when the old CESA driver is
enabled (unless it is explicitly requested to do so).
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
is stable/secure enough.
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index 087370e..c7e25a0 100644
--- a/drivers/crypto/marvell/cesa.c
+++ b/drivers/crypto
Add CESA IP description for all the missing armada SoCs (XP, 375 and 38x).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index e4dfee0..087370e
Add CESA IP description for all the missing armada SoCs (XP, 375 and 38x).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index e4dfee0..087370e
is stable/secure enough.
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index 087370e..c7e25a0 100644
--- a/drivers/crypto/marvell/cesa.c
+++ b/drivers/crypto
Add support for DES operations.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 150
3 files changed, 154 insertions
their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 -
drivers/crypto/mv_cesa.c | 4 +++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
per platform basis.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/marvell/Makefile | 2 +-
drivers/crypto/marvell/cesa.c | 68 +++
drivers/crypto/marvell/cesa.h | 229 ++
drivers/crypto
From: Arnaud Ebalard
Add support for MD5 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 170 +-
3 files changed
On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
From: Arnaud Ebalard
Add support for SHA256 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 157 ++
3 files
Add support for DES operations.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 150
3 files changed, 154 insertions
From: Arnaud Ebalard
Add support for SHA256 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 157 ++
3 files
per platform basis.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/marvell/Makefile | 2 +-
drivers/crypto/marvell/cesa.c | 68 +++
drivers/crypto/marvell/cesa.h | 229 ++
drivers/crypto
commit introduce the base infrastructure allowing us to add support
for DMA optimization.
It also includes support for one hash (SHA1) and one cipher (AES)
algorithm, and enable those features on the Armada 370 SoC.
Other algorithms and platforms will be added later on.
Signed-off-by: Boris Brezillon
commit introduce the base infrastructure allowing us to add support
for DMA optimization.
It also includes support for one hash (SHA1) and one cipher (AES)
algorithm, and enable those features on the Armada 370 SoC.
Other algorithms and platforms will be added later on.
Signed-off-by: Boris Brezillon
.
Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/mv_cesa.txt | 24 ++---
drivers/crypto/Kconfig
.
Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/mv_cesa.txt | 24 ++---
drivers/crypto/Kconfig
Sorry for the noise: apparently I forgot to remove existing patches
when regenerating the series with format-patch.
I'll resend the series tomorrow.
On Thu, 11 Jun 2015 19:36:19 +0200
Boris Brezillon wrote:
> Hello,
>
> This patch series adds a new driver supporting Marvell
From: Arnaud Ebalard
Add support for MD5 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 170 +-
3 files changed
s to the series
Arnaud Ebalard (4):
crypto: marvell/CESA: add Triple-DES support
crypto: marvell/CESA: add MD5 support
crypto: marvell/CESA: add SHA256 support
crypto: marvell/CESA: add support for Kirkwood and Dove SoCs
Boris Brezillon (10):
crypto: mv_cesa: document the clocks property
commit introduce the base infrastructure allowing us to add support
for DMA optimization.
It also includes support for one hash (SHA1) and one cipher (AES)
algorithm, and enable those features on the Armada 370 SoC.
Other algorithms and platforms will be added later on.
Signed-off-by: Boris Brezillon
From: Arnaud Ebalard
Add the Kirkwood and Dove SoC descriptions, and control the allhwsupport
module parameter to avoid probing the CESA IP when the old CESA driver is
enabled (unless it is explicitly requested to do so).
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
From: Arnaud Ebalard
Add support for Triple-DES operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 147
3
Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/marvell-cesa.txt| 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/marvell-cesa.txt
diff
Add CESA IP description for all the missing armada SoCs (XP, 375 and 38x).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index e4dfee0..087370e
is stable/secure enough.
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index 087370e..c7e25a0 100644
--- a/drivers/crypto/marvell/cesa.c
+++ b/drivers/crypto
explicitly requested to do
so).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 42 +++---
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index c7e25a0..bd54973
Add support for DES operations.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/cipher.c | 150
3 files changed, 154 insertions
their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 -
drivers/crypto/mv_cesa.c | 4 +++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
per platform basis.
Signed-off-by: Boris Brezillon
Signed-off-by: Arnaud Ebalard
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/marvell/Makefile | 2 +-
drivers/crypto/marvell/cesa.c | 68 +++
drivers/crypto/marvell/cesa.h | 229 ++
drivers/crypto
.
Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/mv_cesa.txt | 24 ++---
drivers/crypto/Kconfig
On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
From: Arnaud Ebalard
Add support for SHA256 operations.
Signed-off-by: Arnaud Ebalard
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 2 +
drivers/crypto/marvell/cesa.h | 2 +
drivers/crypto/marvell/hash.c | 157 ++
3 files
Hi Herbert,
On Mon, 15 Jun 2015 18:09:20 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:57AM +0200, Boris Brezillon wrote:
> >
> > + ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
> > +DMA_TO_DEVICE);
> > + if
On Mon, 15 Jun 2015 17:59:44 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote:
> > +struct ahash_alg mv_ahmac_sha1_alg = {
> > + .init = mv_cesa_ahmac_sha1_init,
> > + .update = mv_cesa_ahash_update,
> > + .
On Mon, 15 Jun 2015 17:54:21 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote:
> >
> > +static int mv_cesa_cbc_aes_op(struct ablkcipher_request *req,
> > + struct mv_cesa_op_ctx *tmpl)
> > +{
> &g
On Mon, 15 Jun 2015 17:48:27 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote:
> >
> > +static void mv_cesa_dequeue_req_unlocked(struct mv_cesa_engine *engine)
> > +{
> > + struct crypto_async_request *req;
>
On Mon, 15 Jun 2015 17:37:54 +0800
Herbert Xu wrote:
> On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote:
> >
> > +static inline int mv_cesa_sg_count(struct scatterlist *sg, int nbytes)
> > +{
> > + int nents = 0;
> > +
> > + whi
5d2-flexcom";
reg = <0xf8034000 0x800>;
clocks = <&flx0_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8034000 0x800>;
atmel,flexcom-mode = "spi";
usart@200 {
reg = <0x200 0x100>;
))
> + mr = FX_MR_USART;
> + else if (!strcmp(mode, "spi"))
> + mr = FX_MR_SPI;
> + else if (!strcmp(mode, "twi") || !strcmp(mode, "i2c"))
> + mr = FX_MR_TWI;
> + else
> + return -EINVAL;
CBC test vectors.
Other cipher modes (LRW, CTR, ...) should be updated too.
Best Regards,
Boris
Boris Brezillon (2):
crypto: testmgr: test IV value after a cipher operation
crypto: testmgr: add iv_out information for all CBC testvec
crypto/testmgr.c | 12 -
crypto/testmgr.h | 82
Add iv_out information to all CBC testvec so that the testmgr can verify
the IV value after each cipher request.
Signed-off-by: Boris Brezillon
---
crypto/testmgr.h | 81
1 file changed, 81 insertions(+)
diff --git a/crypto/testmgr.h b
The crypto drivers are supposed to update the IV passed to the crypto
request before calling the completion callback.
Test for the IV value before considering the test as successful.
Signed-off-by: Boris Brezillon
---
crypto/testmgr.c | 12 +++-
crypto/testmgr.h | 1 +
2 files changed
A: add Triple-DES support
crypto: marvell/CESA: add MD5 support
crypto: marvell/CESA: add SHA256 support
crypto: marvell/CESA: add support for Kirkwood and Dove SoCs
Boris Brezillon (10):
crypto: mv_cesa: document the clocks property
crypto: mv_cesa: use gen_pool to reserve the SRAM memory re
On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
.
Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/mv_cesa.txt | 24 ++---
drivers/crypto/Kconfig
their crypto engine device
to this driver.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 -
drivers/crypto/mv_cesa.c | 4 +++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
explicitly requested to do
so).
Signed-off-by: Boris Brezillon
---
drivers/crypto/marvell/cesa.c | 42 +++---
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/marvell/cesa.c b/drivers/crypto/marvell/cesa.c
index a05b5cb..8e5ea72
Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/crypto/marvell-cesa.txt| 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/marvell-cesa.txt
diff
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