with and without dt support, but it
has not been tested.
The clocks rate/parent change has not been tested.
Best Regards,
Boris
Boris BREZILLON (50):
ARM: at91: move arch/arm/mach-at91/include/mach/at91_pmc.h to
include/linux/clk/at91.h
ARM: at91: add PMC main clock using common clk framework.
ARM
datasheets).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clk/at91/Makefile |2 +
drivers/clk/at91/clk-programmable.c | 370 +++
include/linux/clk/at91.h| 18 ++
3 files changed, 390 insertions(+)
diff --git a/drivers
-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clk/at91/Makefile |2 +-
drivers/clk/at91/clk-peripheral.c | 376 +
include/linux/clk/at91.h | 14 +-
3 files changed, 388 insertions(+), 4 deletions(-)
diff --git a/drivers/clk
This is the at91 system clock implementation using common clk framework.
Some peripheral needs to enable a system clock in order to work properly.
Each system clock is given an id which is the bit offset used in SCER/SCDR
registers.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91.h).
We need this to avoid reference to machine specific headers in clk
drivers.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
This is the at91 usb clock implementation using common clk framework.
This clock is used to clock usb ports (ohci, ehci and udc).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/Kconfig | 11 ++
drivers/clk/at91/Makefile |1 +
drivers/clk/at91/clk-usb.c
during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
Electrical Characteristics paragraph.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clk/at91/Makefile |2 +-
drivers/clk/at91/clk-master.c | 317
driver
- remove already applied patches (ehci, ohci, dma and serial)
Changes since common clk patch series:
- add clk_prepare_enable return check
- fix a deadlock in atmel-mci (missing spin_unlock)
- remove already applied patches (atmel-ssc and pwm-atmel-tcb)
Boris BREZILLON (4):
ARM: at91
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clocksource/tcb_clksrc.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/mmc/host/atmel-mci.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/usb/gadget/at91_udc.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/usb
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/video/atmel_lcdfb.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/video
specific irq handler inside the the init
functions using set_handle_irq. This way we can remove all the machine
specific handle_irq.
This patch series was tested on kizbox board (sam9g20 SoC) using
device tree. Could someone test it on other boards (both dt and non dt)?
Best Regards,
Boris
Boris
Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
Move arch/arm/mach-at91/at91_aic.h to
arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
to header file :
#include ../../arch/arm/mach-at91/at91_aic.h
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm
Replace machine specific init_irq functions with IRQCHIP_DECLARE.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/board-dt-rm9200.c | 11 ---
arch/arm/mach-at91/board-dt-sam9.c | 12
arch/arm/mach-at91/board-dt-sama5.c | 12
Set machine specific irq handler using set_handle_irq inside aic init functions
instead of handle_irq pointer from machine_desc.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/board-1arm.c|1 -
arch/arm/mach-at91/board-afeb-9260v1.c |1
From: Boris BREZILLON brezillonbo...@gmail.com
Replace machine specific init_irq functions with IRQCHIP_DECLARE.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/board-dt-rm9200.c | 11 ---
arch/arm/mach-at91/board-dt-sam9.c | 12
arch/arm
From: Boris BREZILLON brezillonbo...@gmail.com
Set machine specific irq handler using set_handle_irq inside aic init
functions instead of handle_irq pointer from machine_desc.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/board-1arm.c|1 -
arch
it on other boards (both dt and non dt)?
Best Regards,
Boris
Boris BREZILLON (3):
ARM: at91: move at91 aic driver to drivers/irqchip
ARM: at91: use IRQCHIP_DECLARE instead of machine specific init_irq
ARM: at91: use set_handle_irq instead of machine specific handle_irq
arch/arm/mach-at91
On 23/05/2013 14:13, Thomas Petazzoni wrote:
Dear Russell King - ARM Linux,
On Thu, 23 May 2013 11:18:25 +0100, Russell King - ARM Linux wrote:
I notice arch/arm/mach-at91/pm.c makes use of some of the register
definitions:
at91_irq_suspend();
pr_debug(AT91: PM - wake mask
On 23/05/2013 11:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 11:05 Thu 23 May , Boris BREZILLON wrote:
Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
Move arch/arm/mach-at91/at91_aic.h to
arch/arm/mach-at91/include/mach/at91_aic.h to avoid ugly reference
to header file
Replace machine specific init_irq functions with IRQCHIP_DECLARE.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/board-dt-rm9200.c | 11 ---
arch/arm/mach-at91/board-dt-sam9.c | 12
arch/arm/mach-at91/board-dt-sama5.c | 12
The PA24 pin is wrongly assigned to peripheral B.
In the current config there is 2 ETX3 pins (PA11 and PA24) and
no ETXER pin (PA22).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91sam9260.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Set machine specific irq handler using set_handle_irq inside aic init
functions instead of handle_irq pointer from machine_desc.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/at91_aic.h |3 ---
arch/arm/mach-at91/board-1arm.c |1 -
arch
Move arch/arm/mach-at91/irq.c to drivers/irqchip/irq-at91.c.
Move arch/arm/mach-at91/at91_aic.h to include/linux/irqchip/at91.h to
avoid reference to machine specific hearder files.
Remove __ASSEMBLY__ section in header file (at91_aic_base is only used
in .c files).
Signed-off-by: Boris BREZILLON
- at91xxx.c : NR_AICX_IRQS
Please let me know what you think is best.
Best Regards,
Boris
Boris BREZILLON (3):
ARM: at91: use set_handle_irq instead of machine specific handle_irq
ARM: at91: move at91 aic driver to drivers/irqchip
ARM: at91: use IRQCHIP_DECLARE instead of machine specific
Hello,
I sent a patch 1 month ago to add pinctrl support to pwm-atmel-tcb
driver and didn't get any review.
Could you take a look?
This patch adds pins request for the pwm device exposed by the TC
block using the pinctrl subsystem.
Best Regards,
Boris
Signed-off-by: Boris BREZILLON b.brezil
On 23/05/2013 21:35, Thierry Reding wrote:
On Thu, May 23, 2013 at 06:38:52PM +0200, Boris BREZILLON wrote:
Hello,
I sent a patch 1 month ago to add pinctrl support to pwm-atmel-tcb
driver and didn't get any review.
Could you take a look?
This patch adds pins request for the pwm device
Hello,
This patch adds pinctrl configs for at91 Timer Conter blocks.
These pin configs will be referenced by atmel,tcb-pwm devices to
setup pins as PWM output.
Best Regards,
Boris
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/boot/dts/at91rm9200.dtsi | 76
On 24/05/2013 16:12, Nicolas Ferre wrote:
On 24/05/2013 16:05, Jean-Christophe PLAGNIOL-VILLARD :
On 12:05 Fri 24 May , Boris BREZILLON wrote:
Hello,
This patch adds pinctrl configs for at91 Timer Conter blocks.
These pin configs will be referenced by atmel,tcb-pwm devices to
setup pins
Fix the secs_to_ticks macro in case 0 is passed as an argument.
Rework the heartbeat calculation to increase the security margin of the
watchdog reset timer.
Use the min_heartbeat value instead of the calculated heartbeat value for
the first watchdog reset.
Signed-off-by: Boris BREZILLON
and error messages
- remove unneeded parenthesis in arithmetic operations
- use devm functions to map io memory
- remove unneeded devm_kfree calls
Change since v1:
- fix typo in documentaion
- fix irq dt definition for sama5d3 SoC
Boris BREZILLON (4):
watchdog: at91sam9_wdt: better
On 29/10/2013 13:58, Wim Van Sebroeck wrote:
Hi Boris,
I'm sorry for the inconvenience, but I found some bugs in my patch series:
1) the secs_to_ticks returns an erronous value when 0 is passed as an
argument
2) the calculated heartbeat is too small for some use cases
(i.e. kexecing a
On 29/10/2013 16:45, Guenter Roeck wrote:
On Tue, Oct 29, 2013 at 11:37:33AM +0100, Boris BREZILLON wrote:
Fix the secs_to_ticks macro in case 0 is passed as an argument.
Rework the heartbeat calculation to increase the security margin of the
watchdog reset timer.
Use the min_heartbeat value
On 29/10/2013 17:43, Guenter Roeck wrote:
On Tue, Oct 29, 2013 at 05:22:50PM +0100, boris brezillon wrote:
On 29/10/2013 16:45, Guenter Roeck wrote:
On Tue, Oct 29, 2013 at 11:37:33AM +0100, Boris BREZILLON wrote:
Fix the secs_to_ticks macro in case 0 is passed as an argument.
Rework
brezillon wrote:
On 29/10/2013 17:43, Guenter Roeck wrote:
On Tue, Oct 29, 2013 at 05:22:50PM +0100, boris brezillon wrote:
On 29/10/2013 16:45, Guenter Roeck wrote:
On Tue, Oct 29, 2013 at 11:37:33AM +0100, Boris BREZILLON wrote:
Fix the secs_to_ticks macro in case 0 is passed as an argument.
Rework
(to avoid spurious watchdog
reset).
Best Regards,
Boris
Boris BREZILLON (3):
watchdog: at91sam9_wdt: fix secs_to_ticks
watchdog: at91sam9_wdt: avoid spurious watchdog reset during init
watchdog: at91sam9_wdt: increase security margin on watchdog counter
reset
drivers/watchdog
Fix the secs_to_ticks macro in case 0 is passed as an argument.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/watchdog/at91sam9_wdt.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
to be
in such a case.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/watchdog/at91sam9_wdt.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 65f4691..ab0c4e0 100644
--- a/drivers
On 03/11/2013 17:22, Guenter Roeck wrote:
On 11/03/2013 06:42 AM, boris brezillon wrote:
Hello Guenter,
Are you okay with the 3 fixes/improvements provided by this patch,
and the explanation I gave regarding the reason for these changes ?
If so, I will submit a new series splitting the patch
Try to reset the watchdog counter 4 or 2 times more often than actually
requested, to avoid spurious watchdog reset.
If this is not possible because of the min_heartbeat value, reset it at
the min_heartbeat period.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/watchdog
Hello Nicolas,
On 07/10/2013 17:07, Nicolas Ferre wrote:
On 08/08/2013 07:01, Boris BREZILLON :
This patch adds at91 PMC (Power Management Controller) base support.
All at91 clocks managed by the PMC unit will use this framework.
This framework provides the following fonctionalities
On 07/10/2013 17:12, Nicolas Ferre wrote:
On 08/08/2013 07:02, Boris BREZILLON :
This patch adds the following Kconfig options to prepare the
transition to
common clk framework:
- AT91_USE_OLD_CLK: this option is selected by every SoC which does not
support new at91 clks based on common
On 07/10/2013 17:17, Nicolas Ferre wrote:
On 08/08/2013 07:04, Boris BREZILLON :
This patch adds a new macro file for PMC macros.
This macro file includes the definitions of SR (status register) bit
offsets and will be use to reference PMC irqs.
Signed-off-by: Boris BREZILLON b.brezil
On 07/10/2013 18:51, Nicolas Ferre wrote:
On 08/08/2013 07:06, Boris BREZILLON :
This patch adds new at91 main oscillator clock implementation using
common
clk framework.
If rate is not provided during clock registration it is calculated using
the slow clock (main clk parent in this case
On 08/10/2013 10:24, Nicolas Ferre wrote:
On 07/10/2013 21:11, boris brezillon :
On 07/10/2013 18:51, Nicolas Ferre wrote:
On 08/08/2013 07:06, Boris BREZILLON :
This patch adds new at91 main oscillator clock implementation using
common
clk framework.
If rate is not provided during clock
On 08/10/2013 12:28, Nicolas Ferre wrote:
On 08/08/2013 08:07, Boris BREZILLON :
This patch adds new at91 pll clock implementation using common clk
framework.
The pll clock layout describe the PLLX register layout.
There are four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
On 08/10/2013 12:30, Nicolas Ferre wrote:
On 08/08/2013 08:09, Boris BREZILLON :
This patch adds the PLL id macros which will be used by pll dt
definitions.
It is not needed, drop it. Just document the values in the DT biding
and it will be fine.
I'll drop (and document) it.
Signed
On 08/10/2013 11:44, Nicolas Ferre wrote:
On 08/08/2013 09:19, Boris BREZILLON :
This patch adds new at91 clks dt bindings documentation.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
.../devicetree/bindings/clock/at91-clock.txt | 312
1 file
On 08/10/2013 17:44, Nicolas Ferre wrote:
On 08/08/2013 09:10, Boris BREZILLON :
This patch adds the peripheral divisors macros (for sam9x5 compatible
IPs)
which will be used by peripheral clk dt definitions.
I am in favor for these definitions. So let's keep them (with raw
numbers
On 08/10/2013 18:15, Nicolas Ferre wrote:
On 08/10/2013 18:01, boris brezillon :
On 08/10/2013 17:44, Nicolas Ferre wrote:
On 08/08/2013 09:10, Boris BREZILLON :
This patch adds the peripheral divisors macros (for sam9x5 compatible
IPs)
which will be used by peripheral clk dt definitions.
I
On 07/10/2013 17:12, Nicolas Ferre wrote:
On 08/08/2013 07:02, Boris BREZILLON :
This patch adds the following Kconfig options to prepare the
transition to
common clk framework:
- AT91_USE_OLD_CLK: this option is selected by every SoC which does not
support new at91 clks based on common
implementation. These SoCs won't setup the
register_clocks callback (clk registration is done using of_clk_init).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/Kconfig| 21 +
arch/arm/mach-at91/Kconfig.non_dt |6 ++
arch/arm/mach
This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91_pmc.h).
We need this to avoid reference to machine specific headers in clk
drivers.
Signed-off-by: Boris BREZILLON b.brezil
matching
the definitions in pmc_clk_ids).
This patch copies at91_pmc_base (memory mapping) and at91sam9_idle
(function) from arch/arm/mach-at91/clock.c (which is not compiled if
COMMON_CLK_AT91 is enabled).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clk/Makefile |1
interfaces (no need to define a parent clock,
system clock is a gate with no rate info)
- change system, peripheral and programmable clk dt bindings (1 master node
and multiple child nodes each defining a system/peripheral or prog clock)
- fix bugs in sama5 dt definition
Boris BREZILLON (17
This patch adds a new macro file for PMC macros.
This macro file includes the definitions of SR (status register) bit
offsets and will be use to reference PMC irqs.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
include/dt-bindings/clk/at91.h | 22 ++
1 file
are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
Electrical Characteristics paragraph.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clk/at91/Makefile |2 +-
drivers/clk/at91/clk-master.c | 278
This patch adds new at91 main oscillator clock implementation using common
clk framework.
If rate is not provided during clock registration it is calculated using
the slow clock (main clk parent in this case) rate and MCFR register.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
to
define and reference peripheral clocks.
Some new SoCs (at91sam9x5 and sama5d3) provide a new register (PCR) where you
can configure the peripheral clock as a division of the master clock.
This will help reducing the peripherals power comsumption.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
This patch adds new at91 system clock implementation using common clk
framework.
Some peripherals need to enable a system clock in order to work properly.
Each system clock is given an id based on the bit position in SCER/SCDR
registers.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
This patch adds the peripheral divisors macros (for sam9x5 compatible IPs)
which will be used by peripheral clk dt definitions.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
include/dt-bindings/clk/at91.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/include/dt
atmel's datasheets).
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clk/at91/Makefile |2 +
drivers/clk/at91/clk-programmable.c | 423 +++
drivers/clk/at91/pmc.c | 15 ++
drivers/clk/at91/pmc.h |9 +
4
-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/clk/at91/Makefile |2 +-
drivers/clk/at91/clk-pll.c| 545 +
drivers/clk/at91/clk-plldiv.c | 137 +++
drivers/clk/at91/pmc.c| 21 ++
drivers/clk/at91/pmc.h| 11
This adds new at91 utmi clock implementation using common clk framework.
This clock is a pll with a fixed factor (x40).
It is used as a source for usb clock.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
arch/arm/mach-at91/Kconfig |7 ++
drivers/clk/at91/Makefile |1
it.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
drivers/pinctrl/pinctrl-at91.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5d7529e..76e108d 100644
--- a/drivers/pinctrl
Le 17/07/2013 16:49, Boris BREZILLON a écrit :
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9g45 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON b.brezil
Le 23/07/2013 20:03, Jean-Christophe PLAGNIOL-VILLARD a écrit :
On 15:37 Wed 17 Jul , Boris BREZILLON wrote:
This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91.h).
please
Add vendor prefix for Foxlink Group.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree
This panel is used by Atmel's SAMA5D3 Evaluation Kits (sama5d3xek) and
supported by the simple-panel driver.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../bindings/panel/foxlink,fl500wvr00-a0t.txt | 7 ++
drivers/gpu/drm/panel/panel-simple.c
Hello,
This series adds a new entry in the vendor-prefixes.txt file for Foxlink
Group and defines Foxlink FL500WVR00-A0T panel specifications in the simple
panel driver.
Best Regards,
Boris
Boris BREZILLON (2):
DT: add vendor prefix for Foxlink Group
drm/panel: add support for Foxlink
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12,
at91sam9x5 family or sama5d3 family) provide a PWM device.
This driver add support for this PWM device.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt
access the HLCDC register range
concurrently.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../devicetree/bindings/mfd/atmel-hlcdc.txt| 41
drivers/mfd/Kconfig| 11 ++
drivers/mfd/Makefile
Enable LCD related nodes and reference panel node in the hlcdc (High
LCD Controller) controller on sama5d3xek boards.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sama5d31ek.dts | 24
arch/arm/boot/dts/sama5d33ek.dts | 24
- add support for overlays
- add support for hardware cursor
Boris BREZILLON (7):
mfd: add atmel-hlcdc driver
pwm: add support for atmel-hlcdc-pwm device
drm: add Atmel HLCDC Display Controller support
ARM: AT91/dt: split sama5d3 lcd pin definitions to match RGB mode
configs
ARM: at91/dt
Add LCD panel related nodes (backlight, regulators and panel) to the
sama5d3 Display Module dtsi.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sama5d3xdm.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm
The HLCDC (High LCD Controller) IP supports 4 different output mode
(RGB444, RGB565, RGB666 and RGB888) and the pin muxing depends on the
chosen RGB mode.
Split the pin definition to be able to set the pin config according to the
selected mode.
Signed-off-by: Boris BREZILLON boris.brezil...@free
Define the HLCDC (High LCD Controller) IP available on some sama5d3 SoCs
(i.e. sama5d31, sama5d33, sama5d34 and sama5d36).
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sama5d3_lcd.dtsi | 26 ++
1 file changed, 26 insertions
Hello Wolfram,
On 10/06/2014 10:38, Wolfram Sang wrote:
On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
The P2WI looks like an SMBus controller which only supports byte data
transfers. But, it differs from standard SMBus protocol on several
aspects:
- it supports only one
On 10/06/2014 10:54, Boris BREZILLON wrote:
Hello Wolfram,
On 10/06/2014 10:38, Wolfram Sang wrote:
On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
The P2WI looks like an SMBus controller which only supports byte data
transfers. But, it differs from standard SMBus protocol
Hello Mark,
Did you have time to take a look at this patch ?
I'd like to post a new version of this series addressing Lee's comments,
but it would be great to have your feedback on this patch before posting
a new version.
Best Regards,
Boris
On 27/05/2014 11:38, Boris BREZILLON wrote:
PMIC
Changes since v3:
- update the DT bindings doc
- fix a comment that was no longer true
Changes since v2:
- drop the initialization (switch from I2C to P2WI mode) part
- print devm_ioremap_resource err code
Boris BREZILLON (2):
i2c: sunxi: add P2WI DT bindings documentation
i2c: sunxi: add P2WI
-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/i2c/busses/Kconfig | 12 ++
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-sun6i-p2wi.c | 356
3 files changed, 369 insertions(+)
create mode 100644 drivers/i2c
P2WI (Push/Pull 2 Wire Interface) is an SMBus like bus used to communicate
with some PMICs (like the AXP221).
Document P2WI DT bindings which are pretty much the same as the one defined
for the marvell's mv64xxx controller.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Hello Paul,
On 10/06/2014 10:56, Paul Carpenter wrote:
Wolfram Sang wrote:
On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
The P2WI looks like an SMBus controller which only supports byte data
transfers. But, it differs from standard SMBus protocol on several
aspects
The rtc user must wait at least 1 sec between each time/calandar update
(see atmel's datasheet chapter Updating Time/Calendar).
Use the SECEV interrupt (as suggested by the datasheet) to wait for the
RTC to be ready for new updates.
Cc: sta...@vger.kernel.org # v3.10+
Signed-off-by: Boris
.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
Changes since v3:
- add IGNORE_UNUSED flags to slow osc clks
drivers/clk/at91/Makefile| 4 +-
drivers/clk/at91/clk-slow.c | 467 +++
drivers/clk/at91/pmc.c | 5 +
drivers
families) the multiplexer source is
hardcoded to the external crystal oscillator.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
Changes since v3:
- add IGNORE_UNUSED flags to main osc clks
drivers/clk/at91/clk-main.c | 577
The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
mask all interrupts no matter what IMR claims about already masked irqs.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Reported-by: Bryan Evenson beven...@melinkcorp.com
---
Hello Bryan,
Yet another
On 29/04/2014 01:40, Maxime Ripard wrote:
On Mon, Apr 28, 2014 at 04:58:48PM +0200, Boris BREZILLON wrote:
The PRCM (Power/Reset/Clock Management) unit provides several clock
devices:
- AR100 clk: used to clock the Power Management co-processor
- AHB0 clk: used to clock the AHB0 bus
- APB0
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 39 ++-
1 file changed, 38 insertions(+), 1 deletion
Changes since v1:
- fix prcm and prcm-clks DT documentation
- remove unneeded iounmap and kfree calls from sunxi_reset_remove function
- rework the AR100 clk implementation
Boris BREZILLON (7):
reset: sunxi: document sunxi's reset controllers bindings
reset: sunxi: allow MFD subdevices probe
mfd
Add DT bindings documentation for sunxi's reset controllers.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../bindings/reset/allwinner,sunxi-clock-reset.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644
Documentation/devicetree
.
Moreover, we can make of devm functions when we're in the probe context.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/reset/reset-sunxi.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/reset-sunxi.c b
so that they can be probed
as platform devices instead of registered during early init.
This is needed to be able to probe PRCM MFD subdevices.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/clk/sunxi/Makefile | 2 +
drivers/clk/sunxi/clk-sun6i-prcm.c | 343
Document DT bindings of the PRCM (Power/Reset/Clock Management) unit.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../devicetree/bindings/mfd/sun6i-prcm.txt | 59 ++
1 file changed, 59 insertions(+)
create mode 100644 Documentation
mode 100644
index 000..0156bcb
--- /dev/null
+++ b/drivers/mfd/sun6i-prcm.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2014 Free Electrons
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Boris BREZILLON boris.brezil...@free-electrons.com
+ *
+ * Allwinner PRCM (Power/Reset/Clock
Document new compatible strings for clock provided by the PRCM
(Power/Reset/Clock Management) unit.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
Documentation/devicetree/bindings/clock/sunxi.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation
P2WI (Push/Pull 2 Wire Interface) is an SMBus like bus used to communicate
with some PMICs (like the AXP221).
Document P2WI DT bindings which are pretty much the same as the one defined
for the marvell's mv64xxx controller.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
return check
- rework the macro definitions
- fix typos
[1] http://www.spinics.net/lists/linux-i2c/msg15066.html
[2] http://comments.gmane.org/gmane.comp.hardware.netbook.arm.sunxi/8947
Boris BREZILLON (2):
i2c: sunxi: add P2WI DT bindings documentation
i2c: sunxi: add P2WI (Push/Pull 2 Wire
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