Re: [PATCH 06/10] reset: socfpga: add driver Kconfig option

Hi Philipp, just a minor nit: On 08/24/2016 08:28 AM, Philipp Zabel wrote: > Visible only if COMPILE_TEST is enabled, this allows to include the > driver in build tests. > > Cc: Dinh Nguyen > Signed-off-by: Philipp Zabel > --- > drivers/reset/Kconfig | 6 ++ > dr

Re: [RFC RESEND] serial: 8250: fix regression in 8250 uart driver

Hi Andy, On 08/17/2016 06:14 AM, Andy Shevchenko wrote: > > I sent a v2 of the series for internal review, same you may found on > [1]. If Heikki is okay to that I'll send it here. > > [1] https://bitbucket.org/andy-shev/linux/branch/topic%2Fdw%2Fqrk > I tested this branch on SoCFPGA hardware

Re: [RFC RESEND] serial: 8250: fix regression in 8250 uart driver

Hi Andy, On 08/17/2016 06:14 AM, Andy Shevchenko wrote: > > I sent a v2 of the series for internal review, same you may found on > [1]. If Heikki is okay to that I'll send it here. > > [1] https://bitbucket.org/andy-shev/linux/branch/topic%2Fdw%2Fqrk > I tested this branch on SoCFPGA hardware

Re: [PATCH 3/3] ARM: dts: Add Arria10 SD/MMC EDAC devicetree entry

ha...@opensource.altera.com> > --- > arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 12 > 1 file changed, 12 insertions(+) > Acked-by: Dinh Nguyen <dingu...@opensource.altera.com> Thanks, Dinh

Re: [PATCH 3/3] ARM: dts: Add Arria10 SD/MMC EDAC devicetree entry

0_socdk_sdmmc.dts | 12 > 1 file changed, 12 insertions(+) > Acked-by: Dinh Nguyen Thanks, Dinh

Re: [PATCH 10/10] ARM: dts: Add Arria10 USB EDAC devicetree entry

interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, > + <34 IRQ_TYPE_LEVEL_HIGH>; > + }; > }; > > rst: rstmgr@ffd05000 { > Acked-by: Dinh Nguyen <dingu...@opensource.altera.com> Dinh

Re: [PATCH 10/10] ARM: dts: Add Arria10 USB EDAC devicetree entry

<34 IRQ_TYPE_LEVEL_HIGH>; > + }; > }; > > rst: rstmgr@ffd05000 { > Acked-by: Dinh Nguyen Dinh

Re: [PATCH 09/10] ARM: dts: Add Arria10 DMA EDAC devicetree entry

interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, > + <42 IRQ_TYPE_LEVEL_HIGH>; > + }; > }; > > rst: rstmgr@ffd05000 { > Acked-by: Dinh Nguyen <dingu...@opensource.altera.com> Dinh

Re: [PATCH 09/10] ARM: dts: Add Arria10 DMA EDAC devicetree entry

<42 IRQ_TYPE_LEVEL_HIGH>; > + }; > }; > > rst: rstmgr@ffd05000 { > Acked-by: Dinh Nguyen Dinh

Re: [PATCH 1/3] reset: socfpga: no need to store modrst_offset

set/reset-socfpga.c | 19 +-- > 1 file changed, 9 insertions(+), 10 deletions(-) > In case you want it: Tested-by: Dinh Nguyen <dingu...@opensource.altera.com> Thanks, Dinh

Re: [PATCH 1/3] reset: socfpga: no need to store modrst_offset

> 1 file changed, 9 insertions(+), 10 deletions(-) > In case you want it: Tested-by: Dinh Nguyen Thanks, Dinh

Re: [RESEND PATCH] usb: dwc2: Add reset control to dwc2

Ping? Dinh On 06/21/2016 02:12 PM, dingu...@opensource.altera.com wrote: > From: Dinh Nguyen <dingu...@opensource.altera.com> > > Allow for platforms that have a reset controller driver in place to bring > the USB IP out of reset. > > Signed-off-by: Dinh Nguyen <din

Re: [RESEND PATCH] usb: dwc2: Add reset control to dwc2

Ping? Dinh On 06/21/2016 02:12 PM, dingu...@opensource.altera.com wrote: > From: Dinh Nguyen > > Allow for platforms that have a reset controller driver in place to bring > the USB IP out of reset. > > Signed-off-by: Dinh Nguyen > Acked-by: John Youn > Tested-by

Re: [PATCHv5 8/8] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry

On 06/27/2016 11:18 AM, Borislav Petkov wrote: > On Mon, Jun 27, 2016 at 10:31:29AM -0500, Dinh Nguyen wrote: >> I've applied this patch and will take through the arm-soc tree. > > I already took the whole branch two days ago: > > http://git.kernel.org/cgit/linux/kernel

Re: [PATCHv5 8/8] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry

On 06/27/2016 11:18 AM, Borislav Petkov wrote: > On Mon, Jun 27, 2016 at 10:31:29AM -0500, Dinh Nguyen wrote: >> I've applied this patch and will take through the arm-soc tree. > > I already took the whole branch two days ago: > > http://git.kernel.org/cgit/linux/kernel

Re: [PATCHv5 8/8] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry

Hi Boris, On 06/22/2016 08:58 AM, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree entries needed to support the Altera Ethernet > FIFO buffer EDAC on the Arria10 chip. > > Signed-off-by: Thor Thayer

Re: [PATCHv5 8/8] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry

Hi Boris, On 06/22/2016 08:58 AM, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree entries needed to support the Altera Ethernet > FIFO buffer EDAC on the Arria10 chip. > > Signed-off-by: Thor Thayer > --- > v2 No change > v3 Add interrupts for SBERR and

[RFC RESEND] serial: 8250: fix regression in 8250 uart driver

Apologies, but my original email bounced for Andy and Heikki, resending. Hi Andy, I saw that you have discovered that commit ec5a11a91eec ("serial: 8250: Validate dmaengine rx chan meets requirements") introduced a regression in the 8250 uart driver. For SoCFPGA platform, I am seeing this

[RFC RESEND] serial: 8250: fix regression in 8250 uart driver

Apologies, but my original email bounced for Andy and Heikki, resending. Hi Andy, I saw that you have discovered that commit ec5a11a91eec ("serial: 8250: Validate dmaengine rx chan meets requirements") introduced a regression in the 8250 uart driver. For SoCFPGA platform, I am seeing this

[RFC] serial: 8250: fix regression in 8250 uart driver

Hi Andy, I saw that you have discovered that commit ec5a11a91eec ("serial: 8250: Validate dmaengine rx chan meets requirements") introduced a regression in the 8250 uart driver. For SoCFPGA platform, I am seeing this error: [5.541751] ttyS0 - failed to request DMA Reverting the commit

[RFC] serial: 8250: fix regression in 8250 uart driver

Hi Andy, I saw that you have discovered that commit ec5a11a91eec ("serial: 8250: Validate dmaengine rx chan meets requirements") introduced a regression in the 8250 uart driver. For SoCFPGA platform, I am seeing this error: [5.541751] ttyS0 - failed to request DMA Reverting the commit

Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger

0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; For SOCFPGA: Acked-by: Dinh Nguyen <dingu...@opensource.altera.com> Thanks, Dinh

Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger

<1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; For SOCFPGA: Acked-by: Dinh Nguyen Thanks, Dinh

Re: [PATCH 4/5] ARM: dts: Arria10 ECC Manager IRQ controller changes

On Wed, 25 May 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Changes to support IRQ controller implementation including adding > new property irq-controller to eccmgr and adding IRQ property > to children. > > Signed-off-by: Thor Thayer

Re: [PATCH 4/5] ARM: dts: Arria10 ECC Manager IRQ controller changes

On Wed, 25 May 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Changes to support IRQ controller implementation including adding > new property irq-controller to eccmgr and adding IRQ property > to children. > > Signed-off-by: Thor Thayer > --- >

Re: [PATCH 5/5] ARM: dts: Move Arria10 SDRAM as child of ECC Manager

On Wed, 25 May 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Changes to support ECC Manager as SDRAM IRQ parent by > 1) updating IRQ property values to correct child IRQs > 2) moving node under ECC Manager. > > Signed-off-by: Thor Thayer

Re: [PATCH 5/5] ARM: dts: Move Arria10 SDRAM as child of ECC Manager

On Wed, 25 May 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Changes to support ECC Manager as SDRAM IRQ parent by > 1) updating IRQ property values to correct child IRQs > 2) moving node under ECC Manager. > > Signed-off-by: Thor Thayer > --- >

Re: [PATCHv2 7/7] ARM: dts: Add Altera Arria10 OCRAM EDAC devicetree entry

On Thu, 31 Mar 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree entries needed to support the Altera On-Chip > RAM EDAC on the Arria10 chip. > > Signed-off-by: Thor Thayer > --- > v2: No change

Re: [PATCHv2 7/7] ARM: dts: Add Altera Arria10 OCRAM EDAC devicetree entry

On Thu, 31 Mar 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree entries needed to support the Altera On-Chip > RAM EDAC on the Arria10 chip. > > Signed-off-by: Thor Thayer > --- > v2: No change > --- > arch/arm/boot/dts/socfpga_arria10.dtsi |5 +

Re: [PATCHv2 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup

e applied 1-4 already. > > Yes, no? > > If no, then please send only an updated version of this patch as a reply > to this thread here. > My only suggestion was to change the 3 helper functions(ecc_set_bits, ecc_clear_bits, and ecc_test_bits) should be static inline. So with tha

Re: [PATCHv2 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup

e applied 1-4 already. > > Yes, no? > > If no, then please send only an updated version of this patch as a reply > to this thread here. > My only suggestion was to change the 3 helper functions(ecc_set_bits, ecc_clear_bits, and ecc_test_bits) should be static inline. So with t

Re: [PATCH 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup

On Wed, 30 Mar 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to be > enabled before data is stored in memory otherwise the ECC will fail > on reads. > > Signed-off-by: Thor

Re: [PATCH 6/7] ARM: socfpga: Enable Arria10 OCRAM ECC on startup

On Wed, 30 Mar 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to be > enabled before data is stored in memory otherwise the ECC will fail > on reads. > > Signed-off-by: Thor Thayer > --- [snip] > + >

Re: [PATCH v3 0/8] arm64: rockchip: Initial GeekBox enablement

On Tue, Mar 15, 2016 at 7:36 AM, Giuseppe CAVALLARO wrote: > Hello Tomeu > > On 3/15/2016 8:23 AM, Tomeu Vizoso wrote: >> >> Thanks. >> >> Btw, I have rebased on top of 4.5 this morning and I have noticed that >> 88f8b1bb41c6 ("stmmac: Fix 'eth0: No PHY found' regression")

Re: [PATCH v3 0/8] arm64: rockchip: Initial GeekBox enablement

On Tue, Mar 15, 2016 at 7:36 AM, Giuseppe CAVALLARO wrote: > Hello Tomeu > > On 3/15/2016 8:23 AM, Tomeu Vizoso wrote: >> >> Thanks. >> >> Btw, I have rebased on top of 4.5 this morning and I have noticed that >> 88f8b1bb41c6 ("stmmac: Fix 'eth0: No PHY found' regression") got in >> there, so I

Re: [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

On Tue, Mar 29, 2016 at 9:00 AM, Borislav Petkov wrote: > Fine with me as long as people don't start complaining if they start > testing my for-next branch and realize that the Arria10 support is not > complete. > > Unless they test linux-next where your tree is too, I assume. >

Re: [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

On Tue, Mar 29, 2016 at 9:00 AM, Borislav Petkov wrote: > Fine with me as long as people don't start complaining if they start > testing my for-next branch and realize that the Arria10 support is not > complete. > > Unless they test linux-next where your tree is too, I assume. > Yes, I take the

Re: [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

Hi Boris, On Tue, Mar 29, 2016 at 3:45 AM, Borislav Petkov wrote: > On Mon, Mar 21, 2016 at 11:01:46AM -0500, ttha...@opensource.altera.com wrote: >> From: Thor Thayer >> >> Add the device tree entries needed to support the Altera L2 >> cache EDAC

Re: [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

Hi Boris, On Tue, Mar 29, 2016 at 3:45 AM, Borislav Petkov wrote: > On Mon, Mar 21, 2016 at 11:01:46AM -0500, ttha...@opensource.altera.com wrote: >> From: Thor Thayer >> >> Add the device tree entries needed to support the Altera L2 >> cache EDAC on the Arria10 chip. >> >> Signed-off-by: Thor

Re: [PATCH v3 0/8] arm64: rockchip: Initial GeekBox enablement

On Thu, Mar 10, 2016 at 3:13 AM, Giuseppe CAVALLARO <peppe.cavall...@st.com> wrote: > On 3/9/2016 5:31 PM, Dinh Nguyen wrote: >> >> On Wed, Mar 9, 2016 at 8:53 AM, Giuseppe CAVALLARO >> <peppe.cavall...@st.com> wrote: >>> >>> Hi Tomeu, Dinh, A

Re: [PATCH v3 0/8] arm64: rockchip: Initial GeekBox enablement

On Thu, Mar 10, 2016 at 3:13 AM, Giuseppe CAVALLARO wrote: > On 3/9/2016 5:31 PM, Dinh Nguyen wrote: >> >> On Wed, Mar 9, 2016 at 8:53 AM, Giuseppe CAVALLARO >> wrote: >>> >>> Hi Tomeu, Dinh, Andreas >>> >>> I need a sum and help from y

Re: [PATCH v3 0/8] arm64: rockchip: Initial GeekBox enablement

On Wed, Mar 9, 2016 at 8:53 AM, Giuseppe CAVALLARO wrote: > Hi Tomeu, Dinh, Andreas > > I need a sum and help from you to go ahead on the > tx timeout. > > The "stmmac: MDIO fixes" seems to be the candidate to > fix the phy connection and I will send the V2 asap (Andreas'

Re: [PATCH v3 0/8] arm64: rockchip: Initial GeekBox enablement

On Wed, Mar 9, 2016 at 8:53 AM, Giuseppe CAVALLARO wrote: > Hi Tomeu, Dinh, Andreas > > I need a sum and help from you to go ahead on the > tx timeout. > > The "stmmac: MDIO fixes" seems to be the candidate to > fix the phy connection and I will send the V2 asap (Andreas' comment). > > So,

Re: [PATCH] ARM: socfpga: dts: Add missing clock and interrupt fields for Arria10 DMA

On Tue, 8 Mar 2016, Graham Moore wrote: > The PL330 DMA driver will not load on Arria10 without devicetree entries > for clocks and clock_names. This patch adds those entries. It also adds > the ninth interrupt, which is required for error detection. > > Signed-off-by: Graham Moore

Re: [PATCH] ARM: socfpga: dts: Add missing clock and interrupt fields for Arria10 DMA

On Tue, 8 Mar 2016, Graham Moore wrote: > The PL330 DMA driver will not load on Arria10 without devicetree entries > for clocks and clock_names. This patch adds those entries. It also adds > the ninth interrupt, which is required for error detection. > > Signed-off-by: Graham Moore > --- >

Re: [PATCHv2 11/11] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree entries needed to support the Altera L2 > cache EDAC on the Arria10 chip. > > Signed-off-by: Thor Thayer > --- > v2 Match

Re: [PATCHv2 11/11] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree entries needed to support the Altera L2 > cache EDAC on the Arria10 chip. > > Signed-off-by: Thor Thayer > --- > v2 Match register value (l2-ecc@ffd06010) > --- >

Re: [PATCHv2 10/11] ARM: socfpga: Enable Arria10 L2 cache ECC on startup

1 + > arch/arm/mach-socfpga/l2_cache.c | 49 > ++ > arch/arm/mach-socfpga/socfpga.c | 10 +++- > 3 files changed, 59 insertions(+), 1 deletion(-) > Acked-by: Dinh Nguyen <dingu...@opensource.altera.com> Thanks, Dinh

Re: [PATCHv2 10/11] ARM: socfpga: Enable Arria10 L2 cache ECC on startup

socfpga/socfpga.c | 10 +++- > 3 files changed, 59 insertions(+), 1 deletion(-) > Acked-by: Dinh Nguyen Thanks, Dinh

Re: [PATCH 4/5] ARM: socfpga: Enable Arria10 L2 cache ECC on startup

On Tue, 1 Mar 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be > enabled before data is stored in memory otherwise the ECC will fail > on reads. > > Signed-off-by: Thor Thayer

Re: [PATCH 4/5] ARM: socfpga: Enable Arria10 L2 cache ECC on startup

On Tue, 1 Mar 2016, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be > enabled before data is stored in memory otherwise the ECC will fail > on reads. > > Signed-off-by: Thor Thayer > --- >

Re: [PATCH v2] dts: add specific compatible type for Terasic DE0-NANO-SoC Board

On 02/25/2016 05:34 PM, Tim Sander wrote: > As far as i remember there are different de0 and different sockit boards, so > the name does not seem to be as concise? I don't care but i would say that > de0-nano-soc is the most concise and easier to search for than atlas which > might turn up more

Re: [PATCH v2] dts: add specific compatible type for Terasic DE0-NANO-SoC Board

On 02/25/2016 05:34 PM, Tim Sander wrote: > As far as i remember there are different de0 and different sockit boards, so > the name does not seem to be as concise? I don't care but i would say that > de0-nano-soc is the most concise and easier to search for than atlas which > might turn up more

Re: [PATCH v2] dts: add specific compatible type for Terasic DE0-NANO-SoC Board

On 02/25/2016 04:38 AM, Steffen Trumtrar wrote: > Hi Tim! > > On Thu, Feb 25, 2016 at 11:05:05AM +0100, Tim Sander wrote: >> From: Tim Sander >> >> Add a more specific compatible string:"terasic,de0-nano-soc" for respective >> board. >> Background: when checking for

Re: [PATCH v2] dts: add specific compatible type for Terasic DE0-NANO-SoC Board

On 02/25/2016 04:38 AM, Steffen Trumtrar wrote: > Hi Tim! > > On Thu, Feb 25, 2016 at 11:05:05AM +0100, Tim Sander wrote: >> From: Tim Sander >> >> Add a more specific compatible string:"terasic,de0-nano-soc" for respective >> board. >> Background: when checking for bootspec entries, some board

Re: [PATCH] dmaengine: pl330: fix to support the brust mode

urst s/maxbrust/maxburst > Fixes: commit 848e977 > "dmaengine: pl330: support burst mode for dev-to-mem and mem-to-dev transmit" > > Reported-by: Dinh Nguyen <dingu...@opensource.altera.com> > Signed-off-by: Caesar Wang <w...@rock-chips.com> >

Re: [PATCH] dmaengine: pl330: fix to support the brust mode

/maxbrust/burst > Fixes: commit 848e977 > "dmaengine: pl330: support burst mode for dev-to-mem and mem-to-dev transmit" > > Reported-by: Dinh Nguyen <dingu...@opensource.altera.com> > Signed-off-by: Caesar Wang <w...@rock-chips.com> > --- Tested on SoCFPGA:

Re: [PATCH] dmaengine: pl330: fix to support the brust mode

urst s/maxbrust/maxburst > Fixes: commit 848e977 > "dmaengine: pl330: support burst mode for dev-to-mem and mem-to-dev transmit" > > Reported-by: Dinh Nguyen > Signed-off-by: Caesar Wang > --- Tested on SoCFPGA: Tested-by: Dinh Nguyen Thanks, Dinh

Re: [PATCH] dmaengine: pl330: fix to support the brust mode

/maxbrust/burst > Fixes: commit 848e977 > "dmaengine: pl330: support burst mode for dev-to-mem and mem-to-dev transmit" > > Reported-by: Dinh Nguyen > Signed-off-by: Caesar Wang > --- Tested on SoCFPGA: Tested-by: Dinh Nguyen Thanks, Dinh

Re: [PATCH] dts: add specific compatible type for Terasic DE0-NANO-SoC Board

Hi Tim, On Fri, 12 Feb 2016, Tim Sander wrote: > From: Tim Sander > > Add a more specific compatible string:"terasic,de0-nano-soc" for respective > board. > Background: when checking for bootspec entries, some board specific fixups > are not

Re: [PATCH] dts: add specific compatible type for Terasic DE0-NANO-SoC Board

Hi Tim, On Fri, 12 Feb 2016, Tim Sander wrote: > From: Tim Sander > > Add a more specific compatible string:"terasic,de0-nano-soc" for respective > board. > Background: when checking for bootspec entries, some board specific fixups > are not apropriate for board of

Re: [PATCH] ARM: socfpga: hide unused functions

return 1; > } > +#endif > > static const struct smp_operations socfpga_smp_ops __initconst = { > .smp_prepare_cpus = socfpga_smp_prepare_cpus, > Acked-by: Dinh Nguyen <dingu...@opensource.altera.com> Dinh

Re: [PATCH] ARM: socfpga: hide unused functions

eturn 1; > } > +#endif > > static const struct smp_operations socfpga_smp_ops __initconst = { > .smp_prepare_cpus = socfpga_smp_prepare_cpus, > Acked-by: Dinh Nguyen Dinh

Re: commit 271e1b86e691 is breaking DMA uart on SoCFPGA

Hi, Sorry that I couldn't get to this sooner. On 02/18/2016 10:07 AM, Alexander Kochetkov wrote: > Hello! > > Bartlomiej, could you please tell what uart driver is used on Samsung > Exynos4412? > Dinh, could you please tell what uart driver is used on SoCFPGA? > SoCFPGA is using the 8250_dw.c

Re: commit 271e1b86e691 is breaking DMA uart on SoCFPGA

Hi, Sorry that I couldn't get to this sooner. On 02/18/2016 10:07 AM, Alexander Kochetkov wrote: > Hello! > > Bartlomiej, could you please tell what uart driver is used on Samsung > Exynos4412? > Dinh, could you please tell what uart driver is used on SoCFPGA? > SoCFPGA is using the 8250_dw.c

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

On 02/22/2016 03:50 PM, Stephen Boyd wrote: > > Oops, spoke too soon: > > drivers/clk/socfpga/clk-periph-a10.c:113:27: warning: incorrect type in > assignment (different base types) > drivers/clk/socfpga/clk-periph-a10.c:113:27:expected char const *const > *[assigned] parent_names >

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

On 02/22/2016 03:50 PM, Stephen Boyd wrote: > > Oops, spoke too soon: > > drivers/clk/socfpga/clk-periph-a10.c:113:27: warning: incorrect type in > assignment (different base types) > drivers/clk/socfpga/clk-periph-a10.c:113:27:expected char const *const > *[assigned] parent_names >

commit 271e1b86e691 is breaking DMA uart on SoCFPGA

Hi Vinod, It appears that commit 271e1b86e691 "dmaengine: pl330: add quirk for broken no flushp" is breaking uart dma on SoCFPGA. This commit is in linux-next(next-20160210). Doing a bisect pointed to commit 271e1b86e691, but I had to also revert the following commits (86a8ce7d4103 "dmaengine:

commit 271e1b86e691 is breaking DMA uart on SoCFPGA

Hi Vinod, It appears that commit 271e1b86e691 "dmaengine: pl330: add quirk for broken no flushp" is breaking uart dma on SoCFPGA. This commit is in linux-next(next-20160210). Doing a bisect pointed to commit 271e1b86e691, but I had to also revert the following commits (86a8ce7d4103 "dmaengine:

Re: commit 5146e0b05963 is causing a kernel crash on SoCFPGA

Hi Masahiro, On 02/08/2016 10:00 PM, Masahiro Yamada wrote: > Hi Dinh, > > Thanks for your report. > > > 2016-02-09 11:35 GMT+09:00 Dinh Nguyen : >> Hi Stephen, >> >> It appears that commit 5146e0b05966 "clk: simplify __clk_init_parent()"

Re: commit 5146e0b05963 is causing a kernel crash on SoCFPGA

Hi Masahiro, On 02/08/2016 10:00 PM, Masahiro Yamada wrote: > Hi Dinh, > > Thanks for your report. > > > 2016-02-09 11:35 GMT+09:00 Dinh Nguyen <dingu...@kernel.org>: >> Hi Stephen, >> >> It appears that commit 5146e0b05966 "clk: simplify __clk_in

commit 5146e0b05963 is causing a kernel crash on SoCFPGA

Hi Stephen, It appears that commit 5146e0b05966 "clk: simplify __clk_init_parent()" that is currently in linux-next is causing the following kernel crash on SoCFGPA[1]. I have bisected to this commit and doing a revert of the commit fixes the issue. Dinh [1] Linux version

Re: [PATCHv9 4/4] ARM: socfpga: Enable OCRAM ECC on startup

+ > arch/arm/mach-socfpga/socfpga.c |3 +++ > 4 files changed, 54 insertions(+) > create mode 100644 arch/arm/mach-socfpga/ocram.c > Acked-by: Dinh Nguyen

Re: [PATCHv9 3/4] ARM: socfpga: enable L2 cache ECC on startup

r in header. > --- > arch/arm/mach-socfpga/Makefile |1 + > arch/arm/mach-socfpga/core.h |1 + > arch/arm/mach-socfpga/l2_cache.c | 41 > ++ > arch/arm/mach-socfpga/socfpga.c |2 ++ > 4 files changed, 45 insertions(+) > cre

commit 5146e0b05963 is causing a kernel crash on SoCFPGA

Hi Stephen, It appears that commit 5146e0b05966 "clk: simplify __clk_init_parent()" that is currently in linux-next is causing the following kernel crash on SoCFGPA[1]. I have bisected to this commit and doing a revert of the commit fixes the issue. Dinh [1] Linux version

Re: [PATCHv9 4/4] ARM: socfpga: Enable OCRAM ECC on startup

cfpga/core.h|1 + > arch/arm/mach-socfpga/ocram.c | 49 > +++ > arch/arm/mach-socfpga/socfpga.c |3 +++ > 4 files changed, 54 insertions(+) > create mode 100644 arch/arm/mach-socfpga/ocram.c > Acked-by: Dinh Nguyen <dingu...@opensource.altera.com>

Re: [PATCHv9 3/4] ARM: socfpga: enable L2 cache ECC on startup

cfpga/socfpga.c |2 ++ > 4 files changed, 45 insertions(+) > create mode 100644 arch/arm/mach-socfpga/l2_cache.c > Acked-by: Dinh Nguyen <dingu...@opensource.altera.com>

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/04/2016 02:59 PM, Borislav Petkov wrote: > On Mon, Jan 04, 2016 at 02:46:26PM -0600, Dinh Nguyen wrote: >> I don't see a way for the xgene to manually build for each configuration >> using Kconfig? For SoCFGPA, we would like to keep the option to build >> for each ty

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/04/2016 02:30 PM, Borislav Petkov wrote: > On Mon, Jan 04, 2016 at 02:04:08PM -0600, Dinh Nguyen wrote: >> altr_edac.c originally added support for SDRAM. Now we're adding support >> for L2 and OCRAM into the same file by using #ifdef >> CONFIG_EDAC_ALTERA_OCRAM and C

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/04/2016 01:46 PM, Borislav Petkov wrote: > On Mon, Jan 04, 2016 at 11:17:29AM -0600, Dinh Nguyen wrote: >> We tried to jam the L2 and OCRAM EDAC functionality in the same >> altr_edac.c file. It looks like it might be clean if we split out the L2 >> and OCRAM functions i

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

a faster boot time. >> 2) the SDRAM has an ECC initialization dependency on the preloader >> which is outside the kernel. It is desirable to be able to turn the >> SDRAM on & off separately. >> >> Signed-off-by: Thor Thayer >> Signed-off-by: Dinh Nguyen >

Re: commit e34d65696d2e broke stmmac ethernet on socfpga

On 01/01/2016 02:49 AM, Romain Perier wrote: > Hi all, > > Same here on rockchip. > See "[PATCH] stmmac: Don't exit mdio registration when mdio subnode is > not found in the DTS" > > Regards, > Romain > > 2015-12-18 18:45 GMT+01:00 Dinh Nguyen : >>

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/04/2016 02:30 PM, Borislav Petkov wrote: > On Mon, Jan 04, 2016 at 02:04:08PM -0600, Dinh Nguyen wrote: >> altr_edac.c originally added support for SDRAM. Now we're adding support >> for L2 and OCRAM into the same file by using #ifdef >> CONFIG_EDAC_ALTERA_OCRAM and C

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/04/2016 02:59 PM, Borislav Petkov wrote: > On Mon, Jan 04, 2016 at 02:46:26PM -0600, Dinh Nguyen wrote: >> I don't see a way for the xgene to manually build for each configuration >> using Kconfig? For SoCFGPA, we would like to keep the option to build >> for each ty

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

On 01/04/2016 01:46 PM, Borislav Petkov wrote: > On Mon, Jan 04, 2016 at 11:17:29AM -0600, Dinh Nguyen wrote: >> We tried to jam the L2 and OCRAM EDAC functionality in the same >> altr_edac.c file. It looks like it might be clean if we split out the L2 >> and OCRAM functions i

Re: commit e34d65696d2e broke stmmac ethernet on socfpga

On 01/01/2016 02:49 AM, Romain Perier wrote: > Hi all, > > Same here on rockchip. > See "[PATCH] stmmac: Don't exit mdio registration when mdio subnode is > not found in the DTS" > > Regards, > Romain > > 2015-12-18 18:45 GMT+01:00 Dinh Nguyen

Re: [PATCHv7] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

nd some >> customers need a faster boot time. >> 2) the SDRAM has an ECC initialization dependency on the preloader >> which is outside the kernel. It is desirable to be able to turn the >> SDRAM on & off separately. >> >> Signed-off-by: Thor Thaye

commit e34d65696d2e broke stmmac ethernet on socfpga

Hi, It appears that commit e34d65696d2e 'stmmac: create of compatible mdio bus for stmmac driver' is causing this error on the SoCFPGA platform: [1.767246] libphy: PHY stmmac-0: not found [1.772106] eth0: Could not attach to PHY [1.776129] stmmac_open: Cannot attach to PHY

commit e34d65696d2e broke stmmac ethernet on socfpga

Hi, It appears that commit e34d65696d2e 'stmmac: create of compatible mdio bus for stmmac driver' is causing this error on the SoCFPGA platform: [1.767246] libphy: PHY stmmac-0: not found [1.772106] eth0: Could not attach to PHY [1.776129] stmmac_open: Cannot attach to PHY

Re: [PATCH v5 01/58] mtd: nand: denali: add missing nand_release() call in denali_remove()

On Fri, Dec 11, 2015 at 11:08 AM, Boris Brezillon wrote: > Hi Dinh, > > On Fri, 11 Dec 2015 10:50:21 -0600 > Dinh Nguyen wrote: > >> Hi Boris, >> >> On Fri, Dec 11, 2015 at 9:10 AM, Boris Brezillon >> wrote: >> > + Dinh (who made commit 2a0a2

Re: [PATCH v5 01/58] mtd: nand: denali: add missing nand_release() call in denali_remove()

Hi Boris, On Fri, Dec 11, 2015 at 9:10 AM, Boris Brezillon wrote: > + Dinh (who made commit 2a0a288ec258) > > Also added back the Fixes tag. > > On Fri, 11 Dec 2015 15:02:34 +0100 > Boris Brezillon wrote: > >> Unregister the NAND device from the NAND subsystem when removing a denali >> NAND

Re: [PATCH] MAINTAINERS: Add missing platform maintainers for dts files

arch/arm64/boot/dts/altera/ > W: http://www.rocketboards.org > T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git Acked-by: Dinh Nguyen Thanks, Dinh -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger

Re: [PATCH v5 01/58] mtd: nand: denali: add missing nand_release() call in denali_remove()

Hi Boris, On Fri, Dec 11, 2015 at 9:10 AM, Boris Brezillon wrote: > + Dinh (who made commit 2a0a288ec258) > > Also added back the Fixes tag. > > On Fri, 11 Dec 2015 15:02:34 +0100 > Boris Brezillon wrote: > >> Unregister

Re: [PATCH] MAINTAINERS: Add missing platform maintainers for dts files

; +F: arch/arm64/boot/dts/altera/ > W: http://www.rocketboards.org > T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git Acked-by: Dinh Nguyen <dingu...@opensource.altera.com> Thanks, Dinh -- To unsubscribe from this list: send the line "unsubscribe li

Re: [PATCH v5 01/58] mtd: nand: denali: add missing nand_release() call in denali_remove()

On Fri, Dec 11, 2015 at 11:08 AM, Boris Brezillon <boris.brezil...@free-electrons.com> wrote: > Hi Dinh, > > On Fri, 11 Dec 2015 10:50:21 -0600 > Dinh Nguyen <dinh.li...@gmail.com> wrote: > >> Hi Boris, >> >> On Fri, Dec 11, 2015 at 9:10 AM, Boris Bre

Re: [PATCH] ARM: socfpga: dts: Add NAND device tree for Altera Arria10

reg = <0xffb9 0x72000>, <0xffb8 0x1>; > + reg-names = "nand_data", "denali_reg"; > + interrupts = <0 99 4>; > + dma-mask = <0x>; > + clocks = <_clk>

Re: [PATCH] ARM: socfpga: dts: Add NAND device tree for Altera Arria10

+ reg = <0xffb9 0x72000>, <0xffb8 0x1>; > + reg-names = "nand_data", "denali_reg"; > + interrupts = <0 99 4>; > + dma-mask = <0xffff>; > +

Re: SoCFPGA ethernet broken

Hi Andrew, On Fri, 4 Dec 2015, Andrew Lunn wrote: > On Fri, Dec 04, 2015 at 02:10:50AM +0100, Andrew Lunn wrote: > > > > FWIW: My initial patch to address the failure worked with the original > > > > DTB. > > > > > > Can I ask what patch are you referring to? I was sidetracked for a while > >

Re: SoCFPGA ethernet broken

Hi Andrew, On Fri, 4 Dec 2015, Andrew Lunn wrote: > On Fri, Dec 04, 2015 at 02:10:50AM +0100, Andrew Lunn wrote: > > > > FWIW: My initial patch to address the failure worked with the original > > > > DTB. > > > > > > Can I ask what patch are you referring to? I was sidetracked for a while > >

Re: SoCFPGA ethernet broken

On 12/03/2015 03:23 PM, David Daney wrote: > On 12/03/2015 12:48 PM, Pavel Machek wrote: >> On Thu 2015-10-15 13:25:59, Florian Fainelli wrote: >>> On 15/10/15 12:59, Dinh Nguyen wrote: >>>> On 10/15/2015 03:03 PM, Florian Fainelli wrote: >>>>> On

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