Re: SoCFPGA ethernet broken

On 12/03/2015 03:23 PM, David Daney wrote: > On 12/03/2015 12:48 PM, Pavel Machek wrote: >> On Thu 2015-10-15 13:25:59, Florian Fainelli wrote: >>> On 15/10/15 12:59, Dinh Nguyen wrote: >>>> On 10/15/2015 03:03 PM, Florian Fainelli wrote: >>>>> On

Re: Denali NAND driver on SocKit

CC: Graham Moore Graham should know more about this. Dinh On 11/30/2015 12:31 PM, Pavel Machek wrote: > Hi! > > I'm trying to get NAND to work on socdk board... but it looks like > neccessary device tree bindings are not there. And when I do add them, > they don't seem to work. > > Does it

Re: Denali NAND driver on SocKit

CC: Graham Moore Graham should know more about this. Dinh On 11/30/2015 12:31 PM, Pavel Machek wrote: > Hi! > > I'm trying to get NAND to work on socdk board... but it looks like > neccessary device tree bindings are not there. And when I do add them, > they don't seem to work. > > Does it

Re: SoCFPGA ethernet broken

+CC Giuseppe Cavallaro +CC STi and Rockchip Maintainers This is approaching beyond my breadth of knowledge on this subject, so I just wanted to get some further insight. On Fri, 16 Oct 2015, Andrew Lunn wrote: > > > Maybe we need to walk up the hierarchy. > > > > > > Perhaps something like: >

Re: SoCFPGA ethernet broken

On Mon, 19 Oct 2015, Dinh Nguyen wrote: +CC Giuseppe Cavallaro +CC STi and Rockchip Maintainers This is approaching beyond my breadth of knowledge on this subject, so I just wanted to get some further insight. > > On Fri, 16 Oct 2015, Andrew Lunn wrote: > > > > > May

Re: SoCFPGA ethernet broken

On Mon, 19 Oct 2015, Dinh Nguyen wrote: +CC Giuseppe Cavallaro +CC STi and Rockchip Maintainers This is approaching beyond my breadth of knowledge on this subject, so I just wanted to get some further insight. > > On Fri, 16 Oct 2015, Andrew Lunn wrote: > > > > > May

Re: SoCFPGA ethernet broken

+CC Giuseppe Cavallaro +CC STi and Rockchip Maintainers This is approaching beyond my breadth of knowledge on this subject, so I just wanted to get some further insight. On Fri, 16 Oct 2015, Andrew Lunn wrote: > > > Maybe we need to walk up the hierarchy. > > > > > > Perhaps something like: >

Re: SoCFPGA ethernet broken

On Fri, 16 Oct 2015, David Daney wrote: > On 10/16/2015 08:56 AM, Andrew Lunn wrote: > > > So I think I'll move to inspect what Florian had suggested, and that was > > > to look > > > at: > > > drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c::stmmac_mdio_register > > > > I have a suspicion. If

Re: SoCFPGA ethernet broken

On Fri, 16 Oct 2015, Andrew Lunn wrote: > On Fri, Oct 16, 2015 at 09:38:37AM -0500, Dinh Nguyen wrote: > > On Fri, 16 Oct 2015, Andrew Lunn wrote: > > > > > > Another debugging point, the SoCFPGA board has a Micrel ksz9021 PHY > > > > attached > &

Re: SoCFPGA ethernet broken

On Fri, 16 Oct 2015, Andrew Lunn wrote: > > Another debugging point, the SoCFPGA board has a Micrel ksz9021 PHY attached > > to the ethernet port. What I'm seeing is that with 8b63ec1837fa patch, when > > the call to ksz9021_config_init() is made both of_node and > > dev->parent->of_node > > are

Re: SoCFPGA ethernet broken

On Fri, 16 Oct 2015, David Daney wrote: > On 10/16/2015 08:56 AM, Andrew Lunn wrote: > > > So I think I'll move to inspect what Florian had suggested, and that was > > > to look > > > at: > > > drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c::stmmac_mdio_register > > > > I have a suspicion. If

Re: SoCFPGA ethernet broken

On Fri, 16 Oct 2015, Andrew Lunn wrote: > On Fri, Oct 16, 2015 at 09:38:37AM -0500, Dinh Nguyen wrote: > > On Fri, 16 Oct 2015, Andrew Lunn wrote: > > > > > > Another debugging point, the SoCFPGA board has a Micrel ksz9021 PHY > > > > attached > &

Re: SoCFPGA ethernet broken

On Fri, 16 Oct 2015, Andrew Lunn wrote: > > Another debugging point, the SoCFPGA board has a Micrel ksz9021 PHY attached > > to the ethernet port. What I'm seeing is that with 8b63ec1837fa patch, when > > the call to ksz9021_config_init() is made both of_node and > > dev->parent->of_node > > are

Re: SoCFPGA ethernet broken

On Thu, 15 Oct 2015, Florian Fainelli wrote: > On 15/10/15 13:49, Dinh Nguyen wrote: > >> > >> Does this text change with and without the 8b63ec1837fa patch? > > > > No, this text does not change with/without the 8b63ec1837fa patch. > > Could you in

Re: SoCFPGA ethernet broken

On Thu, 15 Oct 2015, Florian Fainelli wrote: > On 15/10/15 13:49, Dinh Nguyen wrote: > >> > >> Does this text change with and without the 8b63ec1837fa patch? > > > > No, this text does not change with/without the 8b63ec1837fa patch. > > Could you in

Re: SoCFPGA ethernet broken

On 10/15/2015 03:35 PM, David Daney wrote: > On 10/15/2015 01:25 PM, Florian Fainelli wrote: >> On 15/10/15 12:59, Dinh Nguyen wrote: >>> On 10/15/2015 03:03 PM, Florian Fainelli wrote: >>>> On 15/10/15 12:09, Dinh Nguyen wrote: >>>>> Hi, >>>&g

Re: SoCFPGA ethernet broken

On 10/15/2015 03:03 PM, Florian Fainelli wrote: > On 15/10/15 12:09, Dinh Nguyen wrote: >> Hi, >> >> commit "8b63ec1837fa phylib: Make PHYs children of their MDIO bus, not >> the bus' parent." seems to have broken ethernet support for the SoCFPGA >>

SoCFPGA ethernet broken

Hi, commit "8b63ec1837fa phylib: Make PHYs children of their MDIO bus, not the bus' parent." seems to have broken ethernet support for the SoCFPGA platform which is using the stmmac ethernet driver. It appears that during DHCP, it cannot get an IP address. This only happens if ethernet was not

Re: SoCFPGA ethernet broken

On Thu, 15 Oct 2015, Florian Fainelli wrote: > On 15/10/15 13:49, Dinh Nguyen wrote: > >> > >> Does this text change with and without the 8b63ec1837fa patch? > > > > No, this text does not change with/without the 8b63ec1837fa patch. > > Could you in

Re: SoCFPGA ethernet broken

On Thu, 15 Oct 2015, Florian Fainelli wrote: > On 15/10/15 13:49, Dinh Nguyen wrote: > >> > >> Does this text change with and without the 8b63ec1837fa patch? > > > > No, this text does not change with/without the 8b63ec1837fa patch. > > Could you in

Re: SoCFPGA ethernet broken

On 10/15/2015 03:03 PM, Florian Fainelli wrote: > On 15/10/15 12:09, Dinh Nguyen wrote: >> Hi, >> >> commit "8b63ec1837fa phylib: Make PHYs children of their MDIO bus, not >> the bus' parent." seems to have broken ethernet support for the SoCFPGA >>

Re: SoCFPGA ethernet broken

On 10/15/2015 03:35 PM, David Daney wrote: > On 10/15/2015 01:25 PM, Florian Fainelli wrote: >> On 15/10/15 12:59, Dinh Nguyen wrote: >>> On 10/15/2015 03:03 PM, Florian Fainelli wrote: >>>> On 15/10/15 12:09, Dinh Nguyen wrote: >>>>> Hi, >>>&g

SoCFPGA ethernet broken

Hi, commit "8b63ec1837fa phylib: Make PHYs children of their MDIO bus, not the bus' parent." seems to have broken ethernet support for the SoCFPGA platform which is using the stmmac ethernet driver. It appears that during DHCP, it cannot get an IP address. This only happens if ethernet was not

Re: [PATCH v2] ARM: socfpga: dts: add fpga manager

On Tue, 13 Oct 2015, Steffen Trumtrar wrote: > On Tue, Oct 13, 2015 at 02:51:28PM -0500, Dinh Nguyen wrote: > > On Tue, 13 Oct 2015, at...@opensource.altera.com wrote: > > > > > From: Alan Tull > > > > > > Add FPGA manager to device tree for SoCF

Re: [PATCH v2] ARM: socfpga: dts: add fpga manager

On Tue, 13 Oct 2015, at...@opensource.altera.com wrote: > From: Alan Tull > > Add FPGA manager to device tree for SoCFPGA. > > Signed-off-by: Alan Tull > --- > v2: Remove 0x after @ > No caps in hex numbers > renamed hps_0_fpgamgr to fpgamgr0 > move node to be in alpha order by

Re: [PATCH] ARM: socfpga_defconfig: enable fpga manager

On Tue, 13 Oct 2015, at...@opensource.altera.com wrote: > From: Alan Tull > > Enable fpga manager framework and low level driver for > socfpga in socfpga_defconfig > > Signed-off-by: Alan Tull > --- > arch/arm/configs/socfpga_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > Applied!

Re: [PATCH] ARM: socfpga: dts: add fpga manager

On Tue, 13 Oct 2015, Steffen Trumtrar wrote: > Hi Alan! > > On Tue, Oct 13, 2015 at 01:28:20PM -0500, at...@opensource.altera.com wrote: > > From: Alan Tull > > > > Add FPGA manager to device tree for SoCFPGA. > > > > Signed-off-by: Alan Tull > > --- > > arch/arm/boot/dts/socfpga.dtsi | 7

Re: [PATCH v2] ARM: socfpga: dts: add fpga manager

On Tue, 13 Oct 2015, at...@opensource.altera.com wrote: > From: Alan Tull > > Add FPGA manager to device tree for SoCFPGA. > > Signed-off-by: Alan Tull > --- > v2: Remove 0x after @ > No caps in hex numbers > renamed

Re: [PATCH] ARM: socfpga: dts: add fpga manager

On Tue, 13 Oct 2015, Steffen Trumtrar wrote: > Hi Alan! > > On Tue, Oct 13, 2015 at 01:28:20PM -0500, at...@opensource.altera.com wrote: > > From: Alan Tull > > > > Add FPGA manager to device tree for SoCFPGA. > > > > Signed-off-by: Alan Tull

Re: [PATCH] ARM: socfpga_defconfig: enable fpga manager

On Tue, 13 Oct 2015, at...@opensource.altera.com wrote: > From: Alan Tull > > Enable fpga manager framework and low level driver for > socfpga in socfpga_defconfig > > Signed-off-by: Alan Tull > --- >

Re: [PATCH v2] ARM: socfpga: dts: add fpga manager

On Tue, 13 Oct 2015, Steffen Trumtrar wrote: > On Tue, Oct 13, 2015 at 02:51:28PM -0500, Dinh Nguyen wrote: > > On Tue, 13 Oct 2015, at...@opensource.altera.com wrote: > > > > > From: Alan Tull <at...@opensource.altera.com> > > > > >

Re: [PATCHv2] arm64: dts: Add base stratix 10 dtsi

On 08/20/2015 12:23 PM, Mark Rutland wrote: > Hi, > >> +/ { >> +compatible = "altr,socfpga-stratix10"; >> +#address-cells = <1>; >> +#size-cells = <1>; > > I would recommend that you make your root #address-cells and #size-cells equal > to 2, as that will simplify matters later

Re: [PATCHv2] arm64: dts: Add base stratix 10 dtsi

On 08/20/2015 12:23 PM, Mark Rutland wrote: Hi, +/ { +compatible = altr,socfpga-stratix10; +#address-cells = 1; +#size-cells = 1; I would recommend that you make your root #address-cells and #size-cells equal to 2, as that will simplify matters later if/when you need to add

Re: [PATCH v4 4/5] Documentation: dt-bindings: pci: altera pcie device tree binding

On Mon, Aug 17, 2015 at 4:09 AM, Ley Foon Tan wrote: > This patch adds the bindings for Altera PCIe host controller driver and > Altera PCIe MSI driver. > > Signed-off-by: Ley Foon Tan > --- > .../devicetree/bindings/pci/altera-pcie-msi.txt| 27 >

Re: [PATCH v4 2/5] pci:host: Add Altera PCIe host controller driver

On Mon, Aug 17, 2015 at 4:09 AM, Ley Foon Tan wrote: > This patch adds the Altera PCIe host controller driver. > > Signed-off-by: Ley Foon Tan > --- > drivers/pci/host/Kconfig | 7 + > drivers/pci/host/Makefile | 1 + > drivers/pci/host/pcie-altera.c | 543 >

Re: [PATCHv2] arm64: dts: Add base stratix 10 dtsi

On Tue, 11 Aug 2015, dingu...@opensource.altera.com wrote: > From: Dinh Nguyen > > Add the base DTS for Altera's SoCFPGA Stratix 10 platform. > > Signed-off-by: Dinh Nguyen > --- > v2: use interrupt-affinity for pmu node > --- > arch/arm64/Kconfig

Re: [PATCH v4 4/5] Documentation: dt-bindings: pci: altera pcie device tree binding

On Mon, Aug 17, 2015 at 4:09 AM, Ley Foon Tan lf...@altera.com wrote: This patch adds the bindings for Altera PCIe host controller driver and Altera PCIe MSI driver. Signed-off-by: Ley Foon Tan lf...@altera.com --- .../devicetree/bindings/pci/altera-pcie-msi.txt| 27

Re: [PATCH v4 2/5] pci:host: Add Altera PCIe host controller driver

On Mon, Aug 17, 2015 at 4:09 AM, Ley Foon Tan lf...@altera.com wrote: This patch adds the Altera PCIe host controller driver. Signed-off-by: Ley Foon Tan lf...@altera.com --- drivers/pci/host/Kconfig | 7 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-altera.c |

Re: [PATCHv2] arm64: dts: Add base stratix 10 dtsi

On Tue, 11 Aug 2015, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com --- v2: use interrupt-affinity for pmu node --- arch/arm64

Re: [PATCH] arm64: dts: Add base stratix 10 dtsi

Hi Jisheng, On 8/10/15 9:39 PM, Jisheng Zhang wrote: > On Mon, 10 Aug 2015 16:09:18 -0500 > wrote: > >> From: Dinh Nguyen >> >> Add the base DTS for Altera's SoCFPGA Stratix 10 platform. >> >> Signed-off-by: Dinh Nguyen >> --- >> arch/

Re: [PATCH] arm64: dts: Add base stratix 10 dtsi

Hi Jisheng, On 8/10/15 9:39 PM, Jisheng Zhang wrote: On Mon, 10 Aug 2015 16:09:18 -0500 dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com Add the base DTS for Altera's SoCFPGA Stratix 10 platform. Signed-off-by: Dinh Nguyen dingu

Re: [PATCH 4/6] pci: altera: Add Altera PCIe MSI driver

On Tue, Jul 28, 2015 at 10:07 PM, Ley Foon Tan wrote: > On Wed, Jul 29, 2015 at 1:00 AM, Dinh Nguyen wrote: >> On Tue, Jul 28, 2015 at 5:45 AM, Ley Foon Tan wrote: >>> This patch adds Altera PCIe MSI driver. This soft IP supports configurable >>> number of vector

Re: [PATCH 4/6] pci: altera: Add Altera PCIe MSI driver

On Tue, Jul 28, 2015 at 5:45 AM, Ley Foon Tan wrote: > This patch adds Altera PCIe MSI driver. This soft IP supports configurable > number of vectors, which is a dts parameter. > > Signed-off-by: Ley Foon Tan > --- > drivers/pci/host/Kconfig | 7 + > drivers/pci/host/Makefile

Re: [PATCH 3/6] pci:host: Add Altera PCIe host controller driver

On Tue, Jul 28, 2015 at 5:45 AM, Ley Foon Tan wrote: > This patch adds the Altera PCIe host controller driver. > > Signed-off-by: Ley Foon Tan > --- > drivers/pci/host/Kconfig | 9 + > drivers/pci/host/Makefile | 1 + > drivers/pci/host/pcie-altera.c | 576 >

Re: [PATCH 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

On 7/28/15 3:46 AM, Philipp Zabel wrote: > Am Montag, den 27.07.2015, 13:57 -0500 schrieb > dingu...@opensource.altera.com: >> From: Dinh Nguyen >> >> In order for the Arria10 to be able to re-use the reset driver for SoCFPGA >> Cyclone5/Arria5, we need to read the

Re: [PATCH 3/4] reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property

On 7/28/15 3:46 AM, Philipp Zabel wrote: Am Montag, den 27.07.2015, 13:57 -0500 schrieb dingu...@opensource.altera.com: From: Dinh Nguyen dingu...@opensource.altera.com In order for the Arria10 to be able to re-use the reset driver for SoCFPGA Cyclone5/Arria5, we need to read the 'altr

Re: [PATCH 4/6] pci: altera: Add Altera PCIe MSI driver

On Tue, Jul 28, 2015 at 10:07 PM, Ley Foon Tan lf...@altera.com wrote: On Wed, Jul 29, 2015 at 1:00 AM, Dinh Nguyen dinh.li...@gmail.com wrote: On Tue, Jul 28, 2015 at 5:45 AM, Ley Foon Tan lf...@altera.com wrote: This patch adds Altera PCIe MSI driver. This soft IP supports configurable

Re: [PATCH 3/6] pci:host: Add Altera PCIe host controller driver

On Tue, Jul 28, 2015 at 5:45 AM, Ley Foon Tan lf...@altera.com wrote: This patch adds the Altera PCIe host controller driver. Signed-off-by: Ley Foon Tan lf...@altera.com --- drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-altera.c |

Re: [PATCH 4/6] pci: altera: Add Altera PCIe MSI driver

On Tue, Jul 28, 2015 at 5:45 AM, Ley Foon Tan lf...@altera.com wrote: This patch adds Altera PCIe MSI driver. This soft IP supports configurable number of vectors, which is a dts parameter. Signed-off-by: Ley Foon Tan lf...@altera.com --- drivers/pci/host/Kconfig | 7 +

Re: [PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk

On 7/24/15 4:41 PM, Stephen Boyd wrote: > On 07/22, dingu...@opensource.altera.com wrote: >> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi >> index 80f924d..7d5db54 100644 >> --- a/arch/arm/boot/dts/socfpga.dtsi >> +++ b/arch/arm/boot/dts/socfpga.dtsi >> @@ -164,7

Re: [PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk

On 7/24/15 4:41 PM, Stephen Boyd wrote: On 07/22, dingu...@opensource.altera.com wrote: diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 80f924d..7d5db54 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -164,7 +164,7 @@

Re: [PATCHv2 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

On Tue, 21 Jul 2015, Tyler Baker wrote: > Hi, > > On 17 July 2015 at 17:53, Stephen Boyd wrote: > > On 07/06, dingu...@opensource.altera.com wrote: > >> From: Dinh Nguyen > >> > >> Use of_clk_parent_fill to fill in the parent clock names' array. >

Re: [PATCHv2 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

On Tue, 21 Jul 2015, Tyler Baker wrote: Hi, On 17 July 2015 at 17:53, Stephen Boyd sb...@codeaurora.org wrote: On 07/06, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed

Re: [PATCH 24/45] clk: socfpga: Remove clk.h and clkdev.h includes

things keep compiling. > > Cc: Dinh Nguyen > Signed-off-by: Stephen Boyd > --- > drivers/clk/socfpga/clk-gate-a10.c | 1 + > drivers/clk/socfpga/clk-gate.c | 3 +-- > drivers/clk/socfpga/clk-periph-a10.c | 1 + > drivers/clk/socfpga/clk-periph.c | 3 +-- > d

Re: [PATCH v5 3/8] clk: socfpga: switch to GENMASK()

fpga/clk-periph-a10.c | 2 +- > drivers/clk/socfpga/clk-periph.c | 2 +- > drivers/clk/socfpga/clk.h| 1 - > 5 files changed, 4 insertions(+), 5 deletions(-) > Acked-by: Dinh Nguyen Thanks, Dinh -- To unsubscribe from this list: send the line "unsubscribe

Re: [PATCH 24/45] clk: socfpga: Remove clk.h and clkdev.h includes

. Cc: Dinh Nguyen dingu...@opensource.altera.com Signed-off-by: Stephen Boyd sb...@codeaurora.org --- drivers/clk/socfpga/clk-gate-a10.c | 1 + drivers/clk/socfpga/clk-gate.c | 3 +-- drivers/clk/socfpga/clk-periph-a10.c | 1 + drivers/clk/socfpga/clk-periph.c | 3 +-- drivers

Re: [PATCH v5 3/8] clk: socfpga: switch to GENMASK()

/socfpga/clk-periph-a10.c | 2 +- drivers/clk/socfpga/clk-periph.c | 2 +- drivers/clk/socfpga/clk.h| 1 - 5 files changed, 4 insertions(+), 5 deletions(-) Acked-by: Dinh Nguyen dingu...@opensource.altera.com Thanks, Dinh -- To unsubscribe from this list: send the line

Re: [PATCH v4 3/6] clk: socfpga: switch to GENMASK()

Hi Andy, On 07/09/2015 11:43 AM, Andy Shevchenko wrote: > Convert the code to use GENMASK() helper instead of div_mask() macro. > > Signed-off-by: Andy Shevchenko > --- > drivers/clk/socfpga/clk-gate.c | 2 +- > drivers/clk/socfpga/clk-periph.c | 2 +- > drivers/clk/socfpga/clk.h| 1

Re: [PATCH v4 3/6] clk: socfpga: switch to GENMASK()

Hi Andy, On 07/09/2015 11:43 AM, Andy Shevchenko wrote: Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by: Andy Shevchenko andriy.shevche...@linux.intel.com --- drivers/clk/socfpga/clk-gate.c | 2 +- drivers/clk/socfpga/clk-periph.c | 2 +-

Re: [PATCH 1/3] ARM: socfpga: dts: Fix adxl34x formating

On 6/26/15 5:36 AM, Walter Lozano wrote: > Hi Steffen > > On Fri, Jun 26, 2015 at 4:16 AM, Steffen Trumtrar > wrote: >> Hi Walter! >> >> On Thu, Jun 25, 2015 at 11:25:57PM -0300, Walter Lozano wrote: >>> This patch fixes the formating of DTS bindings for the adxl34x digital >>> accelerometer.

Re: [PATCH 1/3] ARM: socfpga: dts: Fix adxl34x formating

On 6/26/15 5:36 AM, Walter Lozano wrote: Hi Steffen On Fri, Jun 26, 2015 at 4:16 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote: Hi Walter! On Thu, Jun 25, 2015 at 11:25:57PM -0300, Walter Lozano wrote: This patch fixes the formating of DTS bindings for the adxl34x digital

Re: [PATCH v2] ARM: socfpga: dts: Add adxl34x

On 6/25/15 12:01 PM, Walter Lozano wrote: > On Thu, Jun 25, 2015 at 4:28 AM, Geert Uytterhoeven > wrote: >> On Tue, Jun 23, 2015 at 10:20 PM, Walter Lozano >> wrote: >>> On Mon, Mar 23, 2015 at 11:29 PM, Walter Lozano >>> wrote: >>>> On Mon, M

Re: [PATCH v2] ARM: socfpga: dts: Add adxl34x

: On Mon, Mar 23, 2015 at 12:03 AM, Dinh Nguyen dingu...@opensource.altera.com wrote: On 3/19/15 4:27 PM, Walter Lozano wrote: On Mon, Mar 16, 2015 at 10:10 AM, Walter Lozano wal...@vanguardiasur.com.ar wrote: On Mon, Jan 5, 2015 at 6:21 AM, Steffen Trumtrar s.trumt...@pengutronix.de wrote

Re: [PATCH 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

On 06/11/2015 04:06 AM, Maxime Ripard wrote: > Hi Dinh, > > On Wed, Jun 10, 2015 at 04:49:24PM -0500, dingu...@opensource.altera.com > wrote: >> From: Dinh Nguyen >> >> Use of_clk_parent_fill to fill in the parent clock names' array. >> >> Signed-off-by

Re: [PATCH 5/6] clk: sunxi: make use of of_clk_parent_fill helper function

On 06/11/2015 04:06 AM, Maxime Ripard wrote: Hi Dinh, On Wed, Jun 10, 2015 at 04:49:24PM -0500, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen dingu

Re: [PATCH v2] ARM: socfpga: add smp_ops.cpu_kill to make kexec/kdump available

> > Signed-off-by: Hiraku Toyooka > Cc: Dinh Nguyen > Cc: Russell King > Cc: linux-arm-ker...@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > arch/arm/mach-socfpga/platsmp.c | 12 > 1 file changed, 12 insertions(+) > Applied! Than

Re: [PATCH v2] ARM: socfpga: add smp_ops.cpu_kill to make kexec/kdump available

-by: Hiraku Toyooka hiraku.toyooka...@hitachi.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Russell King li...@arm.linux.org.uk Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm/mach-socfpga/platsmp.c | 12 1 file changed, 12

Re: [RFC/PATCHv2 1/2] clk: of: helper for filling parent clock array and return num of parents

On 6/4/15 4:24 PM, Stephen Boyd wrote: > On 06/04, dingu...@opensource.altera.com wrote: >> From: Dinh Nguyen >> >> Sprinkled all through the platform clock drivers are code like this to >> fill the clock parent array: >> >> for (i = 0; i <

Re: [PATCHv2 0/4] Add Altera Arria10 EDAC Support

On 6/5/15 6:02 AM, Borislav Petkov wrote: > On Thu, Jun 04, 2015 at 09:28:44AM -0500, ttha...@opensource.altera.com wrote: >> From: Thor Thayer >> >> This series of patches adds support for the Arria10 EDAC. The >> SDRAM controller and ECC registers are significantly different >> from the

Re: [PATCHv2 2/4] edac, altera: Refactor EDAC for Altera CycloneV SoC.

Hi Boris, On 6/5/15 4:17 AM, Borislav Petkov wrote: > On Thu, Jun 04, 2015 at 05:27:28PM -0500, Dinh Nguyen wrote: >> This is my mistake. I applied Alan Tull's patch for suspend-to-ram which >> also touches drivers/edac/altera_edac.c. >> >> https://git.kernel.org/cgi

Re: [PATCHv6 0/2] socfpga: support suspend to ram*

On Thu, Jun 4, 2015 at 5:35 PM, Dinh Nguyen wrote: > Hi Alan, > > On 06/02/2015 02:22 PM, Dinh Nguyen wrote: >> On 06/02/2015 01:35 PM, Alan Tull wrote: >>> Support suspend to ram on socfpga. >>> * allocate space in ocram using sram driver. >>> * Ad

Re: [PATCHv6 0/2] socfpga: support suspend to ram*

On Thu, Jun 4, 2015 at 5:35 PM, Dinh Nguyen dingu...@opensource.altera.com wrote: Hi Alan, On 06/02/2015 02:22 PM, Dinh Nguyen wrote: On 06/02/2015 01:35 PM, Alan Tull wrote: Support suspend to ram on socfpga. * allocate space in ocram using sram driver. * Add a function in ocram

Re: [PATCHv2 0/4] Add Altera Arria10 EDAC Support

On 6/5/15 6:02 AM, Borislav Petkov wrote: On Thu, Jun 04, 2015 at 09:28:44AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com This series of patches adds support for the Arria10 EDAC. The SDRAM controller and ECC registers are significantly

Re: [PATCHv2 2/4] edac, altera: Refactor EDAC for Altera CycloneV SoC.

Hi Boris, On 6/5/15 4:17 AM, Borislav Petkov wrote: On Thu, Jun 04, 2015 at 05:27:28PM -0500, Dinh Nguyen wrote: This is my mistake. I applied Alan Tull's patch for suspend-to-ram which also touches drivers/edac/altera_edac.c. https://git.kernel.org/cgit/linux/kernel/git/dinguyen/linux.git

Re: [RFC/PATCHv2 1/2] clk: of: helper for filling parent clock array and return num of parents

On 6/4/15 4:24 PM, Stephen Boyd wrote: On 06/04, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i num_parents; ++i) parent_names[i

Re: [PATCHv6 0/2] socfpga: support suspend to ram*

Hi Alan, On 06/02/2015 02:22 PM, Dinh Nguyen wrote: > On 06/02/2015 01:35 PM, Alan Tull wrote: >> Support suspend to ram on socfpga. >> * allocate space in ocram using sram driver. >> * Add a function in ocram to place DDR in self-refresh >> and suspend. >

Re: [PATCHv2 2/4] edac, altera: Refactor EDAC for Altera CycloneV SoC.

On 06/04/2015 05:06 PM, Borislav Petkov wrote: > On Thu, Jun 04, 2015 at 04:34:49PM -0500, Thor Thayer wrote: >> OK. I'll refactor and resend. I was using Altera's internal for-next branch. > > Use this one: > > git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git#for-next > This is my

Re: [PATCHv2 2/4] edac, altera: Refactor EDAC for Altera CycloneV SoC.

On 06/04/2015 09:28 AM, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > The Arria10 SOC uses a completely different SDRAM controller from the > earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits > for the CycloneV/ArriaV SoCs in preparation for the Arria10

Re: [PATCHv6 0/2] socfpga: support suspend to ram*

Hi Alan, On 06/02/2015 02:22 PM, Dinh Nguyen wrote: On 06/02/2015 01:35 PM, Alan Tull wrote: Support suspend to ram on socfpga. * allocate space in ocram using sram driver. * Add a function in ocram to place DDR in self-refresh and suspend. * Prevent suspend if EDAC is enabled

Re: [PATCHv2 2/4] edac, altera: Refactor EDAC for Altera CycloneV SoC.

On 06/04/2015 05:06 PM, Borislav Petkov wrote: On Thu, Jun 04, 2015 at 04:34:49PM -0500, Thor Thayer wrote: OK. I'll refactor and resend. I was using Altera's internal for-next branch. Use this one: git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git#for-next This is my mistake. I

Re: [PATCHv2 2/4] edac, altera: Refactor EDAC for Altera CycloneV SoC.

On 06/04/2015 09:28 AM, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com The Arria10 SOC uses a completely different SDRAM controller from the earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits for the CycloneV/ArriaV SoCs in preparation

Re: [PATCHv6 0/2] socfpga: support suspend to ram*

On 06/02/2015 01:35 PM, Alan Tull wrote: > Support suspend to ram on socfpga. > * allocate space in ocram using sram driver. > * Add a function in ocram to place DDR in self-refresh > and suspend. > * Prevent suspend if EDAC is enabled. > * Add a device tree binding document for the

Re: [PATCHv6 0/2] socfpga: support suspend to ram*

On 06/02/2015 01:35 PM, Alan Tull wrote: Support suspend to ram on socfpga. * allocate space in ocram using sram driver. * Add a function in ocram to place DDR in self-refresh and suspend. * Prevent suspend if EDAC is enabled. * Add a device tree binding document for the Altera

Re: [PATCHv5 1/2] ARM: socfpga: support suspend to ram

latform from going into suspend. > > Example of how to request to suspend to ram: > $ echo enabled > \ > /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup > > $ echo -n mem > /sys/power/state > > Signed-off-by: Alan Tull > Cc: Pavel Machek > Cc: Arnd Bergmann

Re: [PATCH v4 1/2] ARM: socfpga: support suspend to ram

On 05/27/2015 03:25 PM, atull wrote: > On Tue, 26 May 2015, Dinh Nguyen wrote: > >> Hi Alan, >> >> On 5/22/15 1:02 PM, Alan Tull wrote: >>> Add code that requests that the sdr controller go into >>> self-refresh mode. This code is run from ocram.

Re: [PATCHv5 1/2] ARM: socfpga: support suspend to ram

. Example of how to request to suspend to ram: $ echo enabled \ /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup $ echo -n mem /sys/power/state Signed-off-by: Alan Tull at...@opensource.altera.com Cc: Pavel Machek pa...@denx.de Cc: Arnd Bergmann a...@arndb.de Cc: Dinh Nguyen

Re: [PATCH v4 1/2] ARM: socfpga: support suspend to ram

On 05/27/2015 03:25 PM, atull wrote: On Tue, 26 May 2015, Dinh Nguyen wrote: Hi Alan, On 5/22/15 1:02 PM, Alan Tull wrote: Add code that requests that the sdr controller go into self-refresh mode. This code is run from ocram. This patch assumes that u-boot has already configured sdr

Re: [PATCH v4 1/2] ARM: socfpga: support suspend to ram

nd to ram: > $ echo enabled > \ > /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup > > $ echo -n mem > /sys/power/state > > Signed-off-by: Alan Tull > Cc: Pavel Machek > Cc: Arnd Bergmann > Cc: Dinh Nguyen > Cc: Steffen Trumtrar > --- > v2: use

Re: [PATCH v4 1/2] ARM: socfpga: support suspend to ram

.serial0/tty/ttyS0/power/wakeup $ echo -n mem /sys/power/state Signed-off-by: Alan Tull at...@opensource.altera.com Cc: Pavel Machek pa...@denx.de Cc: Arnd Bergmann a...@arndb.de Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Steffen Trumtrar s.trumt...@pengutronix.de --- v2: use

Re: [PATCH] dmaengine: pl300: enable the clock to PL330 dma

On 05/20/2015 07:35 PM, Krzysztof Kozlowski wrote: > On 21.05.2015 09:16, Krzysztof Kozlowski wrote: >> On 21.05.2015 05:30, Dinh Nguyen wrote: >>> Hi Krzysztof, >>> >>> On 05/05/2015 02:22 PM, Dinh Nguyen wrote: >>>> On 05/05/2015 09:56 AM,

Re: [PATCH] dmaengine: pl330: Fix hang on dmaengine_terminate_all on certain boards

stop() accesses > device register and can loop infinitely while checking for device state. > > The hang was confirmed by Dinh Nguyen on Altera SOCFPGA Cyclone V > board during boot. It can be also triggered with: > > $ echo 1 > /sys/module/dmatest/parameters/iterations >

Re: [PATCH] dmaengine: pl330: Fix hang on dmaengine_terminate_all on certain boards

register and can loop infinitely while checking for device state. The hang was confirmed by Dinh Nguyen on Altera SOCFPGA Cyclone V board during boot. It can be also triggered with: $ echo 1 /sys/module/dmatest/parameters/iterations $ echo dma1chan0 /sys/module/dmatest/parameters/channel

Re: [PATCH] dmaengine: pl300: enable the clock to PL330 dma

On 05/20/2015 07:35 PM, Krzysztof Kozlowski wrote: On 21.05.2015 09:16, Krzysztof Kozlowski wrote: On 21.05.2015 05:30, Dinh Nguyen wrote: Hi Krzysztof, On 05/05/2015 02:22 PM, Dinh Nguyen wrote: On 05/05/2015 09:56 AM, Dinh Nguyen wrote: On 05/04/2015 10:55 PM, Krzysztof Kozlowski wrote

Re: [PATCH] dmaengine: pl300: enable the clock to PL330 dma

Hi Krzysztof, On 05/05/2015 02:22 PM, Dinh Nguyen wrote: > On 05/05/2015 09:56 AM, Dinh Nguyen wrote: >> On 05/04/2015 10:55 PM, Krzysztof Kozlowski wrote: >>> 2015-05-05 4:52 GMT+09:00 Dinh Nguyen : >>>> On 05/04/2015 09:06 AM, Dinh Nguyen wrote: >>>&g

Re: [PATCH] dmaengine: pl300: enable the clock to PL330 dma

Hi Krzysztof, On 05/05/2015 02:22 PM, Dinh Nguyen wrote: On 05/05/2015 09:56 AM, Dinh Nguyen wrote: On 05/04/2015 10:55 PM, Krzysztof Kozlowski wrote: 2015-05-05 4:52 GMT+09:00 Dinh Nguyen dingu...@opensource.altera.com: On 05/04/2015 09:06 AM, Dinh Nguyen wrote: +CC Olof On 5/4/15 8:50 AM

Re: [PATCHv3 2/4] clk: socfpga: add a clock driver for the Arria 10 platform

On 5/19/15 4:50 PM, Stephen Boyd wrote: > On 05/19/15 09:29, Dinh Nguyen wrote: >> >> On 5/15/15 7:52 PM, Stephen Boyd wrote: >>> On 05/07, dingu...@opensource.altera.com wrote: >>>> + >>>> +static int socfpga_clk_prepare(struct clk_hw *hwclk) >

Re: [PATCHv3 2/4] clk: socfpga: add a clock driver for the Arria 10 platform

On 5/15/15 7:52 PM, Stephen Boyd wrote: > On 05/07, dingu...@opensource.altera.com wrote: >> diff --git a/drivers/clk/socfpga/clk-gate-a10.c >> b/drivers/clk/socfpga/clk-gate-a10.c >> new file mode 100644 >> index 000..fadf6f7 >> --- /dev/null >> +++ b/drivers/clk/socfpga/clk-gate-a10.c >>

Re: [PATCHv3 2/4] clk: socfpga: add a clock driver for the Arria 10 platform

On 5/19/15 4:50 PM, Stephen Boyd wrote: On 05/19/15 09:29, Dinh Nguyen wrote: On 5/15/15 7:52 PM, Stephen Boyd wrote: On 05/07, dingu...@opensource.altera.com wrote: + +static int socfpga_clk_prepare(struct clk_hw *hwclk) +{ + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk

Re: [PATCHv3 2/4] clk: socfpga: add a clock driver for the Arria 10 platform

On 5/15/15 7:52 PM, Stephen Boyd wrote: On 05/07, dingu...@opensource.altera.com wrote: diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c new file mode 100644 index 000..fadf6f7 --- /dev/null +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -0,0 +1,187

Re: [PATCH 3/4] edac, altera: Addition of Arria10 EDAC

On 05/13/2015 04:49 PM, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > The Arria10 SDRAM and ECC system differs significantly from the > Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10 > SoC. > 1) IRQ handler needs to support SHARED IRQ > 2) Support sberr and

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