On 22.02.2018 20:54, Dmitry Osipenko wrote:
> On 22.02.2018 10:42, Adrian Hunter wrote:
>> On 21/02/18 22:50, Dmitry Osipenko wrote:
>>> On 29.11.2017 16:41, Adrian Hunter wrote:
>>>> Define and use a blk-mq queue. Discards and flushes are processed
>>&g
CPU isn't allowed to touch secure registers while running under secure
monitor. Hence skip applying CPU erratas in the reset handler if Trusted
Foundations firmware presents.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 24
arch/arm/mach
r resolved the messiness in
__tegra_cpu_reset_handler_data.
- Added a comment to tf_cache_write_sec(), justifying the warning
message.
Dmitry Osipenko (5):
ARM: trusted_foundations: Implement L2 cache initialization callback
ARM: trusted_foundations: Provide informa
On Tegra20/30 L2 cache must be initialized using firmware call if CPU
is running in insecure mode. Initialize L2 cache and setup the outer-cache
callbacks in early boot using the firmware API.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/tegra.c | 15 +++
1 file changed
Implement L2 cache initialization firmware callback that should be invoked
early in boot to enable cache HW.
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c | 27 +
1 file changed, 27 insertions(+)
diff --git a/arch/arm/firmware
CPU always jumps into the reset handler in ARM-mode from the Trusted
Foundations firmware, hence make CPU to always jump into kernel in
ARM-mode regardless of the firmware presence to support Thumb2 kernel + TF
case.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 1
Add a helper that provides information about whether Trusted Foundations
firmware operations have been registered.
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c| 5 +
arch/arm/include/asm/trusted_foundations.h | 7 +++
2 files changed, 12 insertions
On Friday, 27 July 2018 23:19:53 MSK Peter Geis wrote:
> Kingston KE4CN3K6A.
> Though I am pretty sure I've figured out the instability.
> Brought it in to work and hooked it to a scope.
> Couldn't find clock, but cmd and all eight bits are running at 1.2 volts.
> Repeated the results with the
On Tuesday, 8 May 2018 19:58:41 MSK Dmitry Osipenko wrote:
> Currently Memory Controller informs about erroneous memory accesses done
> by memory clients and that's it. Let's make it to block whole HW unit
> that corresponds to the misbehaving memory client in order to try to avoid
On Sunday, 5 August 2018 03:11:57 MSK Mikko Perttunen wrote:
> One potential issue is with host1x clients where userspace processes can
> submit jobs with invalid memory accesses (addresses not mapped to
> IOMMU). If when such a failure happens, we disable the DMA for the whole
> host1x client,
On Friday, 3 August 2018 20:24:56 MSK Linus Walleij wrote:
> On Thu, Aug 2, 2018 at 1:31 PM Stefan Agner wrote:
> > A while back at least using those init lists were not well received even
> > for GPIO/pinctrl drivers:
> >
> >
On Thursday, 2 August 2018 01:51:42 MSK Stefan Agner wrote:
> On 01.08.2018 22:51, Dmitry Osipenko wrote:
> > On Thursday, 26 July 2018 18:40:25 MSK Stefan Agner wrote:
> >> The properties have been commented out to prevent a regression a
> >> while ago. The first re
On Thursday, 26 July 2018 18:40:25 MSK Stefan Agner wrote:
> The properties have been commented out to prevent a regression a
> while ago. The first regression should be resolved by
> commit 44af7927316e ("spi: Map SPI OF client IRQ at probe time").
>
> The second regression is probably addressed
On Thursday, 2 August 2018 02:11:23 MSK Dmitry Osipenko wrote:
> On Thursday, 2 August 2018 01:51:42 MSK Stefan Agner wrote:
> > On 01.08.2018 22:51, Dmitry Osipenko wrote:
> > > On Thursday, 26 July 2018 18:40:25 MSK Stefan Agner wrote:
> > >> The properties have
TRL driver registration to the arch_init level and GPIO to the
subsys_init.
Signed-off-by: Dmitry Osipenko
---
drivers/gpio/gpio-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 2d940785bad0..a53c77db9744 100644
--- a/dr
TRL driver registration to the arch_init level and GPIO to the
subsys_init.
Signed-off-by: Dmitry Osipenko
---
drivers/pinctrl/tegra/pinctrl-tegra114.c | 7 ++-
drivers/pinctrl/tegra/pinctrl-tegra124.c | 7 ++-
drivers/pinctrl/tegra/pinctrl-tegra20.c | 7 ++-
drivers/pinctrl/tegra/pinctrl-tegr
On Thursday, 2 August 2018 14:11:43 MSK Dmitry Osipenko wrote:
> There is a bug in regards to deferred probing within the drivers core
> that causes GPIO-driver to suspend after its users. The bug appears if
I meant "before its users", of course. If the rest of the patches is fine
On Thursday, 26 July 2018 20:48:55 MSK Peter Geis wrote:
> On 07/26/2018 01:36 PM, Stefan Agner wrote:
> > On 26.07.2018 18:39, Peter Geis wrote:
> >> I finally got around to testing this on the Ouya (Tegra 3).
> >
> > Thanks for testing!
> >
> >> I found that the "Got
sysfs data and finally release the cooling device.
Cc: # v4.17+
Fixes: 8ea229511e06 ("thermal: Add cooling device's statistics in sysfs")
Signed-off-by: Dmitry Osipenko
---
drivers/thermal/thermal_core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drive
On Tuesday, 19 June 2018 14:00:23 MSK Dmitry Osipenko wrote:
> Implement L2 cache initialization firmware callback that should be invoked
> early in boot to enable cache HW.
>
> Signed-off-by: Dmitry Osipenko
> ---
> arch/arm/firmware/trusted_foundations.c | 27
On Thursday, 2 August 2018 13:35:46 MSK Dmitry Osipenko wrote:
> On Thursday, 2 August 2018 02:11:23 MSK Dmitry Osipenko wrote:
> > On Thursday, 2 August 2018 01:51:42 MSK Stefan Agner wrote:
> > > On 01.08.2018 22:51, Dmitry Osipenko wrote:
> > > > On Thursday, 26
On Monday, 13 August 2018 20:48:25 MSK Dmitry Osipenko wrote:
> On Friday, 10 August 2018 02:12:11 MSK Dmitry Osipenko wrote:
> > From time to time new bugs are popping up, causing some host1x client to
> > fail its initialization. Currently a single clients initialization failure
&
On Monday, 6 August 2018 16:03:01 MSK Stefan Agner wrote:
> On 04.08.2018 16:01, Dmitry Osipenko wrote:
> > On Friday, 3 August 2018 20:24:56 MSK Linus Walleij wrote:
> >> On Thu, Aug 2, 2018 at 1:31 PM Stefan Agner wrote:
> >> > A while back at least using those ini
TRL driver registration to the arch_init level and GPIO to the
subsys_init.
Signed-off-by: Dmitry Osipenko
Acked-by: Stefan Agner
---
Changelog:
v2: Corrected commit message with s/to suspend after/to suspend before/.
drivers/gpio/gpio-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
TRL driver registration to the arch_init level and GPIO to the
subsys_init.
Signed-off-by: Dmitry Osipenko
Acked-by: Stefan Agner
---
Changelog:
v2: Corrected commit message with s/to suspend after/to suspend before/.
drivers/pinctrl/tegra/pinctrl-tegra114.c | 7 ++-
drivers/pinctrl/tegra/pinctrl-
On Thursday, 2 August 2018 16:01:24 MSK Dmitry Osipenko wrote:
> On Thursday, 2 August 2018 14:11:43 MSK Dmitry Osipenko wrote:
> > There is a bug in regards to deferred probing within the drivers core
> > that causes GPIO-driver to suspend after its users. The bug appears if
>
) may result in extra long period of PLL re-locking.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-pll.c | 50 +++--
1 file changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 830d1c87fa7c
the lock-status polling. This significantly
reduces delay of any operation that require PLL to lock.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-tegra20.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b
On Friday, 20 July 2018 11:02:04 MSK Jon Hunter wrote:
> On 19/07/18 16:38, Dmitry Osipenko wrote:
> > On Thursday, 19 July 2018 18:30:48 MSK Jon Hunter wrote:
> >> On 19/07/18 14:24, Dmitry Osipenko wrote:
> >>> This fixes irrelevant "tegra-mc 7000f000.memory-
On Saturday, 21 July 2018 12:56:15 MSK Mark Brown wrote:
> On Fri, Jul 20, 2018 at 12:31:07PM +, Marcel Ziswiler wrote:
> > On Fri, 2018-07-20 at 13:16 +0100, Mark Brown wrote:
> > > > ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
> > > >
> > > >
On Saturday, 21 July 2018 14:55:21 MSK Marcel Ziswiler wrote:
> On Sat, 2018-07-21 at 14:17 +0300, Dmitry Osipenko wrote:
>
> > On Saturday, 21 July 2018 12:56:15 MSK Mark Brown wrote:
> >
> > > On Fri, Jul 20, 2018 at 12:31:07PM +, Marcel Ziswiler wrote:
> &
On Saturday, 21 July 2018 15:03:57 MSK Dmitry Osipenko wrote:
> On Saturday, 21 July 2018 14:55:21 MSK Marcel Ziswiler wrote:
> > On Sat, 2018-07-21 at 14:17 +0300, Dmitry Osipenko wrote:
> > > On Saturday, 21 July 2018 12:56:15 MSK Mark Brown wrote:
> > > > On F
p_lock_as_irq: cannot get GPIO direction
tegra-gpio 6000d000.gpio: unable to lock Tegra GPIO 144 as IRQ
Fixes: 36b312792b97 ("gpiolib: Respect error code of ->get_direction()")
Signed-off-by: Dmitry Osipenko
---
drivers/gpio/gpio-tegra.c | 15 ---
1 file changed, 8
On Monday, 23 July 2018 21:37:50 MSK Peter Geis wrote:
> On 07/23/2018 02:13 PM, Mark Brown wrote:
> > On Mon, Jul 23, 2018 at 01:58:26PM -0400, Peter Geis wrote:
> >> SW2 and SW4 use a shared table to provide voltage to the cpu core and
> >> devices on Tegra hardware.
> >> Added this table to the
On Monday, 23 July 2018 22:38:48 MSK Peter Geis wrote:
> Added support for the CPCAP power management regulator functions on
> Tegra devices.
> Added sw2_sw4 value tables, which provide power to the Tegra core and
> aux devices.
> Added the Tegra init tables and device tree compatibility match.
>
On Tuesday, 24 July 2018 04:57:24 MSK Peter Geis wrote:
> On 07/23/2018 08:27 PM, Dmitry Osipenko wrote:
> > On Monday, 23 July 2018 22:38:48 MSK Peter Geis wrote:
> >> Added support for the CPCAP power management regulator functions on
> >> Tegra devices.
> >&g
On Monday, 23 July 2018 16:05:21 MSK Dmitry Osipenko wrote:
> On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> > The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> > clocks by making a 2D and 3D mux, and split the divider into the
> > standard 2D/3
On Thursday, 19 July 2018 16:21:30 MSK Dmitry Osipenko wrote:
> Kernel should never gate the EMC clock as it causes immediate lockup, so
> removing clk-gate functionality doesn't affect anything. Turning EMC clk
> gate into divider allows to implement glitch-less EMC scaling,
On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> clocks by making a 2D and 3D mux, and split the divider into the
> standard 2D/3D ones and 2D/3D idle clocks.
>
> Signed-off-by: Ben Dooks
> ---
>
On Monday, 23 July 2018 11:28:25 MSK Ben Dooks wrote:
> On 2018-07-22 12:55, Dmitry Osipenko wrote:
> > On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> >> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> >> clocks by making a 2D and 3D
On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote:
> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these
> clocks by making a 2D and 3D mux, and split the divider into the
> standard 2D/3D ones and 2D/3D idle clocks.
>
> Signed-off-by: Ben Dooks
> ---
>
This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
timings for RAM code 0 registered" warning message during of kernels
boot-up on Tegra20.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletion
Introduce driver for the External Memory Controller (EMC) found on Tegra20
chips, which controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
Ensure that direct PLLM sourcing is turned off for EMC as we don't support
that configuration in the clk driver.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra20.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/tegra/clk
code cleanups like consistent use of writel_relaxed instead
of non-relaxed version, reworded error messages, etc.
- Factored out use_pllm_ud bit checking into a standalone patch for
consistency.
Dmitry Osipenko (8):
dt: bindings: tegra20-emc: Document interrupt proper
Kernel should never gate the EMC clock as it causes immediate lockup, so
removing clk-gate functionality doesn't affect anything. Turning EMC clk
gate into divider allows to implement glitch-less EMC scaling, avoiding
reparenting to a backup clock.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter
Add clock entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9eb4163a4390..979f38293fe5 100644
--- a/arch/arm/boot/dts/tegra20
Embedded memory controller has a corresponding clock, document the clock
property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
EMC has a dedicated interrupt that is used to notify about completion of
HW operations. Document the interrupt property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
Acked-by: Peter De Schrijver
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed
Add interrupt entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 15b73bd377f0..9eb4163a4390 100644
Move tegra20-emc binding to the memory-controllers directory for
consistency with the other Tegra memory bindings.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../{arm/tegra => memory-controllers}/nvidia,tegra20-emc.txt | 0
1 file changed, 0 insertions(+), 0 deleti
On Thursday, 19 July 2018 18:30:48 MSK Jon Hunter wrote:
> On 19/07/18 14:24, Dmitry Osipenko wrote:
> > This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
> > timings for RAM code 0 registered" warning message during of kernels
> > b
This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
timings for RAM code 0 registered" warning message during of kernels
boot-up on Tegra20.
Fixes: a8d502fd3348 ("memory: tegra: Squash tegra20-mc into common tegra-mc
driver")
Signed-off-by: Dmitry Osipenko
On Sunday, 22 July 2018 19:49:09 MSK Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> Avoid eMMC issues by specifying broken-hpi.
>
> Signed-off-by: Marcel Ziswiler
>
> ---
Is it a specific eMMC card model that has broken HPI or it is a host
controller bug?
On Tuesday, 24 July 2018 15:24:34 MSK Marcel Ziswiler wrote:
> Sorry, I meant to write "minor revamp" in the subject line here as
> Apalis TK1 was already in quite good a shape but this are still some
> worthy improvements (;-p).
>
> On Tue, 2018-07-24 at 12:42 +0200, Marcel Ziswiler wrote:
>
On Tuesday, 24 July 2018 17:26:58 MSK Marcel Ziswiler wrote:
> On Tue, 2018-07-24 at 17:03 +0300, Dmitry Osipenko wrote:
>
> > On Sunday, 22 July 2018 19:49:09 MSK Marcel Ziswiler wrote:
> >
> > > From: Marcel Ziswiler
> > >
> > > Avoid eMMC issues
On Tuesday, 24 July 2018 17:16:33 MSK Marcel Ziswiler wrote:
> On Tue, 2018-07-24 at 15:44 +0300, Dmitry Osipenko wrote:
>
> > On Tuesday, 24 July 2018 15:24:34 MSK Marcel Ziswiler wrote:
> >
> > > Sorry, I meant to write "minor revamp" in the subject line
On Tuesday, 24 July 2018 17:45:01 MSK Marcel Ziswiler wrote:
> On Tue, 2018-07-24 at 17:31 +0300, Dmitry Osipenko wrote:
>
> > On Tuesday, 24 July 2018 17:16:33 MSK Marcel Ziswiler wrote:
> >
> > > On Tue, 2018-07-24 at 15:44 +0300, Dmitry Osipenko wrote:
> >
se clocks should be in the device tree.
- Some minor cleanups and fixes in the drivers code.
v2:
- Minor code cleanups like consistent use of writel_relaxed instead
of non-relaxed version, reworded error messages, etc.
- Factored out use_pllm_ud bit checking into a
Embedded memory controller has a corresponding clock, document the clock
property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
Move tegra20-emc binding to the memory-controllers directory for
consistency with the other Tegra memory bindings.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../{arm/tegra => memory-controllers}/nvidia,tegra20-emc.txt | 0
1 file changed, 0 insertions(+), 0 deleti
EMC has a dedicated interrupt that is used to notify about completion of
HW operations. Document the interrupt property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
Acked-by: Peter De Schrijver
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed
Add interrupt entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 15b73bd377f0..9eb4163a4390 100644
Add clock entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9eb4163a4390..979f38293fe5 100644
--- a/arch/arm/boot/dts/tegra20
Introduce driver for the External Memory Controller (EMC) found on Tegra20
chips, which controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
Ensure that direct PLLM sourcing is turned off for EMC as we don't support
that configuration in the clk driver.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra20.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/tegra/clk
Kernel should never gate the EMC clock as it causes immediate lockup, so
removing clk-gate functionality doesn't affect anything. Turning EMC clk
gate into divider allows to implement glitch-less EMC scaling, avoiding
reparenting to a backup clock.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter
On Tuesday, 24 July 2018 18:47:41 MSK Peter Geis wrote:
> On 07/24/2018 10:48 AM, Dmitry Osipenko wrote:
> > On Tuesday, 24 July 2018 17:45:01 MSK Marcel Ziswiler wrote:
> >> On Tue, 2018-07-24 at 17:31 +0300, Dmitry Osipenko wrote:
> >>> On Tuesday, 24 July 2018 17:1
Tegra20/30 drivers do not handle the tick_broadcast_enter() error,
let's just move out the broadcasting to the CPUIDLE core by setting
the respective flag in the Tegra20/30 drivers.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 11 ++-
arch/arm/mach-tegra
Add more predefined rates to the PLLX table, allowing to lower the rate
down to 312MHz. This gives more variations of frequency selection to the
CPUFREQ driver.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-tegra30.c | 42 +
1 file changed, 42
parents from device tree, which is necessary for the CPUFreq
driver.
Note that CCLKG bypasses clock divider only if PLLX is selected as the
parent, hence previous CCLKG parents definition was incorrect.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-super.c| 16
Hello,
This series is a prerequisite for the CPUFREQ driver patches, it can be
applied separately. CPUFREQ will be supported on Tegra30 once this and
the CPUFREQ patch-series will be applied.
Dmitry Osipenko (3):
clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30
clk: tegra: Add
Poll PLLX lock-status instead of delaying for a constant time. This speeds
up resume from suspend a tad and is less error-prone since lock failure
will be reported.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-tegra20.c | 51 +++--
drivers/clk/tegra/clk
Tegra20-cpufreq driver require a platform device in order to be loaded,
instantiate a simple platform device for the driver during of the machines
late initialization. Driver now supports Tegra30 SoC's, hence create the
device on Tegra30 machines.
Signed-off-by: Dmitry Osipenko
---
arch/arm
Add device-tree binding that describes CPU frequency-scaling hardware
found on NVIDIA Tegra20/30 SoC's.
Signed-off-by: Dmitry Osipenko
---
.../cpufreq/nvidia,tegra20-cpufreq.txt| 38 +++
1 file changed, 38 insertions(+)
create mode 100644
Documentation/devicetree
Add support for thermal throttling and Operating Performance Points.
Driver now relies on OPP's supplied via device tree and therefore will
work only on devices that use the updated device tree. The generalization
of the driver allows to transparently support Tegra30.
Signed-off-by: Dmitry
Add CPU's Operating Performance Points to the device tree, they are used
by the CPUFreq driver and allow to setup thermal throttling for the boards
by linking the cooling device (CPU) with thermal sensors via thermal-zones
description.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts
Add CPU's Operating Performance Points to the device tree, they are used
by the CPUFreq driver and allow to setup thermal throttling for the boards
by linking the cooling device (CPU) with thermal sensors via thermal-zones
description.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts
depends on the clock patches that
are under review now, CPUFREQ driver will fail to probe until CCLKG clock
will get exposed by the clock driver. Hence this series can be applied
independently of the clock patches, CPUFREQ will start to work on Tegra30
once both patchsets will be applied.
Dmitry
Hello,
This patch-series fixes CPU hanging after suspend-resume / LP2 cpuidle
on Tegra30. The bug really appears during stress-testing, like frequent
suspending under variable load + the upcoming Tegra30 CPUFREQ driver.
Dmitry Osipenko (2):
ARM: tegra: Switch CPU to PLLP before powergating
-by: Dmitry Osipenko
---
arch/arm/mach-tegra/sleep-tegra30.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S
b/arch/arm/mach-tegra/sleep-tegra30.S
index d572d4b860be..127fc78365fe 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b
PLLX is getting turned by the HW logic when CPU enters powergated state
and there is no enough time for PLLX to re-lock on exiting the low-power
state, this causes memory errors coming from misbehaving CPU and eventual
hanging of the system.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach
_write_sec(), justifying the warning
message.
Dmitry Osipenko (8):
ARM: trusted_foundations: Implement L2 cache initialization callback
ARM: trusted_foundations: Make prepare_idle call to take mode argument
ARM: trusted_foundations: Provide information about whether firmware
is regist
On Tegra30 L2 cache should be initialized using firmware call if CPU is
running in insecure mode. Initialize L2 cache and setup the outer-cache
callbacks in early boot using the firmware API.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/tegra.c | 10 ++
1 file changed, 10
) may result in extra long period of PLL re-locking.
Signed-off-by: Dmitry Osipenko
---
Changelog:
v2: No change.
drivers/clk/tegra/clk-pll.c | 50 +++--
1 file changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk
. This reduces delay of any operation that require PLL
to lock.
Signed-off-by: Dmitry Osipenko
---
Changelog:
v2: Don't enable polling for PLLE as it known to not being able to lock.
drivers/clk/tegra/clk-tegra20.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions
Add a helper that provides information about whether Trusted Foundations
firmware operations have been registered.
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c| 5 +
arch/arm/include/asm/trusted_foundations.h | 7 +++
2 files changed, 12 insertions
.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/reset-handler.S
b/arch/arm/mach-tegra/reset-handler.S
index a9f13230da2f..555c652f5a07 100644
--- a/arch/arm/mach-tegra
Trusted Foundations firmware require MMU to be enabled for L2 cache
maintenance on Tegra30, hence perform the maintenance early-late on
suspend-resume respectively.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/pm.c| 36 +
arch/arm/mach-tegra
In order to resume CPU from suspend via trusted Foundations firmware,
the LP1/LP2 boot vectors shall be specified using the firmware calls.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/pm.c| 7 ++
arch/arm/mach-tegra/reset-handler.S | 33
CPU isn't allowed to touch secure registers while running under secure
monitor. Hence skip applying of CPU erratas in the reset handler if
Trusted Foundations firmware presents.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 24
arch/arm/mach
The Trusted Foundations firmware call varies depending on the required
suspend-mode. Make the firmware API to take the mode argument in order
to expose all of the modes to firmware user.
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c| 29
Implement L2 cache initialization firmware callback that should be invoked
early in boot in order to setup the required outer cache driver callbacks.
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c | 46 +
1 file changed, 46 insertions(+)
diff
The memory interface configuration and re-calibration interval are left
unassigned on resume from LP1 because these registers are shadowed and
require latching after being adjusted.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/sleep-tegra30.S | 2 ++
1 file changed, 2 insertions
Hello,
This patch series fixes couple bugs in the memory self-refresh code.
The EMC / MC state is properly restored after patches being applied,
please review.
Dmitry Osipenko (4):
ARM: tegra: Fix missed EMC registers latching on resume from LP1 on
Tegra30+
ARM: tegra: Fix DRAM refresh
LP1 on Tegra30.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/iomap.h | 9 +
arch/arm/mach-tegra/sleep-tegra30.S | 21 +
2 files changed, 30 insertions(+)
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 9e5b2f869fc8
from the self-refresh mode for consistency, that
will also allow to not receive spurious interrupts in the EMC driver
after resume from suspend.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/sleep-tegra30.S | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-tegra
The DRAM refresh-interval is getting erroneously set to "1" on exiting
from memory self-refreshing mode. The clobbered interval causes the
"refresh request overflow timeout" error raised by the External Memory
Controller on exiting from LP1 on Tegra30.
Signed-off-by: Dmitry
)
[] (kernel_init_freeable) from [] (kernel_init+0x18/0x124)
[] (kernel_init) from [] (ret_from_fork+0x14/0x24)
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index
[] (cpu_startup_entry+0x28/0x2c)
[] (cpu_startup_entry) from [] (rest_init+0xd8/0xdc)
[] (rest_init) from [] (start_kernel+0x41c/0x430)
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git
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