Re: [PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

于 2017年8月23日 GMT+08:00 上午4:12:15, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Tue, Aug 22, 2017 at 02:17:42PM +0800, Icenowy Zheng wrote: >> +_vcc5v0 { >> +gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ >> +enable-active-high; >> +

Re: [PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

于 2017年8月23日 GMT+08:00 上午4:12:15, Maxime Ripard 写到: >On Tue, Aug 22, 2017 at 02:17:42PM +0800, Icenowy Zheng wrote: >> +_vcc5v0 { >> +gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ >> +enable-active-high; >> +}; > >Same thing here, you're not using t

Re: [PATCH 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

于 2017年8月23日 GMT+08:00 上午4:10:43, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >Hi, > >On Tue, Aug 22, 2017 at 02:17:41PM +0800, Icenowy Zheng wrote: >> From: Chen-Yu Tsai <w...@csie.org> >> >> The Banana Pi M2 Ultra is an SBC based on th

Re: [PATCH 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

于 2017年8月23日 GMT+08:00 上午4:10:43, Maxime Ripard 写到: >Hi, > >On Tue, Aug 22, 2017 at 02:17:41PM +0800, Icenowy Zheng wrote: >> From: Chen-Yu Tsai >> >> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The >> form factor and position of var

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

于 2017年8月23日 GMT+08:00 上午4:05:21, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >Hi, > >On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote: >> From: Chen-Yu Tsai <w...@csie.org> >> >> The Allwinner R40 SoC is marketed as the successor

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

于 2017年8月23日 GMT+08:00 上午4:05:21, Maxime Ripard 写到: >Hi, > >On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote: >> From: Chen-Yu Tsai >> >> The Allwinner R40 SoC is marketed as the successor to the A20 SoC. >> The R40 is a smaller chip than t

[PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

headphone jack - red and green LEDs - debug UART pins - Raspberry Pi B+ compatible GPIO header - power and reset buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/Makefile

[PATCH 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

headphone jack - red and green LEDs - debug UART pins - Raspberry Pi B+ compatible GPIO header - power and reset buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/Makefile| 3 +- arch/arm/boot

[PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

00 MP2 GPU. It retains most if not all features from the A20, while adding some new features, such as MIPI DSI output, or updating various hardware blocks, such as DE 2.0. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/

[PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

. It retains most if not all features from the A20, while adding some new features, such as MIPI DSI output, or updating various hardware blocks, such as DE 2.0. Signed-off-by: Chen-Yu Tsai Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-r40.dtsi | 396 +++ 1

[PATCH 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

power, reset, and boot control buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/Makefile| 1 + arch/arm/boot/dts/sun

[PATCH 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

control buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Chen-Yu Tsai Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/Makefile| 1 + arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 181 ++ 2 files

[PATCH v2 3/3] ARM: sunxi: add support for R40 SoC

Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Fix alphabetical orders. Documentation/arm/sunxi/README | 6 ++ Documentation/devicetree/bindin

[PATCH v2 3/3] ARM: sunxi: add support for R40 SoC

Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v2: - Fix alphabetical orders. Documentation/arm/sunxi/README | 6 ++ Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch

[PATCH v2 2/3] ARM: sunxi: fix the core number of V3s in sunxi README

The Allwinner V3s SoC is not quad-core, but single-core. Fix this in the README file. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/arm/sunxi/README | 9 + 1 file changed, 5 insertions

[PATCH v2 2/3] ARM: sunxi: fix the core number of V3s in sunxi README

The Allwinner V3s SoC is not quad-core, but single-core. Fix this in the README file. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Signed-off-by: Icenowy Zheng --- Documentation/arm/sunxi/README | 9 + 1 file changed, 5 insertions(+), 4 deletions(-)

[PATCH v2 1/3] dt-bindings: add compatible string for Allwinner V3s SoC

The compatible string for Allwinner V3s SoC used to be missing. Add it to the binding document. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file chan

[PATCH v2 1/3] dt-bindings: add compatible string for Allwinner V3s SoC

The compatible string for Allwinner V3s SoC used to be missing. Add it to the binding document. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file changed, 1 insertion(+)

[PATCH v2 3/4] net: phy: realtek: add disable RX internal delay mode

From: Icenowy Zheng <icen...@aosc.xyz> Some RTL8211E chips have broken GbE function, which needs a hack to fix. It's said that this fix will affect the performance on not-buggy PHYs, so it should only be enabled on boards with the broken PHY. Currently only some Pine64+ boards are known t

[PATCH v2 3/4] net: phy: realtek: add disable RX internal delay mode

From: Icenowy Zheng Some RTL8211E chips have broken GbE function, which needs a hack to fix. It's said that this fix will affect the performance on not-buggy PHYs, so it should only be enabled on boards with the broken PHY. Currently only some Pine64+ boards are known to have this issue

[PATCH v2 2/4] net: phy: realtek: change macro name for page select register

From: Icenowy Zheng <icen...@aosc.xyz> The page select register also exists on RTL8211E PHY (although it behaves slightly differently). Change the register macro name to remove the F. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- drivers/net/phy/realtek.c | 12 +++-

[PATCH v2 2/4] net: phy: realtek: change macro name for page select register

From: Icenowy Zheng The page select register also exists on RTL8211E PHY (although it behaves slightly differently). Change the register macro name to remove the F. Signed-off-by: Icenowy Zheng --- drivers/net/phy/realtek.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions

[PATCH v2 4/4] arm64: allwinner: a64: disable the RTL8211E internal RX delay on Pine64+

Some Pine64+ boards have a broken RTL8211E PHY, which cannot work reliably in 1000Base-T mode with default configuration. A solution is passed to Pine64, which is said to be disabling the internal RX delay of the PHY. Enable the hack by set the PHY mode to RGMII-TXID. Signed-off-by: Icenowy

[PATCH v2 4/4] arm64: allwinner: a64: disable the RTL8211E internal RX delay on Pine64+

Some Pine64+ boards have a broken RTL8211E PHY, which cannot work reliably in 1000Base-T mode with default configuration. A solution is passed to Pine64, which is said to be disabling the internal RX delay of the PHY. Enable the hack by set the PHY mode to RGMII-TXID. Signed-off-by: Icenowy

[PATCH v2 1/4] net: stmmac: dwmac-sun8i: support RGMII modes with PHY internal delay

Some boards uses a PHY with internal delay with an Allwinner SoC. Support these PHY modes in the driver. As the driver has no configuration registers for these modes, just treat them as ordinary RGMII. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/ethernet/stmicro/stmmac

[PATCH v2 1/4] net: stmmac: dwmac-sun8i: support RGMII modes with PHY internal delay

Some boards uses a PHY with internal delay with an Allwinner SoC. Support these PHY modes in the driver. As the driver has no configuration registers for these modes, just treat them as ordinary RGMII. Signed-off-by: Icenowy Zheng --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3

[PATCH v2 0/4] Workaround broken RTL8211E on some Pine64+ boards

variants' support to the dwmac-sun8i driver. The second patch renames some macros in RTL PHY driver, and the third patch introduces the hack as the "RGMII-TXID" mode of the PHY. The fourth patch enables the hack in the device tree. Icenowy Zheng (4): net: stmmac: dwmac-sun8i: support R

[PATCH v2 0/4] Workaround broken RTL8211E on some Pine64+ boards

variants' support to the dwmac-sun8i driver. The second patch renames some macros in RTL PHY driver, and the third patch introduces the hack as the "RGMII-TXID" mode of the PHY. The fourth patch enables the hack in the device tree. Icenowy Zheng (4): net: stmmac: dwmac-sun8i: support R

[PATCH 2/2] ARM: sunxi: add support for R40 SoC

Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/arm/sunxi/README | 6 ++ Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/s

[PATCH 2/2] ARM: sunxi: add support for R40 SoC

Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng --- Documentation/arm/sunxi/README | 6 ++ Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/sunxi.c

[PATCH 1/2] dt-bindings: add compatible string for Allwinner V3s SoC

The compatible string for Allwinner V3s SoC used to be missing. Add it to the binding document. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file chan

[PATCH 1/2] dt-bindings: add compatible string for Allwinner V3s SoC

The compatible string for Allwinner V3s SoC used to be missing. Add it to the binding document. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file changed, 1 insertion(+)

Re: [linux-sunxi] [PATCH 2/4] drivers: soc: sunxi: fix error processing on base address when claiming

于 2017年8月18日 GMT+08:00 下午2:21:07, Chen-Yu Tsai <w...@csie.org> 写到: >Hi, > >On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng <icen...@aosc.io> wrote: >> When claiming SRAM, if the base is set to an error, it means that the >> SRAM controller has been probed, b

Re: [linux-sunxi] [PATCH 2/4] drivers: soc: sunxi: fix error processing on base address when claiming

于 2017年8月18日 GMT+08:00 下午2:21:07, Chen-Yu Tsai 写到: >Hi, > >On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote: >> When claiming SRAM, if the base is set to an error, it means that the >> SRAM controller has been probed, but failed to remap the controller >> memor

[PATCH] ARM: sun8i: a33: add dts for Q8 tablets with different resolution

driver still has some problems to support the LCDs, the real LCD device nodes are not added to the device tree files. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dt

[PATCH] ARM: sun8i: a33: add dts for Q8 tablets with different resolution

driver still has some problems to support the LCDs, the real LCD device nodes are not added to the device tree files. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts | 49 ++ arch/arm

[PATCH v5] clk: sunxi-ng: support R40 SoC

Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v5: - Added TODO's for PLL constraints. - Forced OHCI12M mux to 0. - Changed "

[PATCH v5] clk: sunxi-ng: support R40 SoC

Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v5: - Added TODO's for PLL constraints. - Forced OHCI12M mux to 0. - Changed "adda" clock

[PATCH v4 3/3] clk: sunxi-ng: support R40 SoC

Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v4: - Removed usb-ohci-12M mux clocks. - Removed unused (and not in user manual) a

[PATCH v4 2/3] clk: sunxi-ng: nkm: add support for fixed post-divider

SATA PLL on Allwinner R40 is of type (parent) * N * K / M / 6 where 6 is the fixed post-divider. Add post-divider support for NKM type clock. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu_nkm.c | 22 +++--- drivers/clk/sunxi-ng/ccu_nkm.h | 2

[PATCH v4 3/3] clk: sunxi-ng: support R40 SoC

Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v4: - Removed usb-ohci-12M mux clocks. - Removed unused (and not in user manual) adda-4x clock

[PATCH v4 2/3] clk: sunxi-ng: nkm: add support for fixed post-divider

SATA PLL on Allwinner R40 is of type (parent) * N * K / M / 6 where 6 is the fixed post-divider. Add post-divider support for NKM type clock. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu_nkm.c | 22 +++--- drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++ 2 files changed, 21

[PATCH v4 0/3] Allwinner R40 CCU driver

). Patch 2 adds postdiv support for NKM type clock, which is needed for pll-sata (with a postdiv of 6). Patch 3 is the main patch, which adds the support for R40 CCU. Icenowy Zheng (2): clk: sunxi-ng: nkm: add support for fixed post-divider clk: sunxi-ng: support R40 SoC Priit Laes (1): clk: sunxi

[PATCH v4 1/3] clk: sunxi-ng: div: Add support for fixed post-divider

From: Priit Laes SATA clock on sun4i/sun7i is of type (parent) / M / 6 where 6 is fixed post-divider. Signed-off-by: Priit Laes --- It's based on the patch in v6 of the A10/A20 CCU patchset, but with ccu_div_round_rate fixed. drivers/clk/sunxi-ng/ccu_div.c |

[PATCH v4 0/3] Allwinner R40 CCU driver

). Patch 2 adds postdiv support for NKM type clock, which is needed for pll-sata (with a postdiv of 6). Patch 3 is the main patch, which adds the support for R40 CCU. Icenowy Zheng (2): clk: sunxi-ng: nkm: add support for fixed post-divider clk: sunxi-ng: support R40 SoC Priit Laes (1): clk: sunxi

[PATCH v4 1/3] clk: sunxi-ng: div: Add support for fixed post-divider

From: Priit Laes SATA clock on sun4i/sun7i is of type (parent) / M / 6 where 6 is fixed post-divider. Signed-off-by: Priit Laes --- It's based on the patch in v6 of the A10/A20 CCU patchset, but with ccu_div_round_rate fixed. drivers/clk/sunxi-ng/ccu_div.c | 22 +++---

[PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

arm64: allwinner: h5: add Allwinner H5 .dtsi") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi in

[PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

arm64: allwinner: h5: add Allwinner H5 .dtsi") Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 732e2e06f503..d9

[PATCH 0/2] Allwinner H5 IRQ fixes

The current pinctrl code and H5 device tree have an error: the bank number of IRQs are wrongly set to 2, which makes PG bank interrupts not usable. Fixes in both the pinctrl driver and the device tree. Please apply the DT fix after applying the pinctrl fix. Icenowy Zheng (2): pinctrl: sunxi

[PATCH 0/2] Allwinner H5 IRQ fixes

The current pinctrl code and H5 device tree have an error: the bank number of IRQs are wrongly set to 2, which makes PG bank interrupts not usable. Fixes in both the pinctrl driver and the device tree. Please apply the DT fix after applying the pinctrl fix. Icenowy Zheng (2): pinctrl: sunxi

[PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

, and allow new device trees to use correct 3 IRQ banks. Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 26 +++--- 1 file changed, 23 insertions

[PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

, and allow new device trees to use correct 3 IRQ banks. Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC") Signed-off-by: Icenowy Zheng --- drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 26 +++--- 1 file changed, 23 insertions(+), 3 deletions(-)

Re: [linux-sunxi] [PATCH v4] arm64: allwinner: a64: Add initial NanoPi A64 support

于 2017年8月11日 GMT+08:00 下午8:31:43, Jagan Teki 写到: >From: Jagan Teki > >NanoPi A64 is a new board of high performance with low cost >designed by FriendlyElec., using the Allwinner A64 SOC. As AXP803 regulators support now entered linux-next,

Re: [linux-sunxi] [PATCH v4] arm64: allwinner: a64: Add initial NanoPi A64 support

于 2017年8月11日 GMT+08:00 下午8:31:43, Jagan Teki 写到: >From: Jagan Teki > >NanoPi A64 is a new board of high performance with low cost >designed by FriendlyElec., using the Allwinner A64 SOC. As AXP803 regulators support now entered linux-next, please add proper AXP803 support when supporting new

Re: [linux-sunxi] [PATCH 1/3] arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node

于 2017年8月10日 GMT+08:00 上午11:56:02, Chen-Yu Tsai <w...@csie.org> 写到: >Hi, > >On Sat, Jul 22, 2017 at 10:28 AM, Icenowy Zheng <icen...@aosc.io> >wrote: >> The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet >> link. >> >> Add the eth

Re: [linux-sunxi] [PATCH 1/3] arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node

于 2017年8月10日 GMT+08:00 上午11:56:02, Chen-Yu Tsai 写到: >Hi, > >On Sat, Jul 22, 2017 at 10:28 AM, Icenowy Zheng >wrote: >> The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet >> link. >> >> Add the ethernet0 alias in the device tree, in o

[PATCH 1/4] dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C

The display engine on Allwinner A64 wants to claim the SRAM C section. Add a SRAM controller compatible for A64, and a SRAM section compatible for its SRAM C. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 9 +++-- 1 file c

[PATCH 1/4] dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C

The display engine on Allwinner A64 wants to claim the SRAM C section. Add a SRAM controller compatible for A64, and a SRAM section compatible for its SRAM C. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 9 +++-- 1 file changed, 7 insertions

[PATCH 2/4] drivers: soc: sunxi: fix error processing on base address when claiming

-EPROBE_DEFER in the former situation, and ignored the latter situation (which will lead to the kernel to panic). Fix the behavior on abnormal base address processing when claiming. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/soc/sunxi/sunxi_sram.c | 3 +++ 1 file changed, 3 inse

[PATCH 3/4] drivers: soc: sunxi: add support for remapping func value to reg value

E, and for Allwinner A64's SRAM C the needed register value to claim it to DE2 is 0, and the value that enables CPU's access to the SRAM is 1. Add a value remapping in sunxi_sram_func structure, and let the sunxi_sram_of_parse function set the remapped register value. Signed-off-by: Icenowy Zh

[PATCH 2/4] drivers: soc: sunxi: fix error processing on base address when claiming

-EPROBE_DEFER in the former situation, and ignored the latter situation (which will lead to the kernel to panic). Fix the behavior on abnormal base address processing when claiming. Signed-off-by: Icenowy Zheng --- drivers/soc/sunxi/sunxi_sram.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

[PATCH 3/4] drivers: soc: sunxi: add support for remapping func value to reg value

E, and for Allwinner A64's SRAM C the needed register value to claim it to DE2 is 0, and the value that enables CPU's access to the SRAM is 1. Add a value remapping in sunxi_sram_func structure, and let the sunxi_sram_of_parse function set the remapped register value. Signed-off-by: Icenowy Zhe

[PATCH 4/4] drivers: soc: sunxi: add support for A64 and its SRAM C

Allwinner A64's display engine claims the SRAM C section to work. Add support for the A64 SRAM controller and the SRAM C section of it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/soc/sunxi/sunxi_sram.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drive

[PATCH 4/4] drivers: soc: sunxi: add support for A64 and its SRAM C

Allwinner A64's display engine claims the SRAM C section to work. Add support for the A64 SRAM controller and the SRAM C section of it. Signed-off-by: Icenowy Zheng --- drivers/soc/sunxi/sunxi_sram.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/soc/sunxi

[PATCH 0/4] Allwinner A64 SRAM C (DE2 SRAM) support

; this patch fixed probe defering when claiming SRAM region. Patch 3 adds the remapping code. Patch 4 adds necessary codes for A64 SRAM C. Icenowy Zheng (4): dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C drivers: soc: sunxi: fix error processing on base address when claiming

[PATCH 0/4] Allwinner A64 SRAM C (DE2 SRAM) support

; this patch fixed probe defering when claiming SRAM region. Patch 3 adds the remapping code. Patch 4 adds necessary codes for A64 SRAM C. Icenowy Zheng (4): dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C drivers: soc: sunxi: fix error processing on base address when claiming

[PATCH v2] mmc: sunxi: fix support for new timings mode only SoCs

: b0600daebf31 ("mmc: sunxi: Support controllers that can use both old and new timings") Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v2: - Slightly adjusted the format of the Fixes: line/ - Added r

[PATCH v2] mmc: sunxi: fix support for new timings mode only SoCs

: b0600daebf31 ("mmc: sunxi: Support controllers that can use both old and new timings") Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai --- Changes in v2: - Slightly adjusted the format of the Fixes: line/ - Added review tag from Chen-Yu. drivers/mmc/host/sunxi

Re: [linux-sunxi] [PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller

于 2017年8月6日 GMT+08:00 上午10:39:54, Chen-Yu Tsai <w...@csie.org> 写到: >On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote: >> The configuration struct of A64 EMMC(MMC2) compatible used to >> have the needs_new_timings variable missing, which lead to NULL >> p

Re: [linux-sunxi] [PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller

于 2017年8月6日 GMT+08:00 上午10:39:54, Chen-Yu Tsai 写到: >On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote: >> The configuration struct of A64 EMMC(MMC2) compatible used to >> have the needs_new_timings variable missing, which lead to NULL >> pointer dereference now

[PATCH 1/2] mmc: sunxi: fix support for new timings mode only SoCs

: b0600daebf31 ("mmc: sunxi: Support controllers that can use both old and new timings") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/mmc/host/sunxi-mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/s

[PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller

it to true in the configuration struct. Fixes: 4fb3ce07eafa ("mmc: sunxi: Add EMMC (MMC2) controller compatible") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/mmc/host/sunxi-mmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sunxi-mmc.c b/

[PATCH 1/2] mmc: sunxi: fix support for new timings mode only SoCs

: b0600daebf31 ("mmc: sunxi: Support controllers that can use both old and new timings") Signed-off-by: Icenowy Zheng --- drivers/mmc/host/sunxi-mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 37

[PATCH 2/2] mmc: sunxi: fix new timings mode on A64 EMMC (MMC2) controller

it to true in the configuration struct. Fixes: 4fb3ce07eafa ("mmc: sunxi: Add EMMC (MMC2) controller compatible") Signed-off-by: Icenowy Zheng --- drivers/mmc/host/sunxi-mmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-m

Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

于 2017年8月4日 GMT+08:00 下午4:59:03, "Jernej Škrabec" <jernej.skra...@siol.net> 写到: >Hi Chen-Yu, > >Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a): >> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng <icen...@aosc.io> >wrote: >> &g

Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

于 2017年8月4日 GMT+08:00 下午4:59:03, "Jernej Škrabec" 写到: >Hi Chen-Yu, > >Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a): >> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng >wrote: >> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai

Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <w...@csie.org> 写到: >Hi, > >On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icen...@aosc.io> wrote: >> From: Jernej Skrabec <jernej.skra...@siol.net> >> >> When setting the HDMI clock of H3, th

Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai 写到: >Hi, > >On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng wrote: >> From: Jernej Skrabec >> >> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be >set. >> >> Add CLK_SET_RATE_PAREN

[PATCH v2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use an out-of-band interrupt pin instead of SDIO in-band interrupt. Add the device tree binding of this chip, in order to make it possible to add this interrupt pin to device trees. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use an out-of-band interrupt pin instead of SDIO in-band interrupt. Add the device tree binding of this chip, in order to make it possible to add this interrupt pin to device trees. Signed-off-by: Icenowy Zheng --- Changes

Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

gt;> > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng >> > >> > napisal(a): >> >> Allwinner H3 features a "Display Engine 2.0". >> >> >> >> Add device tree bindings for the following parts: >> >> - H3 TCO

Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

于 2017年8月3日 GMT+08:00 上午3:06:26, "Jernej Škrabec" 写到: >Hi, > >Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io >napisal(a): >> 在 2017-08-02 12:53，Jernej Škrabec 写道： >> >> > Hi Icenowy, >> > >> > Dne torek, 01. avg

[PATCH] pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base

kernel.org Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index c86d3c42a905..496ba34e1f5f 100644 --- a

[PATCH] pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base

kernel.org Signed-off-by: Icenowy Zheng --- drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index c86d3c42a905..496ba34e1f5f 100644 --- a/drivers/pinctrl/sunxi/pin

[PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

Allwinner H3 features a "Display Engine 2.0". Add device tree bindings for the following parts: - H3 TCONs - H3 Mixers - H3 Display engine Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../bindings/display/sunxi/sun4i-drm.txt | 25 ++ 1

[PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

Allwinner H3 features a "Display Engine 2.0". Add device tree bindings for the following parts: - H3 TCONs - H3 Mixers - H3 Display engine Signed-off-by: Icenowy Zheng --- .../bindings/display/sunxi/sun4i-drm.txt | 25 ++ 1 file changed, 21 insert

[PATCH 02/13] drm: sun4i: add support for H3 mixers

From: Icenowy Zheng <icen...@aosc.xyz> Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels, and the other has 1 VI and 1 UI. There's also some graphics post-process function that is missing on mixer1, however, as we currently support none of these functions, th

[PATCH 02/13] drm: sun4i: add support for H3 mixers

From: Icenowy Zheng Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels, and the other has 1 VI and 1 UI. There's also some graphics post-process function that is missing on mixer1, however, as we currently support none of these functions, the only difference that is shown

[PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC

Orange Pi PC board has a HDMI-A port connected to the HDMI controller of Allwinner H3 SoC. Enable the HDMI output in Orange Pi PC device tree. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16 1 file changed, 16 inse

[PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC

Orange Pi PC board has a HDMI-A port connected to the HDMI controller of Allwinner H3 SoC. Enable the HDMI output in Orange Pi PC device tree. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch

[PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller

The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific glues. Add the related device nodes. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/ar

[PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller

The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific glues. Add the related device nodes. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3

[PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3

From: Jernej Skrabec Allwinner H3 features DesignWare HDMI Transmitter paired with custom PHY. For now, only video is supported by the driver. However, audio and CEC are also supported by the hardware. Signed-off-by: Jernej Skrabec ---

[PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3

From: Jernej Skrabec Allwinner H3 features DesignWare HDMI Transmitter paired with custom PHY. For now, only video is supported by the driver. However, audio and CEC are also supported by the hardware. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/Kconfig | 9 +

[PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

From: Jernej Skrabec <jernej.skra...@siol.net> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set. Add CLK_SET_RATE_PARENT flag for H3 HDMI clock. Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- dr

[PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

From: Jernej Skrabec When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set. Add CLK_SET_RATE_PARENT flag for H3 HDMI clock. Signed-off-by: Jernej Skrabec Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver

From: Jernej Skrabec Some platform glues of DesignWare HDMI controller require some initialization to be performed before probing the main HDMI controller. Add a pre_init function for this kind of work. Signed-off-by: Jernej Skrabec ---

[PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver

From: Jernej Skrabec Some platform glues of DesignWare HDMI controller require some initialization to be performed before probing the main HDMI controller. Add a pre_init function for this kind of work. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++

[PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi

From: Jernej Skrabec Some custom phys don't support hpd interrupts. Add support for polling such events. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-)

[PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi

From: Jernej Skrabec Some custom phys don't support hpd interrupts. Add support for polling such events. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git

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