[PATCH v5 07/11] drm/sun4i: Add compatible string for V3s display engine

Allwinner V3s features the new "Display Engine 2.0", which can now also be driven with our subdrivers in sun4i-drm. Add the compatible string for in sun4i_drv.c, in order to make the display engine and its components probed. Signed-off-by: Icenowy Zheng <icen...@aosc.io> ---

[PATCH v5 03/11] dt-bindings: add bindings for DE2 on V3s SoC

Allwinner V3s SoC have a display engine which have a different pipeline with older SoCs. Add document for it (new compatibles and the new "mixer" part). Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v4: - Remove

[PATCH v5 08/11] drm/sun4i: tcon: add support for V3s TCON

Allwinner V3s SoC features a TCON without channel 1. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++- drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/g

[PATCH v5 00/11] Initial Allwinner Display Engine 2.0 Support

, but still not so usable because of some problem). ) Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts to discover the internal of DE2! [1] https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html Icenowy Zheng (11): dt-bindings: add binding for the Allwinner DE2 CCU

[PATCH v5 01/11] dt-bindings: add binding for the Allwinner DE2 CCU

Allwinner "Display Engine 2.0" contains some clock controls in it. In order to add them as clock drivers, we need a device tree binding. Add the binding here. Also add the device tree binding headers. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v5: - Moved dt

[PATCH v5 02/11] clk: sunxi-ng: add support for DE2 CCU

The "Display Engine 2.0" in Allwinner newer SoCs contains a clock management unit for its subunits, like the DE CCU in A80. Add a sunxi-ng style driver for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v5: - Removed dt-bindings headers (they're now in patch 1

[PATCH v5 05/11] drm/sun4i: abstract a engine type

.c) should be built. As we removed the codes in CRTC code that directly call the layer code, we can now extract the layer part and combine it with the backend part into a new module, sun4i-backend.ko. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v5: - Really made a sunxi_en

[PATCH v5 09/11] ARM: dts: sun8i: add DE2 nodes for V3s SoC

Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON which have RGB LCD output. Add device nodes for it as well as the TCON. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 87 1

[PATCH v5 11/11] [DO NOT MERGE] ARM: dts: sun8i: enable LCD panel of Lichee Pi Zero

A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi. This commit connects this panel to Lichee Pi Zero. Lichee Pi also provides a 800x480 panel without accurate model number, so do not merge this patch. It will finally come as device tree overlay. Signed-off-by: Icenowy Zheng

[PATCH v5 10/11] ARM: dts: sun8i: add pinmux for LCD pins of V3s SoC

Allwinner V3s SoC features a set of pins that have functionality of RGB LCD, the pins are at different pin ban than other SoCs. Add pinctrl node for them. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 9 + 1 file changed, 9 insertions(+)

[PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts

As we added USB0 route auto switching support for A64, add related device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the pmu0 memory area for PHY). Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 +

[PATCH 0/2] pmu0 MMIO region for A64 USB PHY

his region in 4.11. Icenowy Zheng (2): dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 arm64: allwinner: a64: add pmu0 regs for USB PHY Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++ 2 files

[PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change

and EHCI/OHCI controllers for USB0. The third patch enabled EHCI0/OHCI0 for Pine64 board. This patchset should go in 4.11 as Maxime Ripard suggested. Icenowy Zheng (3): dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 arm64: allwinner: a64: add USB0 OHCI/EHCI related

[PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

From: Icenowy Zheng <icen...@aosc.xyz> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allw

[PATCH v2 00/11] AXP803 PMIC support for Pine64

for other AXPs. PATCH 10 enabled the regulators on Pine64. PATCH 11 enabled Wi-Fi support on Pine64, which required DLDO4 and ELDO1 regulators. Icenowy Zheng (11): arm64: allwinner: a64: enable RSB on A64 arm64: allwinner: a64: add NMI controller on A64 dt-bindings: add device tree binding

[PATCH v2 02/11] arm64: allwinner: a64: add NMI controller on A64

Allwinner A64 SoC features a NMI controller, which is usually connected to the AXP PMIC. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v2: - Added Chen-Yu's ACK. arch/arm64/boot/dts/allwinner/sun50i-

[PATCH v2 01/11] arm64: allwinner: a64: enable RSB on A64

Allwinner A64 have a RSB controller like the one on A23/A33 SoCs. Add it and its pinmux. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v2: - Removed bonus properties in pio node. - Added Chen-Yu's ACK. arch/arm64/boot/dts/allw

[PATCH v2 11/11] arm64: allwinner: a64: enable Wi-Fi for Pine64

The Wi-Fi modules of Pine64 is powered via DLDO4 and ELDO1 (the latter one provides I/O voltage). Add device node for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16 1 file changed, 16 insertions(+) diff

[PATCH v2 09/11] arm64: allwinner: a64: add DTSI file for AXP803 PMIC

As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it, like the old DTSI files for AXP20x/22x, for the common parts of the PMIC. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/axp803.dtsi | 150 ++ 1 file change

[PATCH] arm64: allwinner: h5: add support for Orange Pi Prime board

Orange Pi Prime is a new Allwinner H5-based SBC by Xunlong. It's like a Orange Pi Plus 2E with H3 replaced with H5, eMMC replaced with onboard SPI NOR Flash and wireless card changed to Realtek RTL8723BS (with Bluetooth functionality). Signed-off-by: Icenowy Zheng <icen...@aosc.io> ---

[PATCH v2 08/11] mfd: axp20x: add axp20x-regulator cell for AXP803

As axp20x-regulator now supports AXP803, add a cell for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/mfd/axp20x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 2268a6a9aa2c..08b9bbd5bd71 100644 --- a/drivers/mfd/ax

[PATCH v2 07/11] regulator: axp20x-regulator: add support for AXP803

AXP803 PMIC also have a series of regulators (DCDCs and LDOs) controllable via I2C/RSB bus. Add support for them. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Place AXP803 codes before AXP806/809 ones. - Fixed some errors in regulator description. - Reuse AXP803

[PATCH v2 10/11] arm64: allwinner: a64: enable AXP803 regulators for Pine64

Add support of AXP803 regulators in the Pine64 device tree, in order to enable many future functionalities, e.g. Wi-Fi. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 + 1 file changed, 109 insertions(+) diff

[PATCH v2 04/11] mfd: axp20x: support AXP803 variant

AXP803 is a new PMIC chip produced by X-Powers, usually paired with A64 via RSB bus. The PMIC itself is like AXP288, but with RSB support and dedicated VBUS and ACIN. Add support for it in the axp20x mfd driver. Currently only power key function is supported. Signed-off-by: Icenowy Zheng <i

[PATCH v2 05/11] arm64: allwinner: a64: add AXP803 node to Pine64 device tree

The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC. Add its device node. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/all

[PATCH v2 03/11] dt-bindings: add device tree binding for X-Powers AXP803 PMIC

AXP803 is a PMIC produced by Shenzhen X-Powers, with either I2C or RSB bus. Add a compatible for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v2: - Place AXP803 before AXP806/809. - Added Chen-Yu's ACK. Documentatio

[PATCH v2 06/11] dt-bindings: add AXP803's regulator info

AXP803 have the most regulators in currently supported AXP PMICs. Add info for the regulators in the dt-bindings document. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Place AXP803 regulators before AXP806/809 ones. Documentation/devicetree/bindings/mfd/axp20x.tx

[PATCH 2/2] clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value

The CLK_NUMBER value of PRCM CCU is wrongly set to (CLK_APB0_PWD + 1), which prevented the IR mod clock from being set up. Change it to (CLK_IR + 1) in order to correctly get IR mod set up. Fixes: cdb8b80b6093 ("clk: sunxi-ng: add support for PRCM CCUs") Signed-off-by: Icenowy Z

[PATCH 1/2] clk: sunxi-ng: fix PRCM CCU ir clk parent

The first parent of ir clk in PRCM CCU is wrongly written as "osc32K" instead of "osc32k". Change it to "osc32k". Fixes: cdb8b80b6093 ("clk: sunxi-ng: add support for PRCM CCUs") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/su

Linux next-20170407 failed to build on ARM due to usage of mod in btrfs code

Hello everyone, Today I tried to build a kernel with btrfs enabled on ARM, then when linking I met such an error: ``` fs/built-in.o: In function `scrub_bio_end_io_worker': acl.c:(.text+0x2f0450): undefined reference to `__aeabi_uldivmod' fs/built-in.o: In function `scrub_extent_for_parity':

Re: [PATCH v4 05/11] drm/sun4i: abstract a engine type

于 2017年4月18日 GMT+08:00 下午4:55:48, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >Hi, > >Thanks for that rework. > >On Sun, Apr 16, 2017 at 08:08:43PM +0800, Icenowy Zheng wrote: >> As we are going to add support for the Allwinner DE2 engine in >sun4i-drm &

Re: sun50i-a64-pinctrl WARN_ON drivers/base/dd.c:349

于 2017年4月18日 GMT+08:00 下午3:25:05, Tejun Heo 写到: >Hello, > >On Mon, Apr 03, 2017 at 12:48:16AM +0100, André Przywara wrote: >> So I see this problem easily now - on every boot - with an unpatched >> 4.11-rc3 kernel and the (arm64) defconfig on a Pine64 or BananaPi >M64. >> I

Re: [linux-sunxi] Re: [PATCH v3 02/12] arm64: allwinner: a64: add NMI controller on A64

于 2017年4月18日 GMT+08:00 下午3:00:16, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Mon, Apr 17, 2017 at 07:57:37PM +0800, Icenowy Zheng wrote: >> Allwinner A64 SoC features a NMI controller, which is usually >connected >> to the AXP PMIC. >> >> A

Re: [PATCH v4 06/11] drm/sun4i: add support for Allwinner DE2 mixers

于 2017年4月18日 GMT+08:00 下午5:00:47, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Sun, Apr 16, 2017 at 08:08:44PM +0800, Icenowy Zheng wrote: >> Allwinner have a new "Display Engine 2.0" in their new SoCs, which >comes >> with mixers to do graphic proc

Re: [linux-sunxi] [PATCH v3 09/12] mfd: axp20x: add axp20x-regulator cell for AXP803

于 2017年4月18日 GMT+08:00 下午6:38:09, Chen-Yu Tsai <w...@csie.org> 写到: >On Mon, Apr 17, 2017 at 7:57 PM, Icenowy Zheng <icen...@aosc.io> wrote: >> As axp20x-regulator now supports AXP803, add a cell for it. >> >> Signed-off-by: Icenowy Zheng <icen...@aosc.io

[PATCH v4 03/10] irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC

Add support for the newly imported compatible for the A64 R_INTC in irq-sunxi-nmi driver Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- New patch in v4, which is part of NMI refactor. drivers/irqchip/irq-sunxi-nmi.c | 13 + 1 file changed, 13 insertions(+) diff --git a/d

[PATCH v4 06/10] regulator: axp20x-regulator: add support for AXP803

AXP803 PMIC also have a series of regulators (DCDCs and LDOs) controllable via I2C/RSB bus. Add support for them. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v4: - Fixed somewhere which mention AXP806 before 803. Changes in

[PATCH v4 05/10] arm64: allwinner: a64: add AXP803 node to Pine64 device tree

The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC. Add its device node. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/all

[PATCH v4 07/10] mfd: axp20x: add axp20x-regulator cell for AXP803

As axp20x-regulator now supports AXP803, add a cell for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v4: - Added a trailing comma for new cell, for easier further cell addition. Changes in v3: - Make the new cell one-liner.

[PATCH v4 04/10] arm64: allwinner: a64: add NMI (R_INTC) controller on A64

Allwinner A64 SoC features a R_INTC controller, which controls the NMI line, and this interrupt line is usually connected to the AXP PMIC. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v4: - Changes it to use R_INTC binding and change node label to

[PATCH v4 00/10] AXP803 PMIC support for Pine64

in Pine64 device tree. PATCH 10 enables Wi-Fi for Pine64. Icenowy Zheng (10): arm64: allwinner: a64: enable RSB on A64 irqchip/sunxi-nmi: add A64 R_INTC to the binding doc irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC arm64: allwinner: a64: add NMI (R_INTC) controller on A64 arm64

[PATCH v4 01/10] arm64: allwinner: a64: enable RSB on A64

Allwinner A64 have a RSB controller like the one on A23/A33 SoCs. Add it and its pinmux. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v2: - Removed bonus properties in pio node. - Added Chen-Yu's ACK. arch/arm64/boot/dts/allw

[PATCH v4 10/10] arm64: allwinner: a64: enable Wi-Fi for Pine64

as GPIO (so it's with 2.0mm pitch, not 2.54mm as other GPIO headers). Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts

[PATCH v4 02/10] irqchip/sunxi-nmi: add A64 R_INTC to the binding doc

The A31 NMI driver seems to be using wrong base address. As we're going to convert to use a correct NMI base address (and correctly name it to R_INTC as the datasheet suggests), add a new compatible string for the "correct" R_INTC, which we will use for A64 SoC. Signed-off-by: Ice

[PATCH v4 09/10] arm64: allwinner: a64: enable AXP803 regulators for Pine64

Add support of AXP803 regulators in the Pine64 device tree, in order to enable many future functionalities, e.g. Wi-Fi. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 + 1 file changed, 109 insertions(+) diff

[PATCH v4 08/10] arm64: allwinner: a64: add DTSI file for AXP803 PMIC

As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it, like the old DTSI files for AXP20x/22x, for the common parts of the PMIC. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v4: - Re-sorted the nodes. arch/arm64/boot/dts/allwinner/axp803.dtsi

[PATCH] pinctrl: sunxi: rename R_PIO i2c pin function name

in mainline kernel so I think it's safe to change the name. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 4 ++-- 3 files changed, 6 ins

Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

gt;> > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng >> > >> > napisal(a): >> >> Allwinner H3 features a "Display Engine 2.0". >> >> >> >> Add device tree bindings for the following parts: >> >> - H3 TCO

[PATCH v2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use an out-of-band interrupt pin instead of SDIO in-band interrupt. Add the device tree binding of this chip, in order to make it possible to add this interrupt pin to device trees. Signed-off-by: Icenowy Zheng <icen...@aosc

Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <w...@csie.org> 写到: >Hi, > >On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icen...@aosc.io> wrote: >> From: Jernej Skrabec <jernej.skra...@siol.net> >> >> When setting the HDMI clock of H3, th

Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

于 2017年8月4日 GMT+08:00 下午4:59:03, "Jernej Škrabec" <jernej.skra...@siol.net> 写到: >Hi Chen-Yu, > >Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a): >> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng <icen...@aosc.io> >wrote: >> &g

[PATCH v5] clk: sunxi-ng: support R40 SoC

Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v5: - Added TODO's for PLL constraints. - Forced OHCI12M mux to 0. - Changed "

Re: [linux-sunxi] [PATCH 1/3] arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node

于 2017年8月10日 GMT+08:00 上午11:56:02, Chen-Yu Tsai <w...@csie.org> 写到: >Hi, > >On Sat, Jul 22, 2017 at 10:28 AM, Icenowy Zheng <icen...@aosc.io> >wrote: >> The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet >> link. >> >> Add the eth

Re: [linux-sunxi] [PATCH v4] arm64: allwinner: a64: Add initial NanoPi A64 support

于 2017年8月11日 GMT+08:00 下午8:31:43, Jagan Teki 写到: >From: Jagan Teki > >NanoPi A64 is a new board of high performance with low cost >designed by FriendlyElec., using the Allwinner A64 SOC. As AXP803 regulators support now entered linux-next,

[PATCH v4 0/3] Allwinner R40 CCU driver

). Patch 2 adds postdiv support for NKM type clock, which is needed for pll-sata (with a postdiv of 6). Patch 3 is the main patch, which adds the support for R40 CCU. Icenowy Zheng (2): clk: sunxi-ng: nkm: add support for fixed post-divider clk: sunxi-ng: support R40 SoC Priit Laes (1): clk: sunxi

[PATCH v4 1/3] clk: sunxi-ng: div: Add support for fixed post-divider

From: Priit Laes SATA clock on sun4i/sun7i is of type (parent) / M / 6 where 6 is fixed post-divider. Signed-off-by: Priit Laes --- It's based on the patch in v6 of the A10/A20 CCU patchset, but with ccu_div_round_rate fixed. drivers/clk/sunxi-ng/ccu_div.c |

[PATCH v4 3/3] clk: sunxi-ng: support R40 SoC

Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v4: - Removed usb-ohci-12M mux clocks. - Removed unused (and not in user manual) a

[PATCH v4 2/3] clk: sunxi-ng: nkm: add support for fixed post-divider

SATA PLL on Allwinner R40 is of type (parent) * N * K / M / 6 where 6 is the fixed post-divider. Add post-divider support for NKM type clock. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu_nkm.c | 22 +++--- drivers/clk/sunxi-ng/ccu_nkm.h | 2

[PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

, and allow new device trees to use correct 3 IRQ banks. Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 26 +++--- 1 file changed, 23 insertions

[PATCH 0/2] Allwinner H5 IRQ fixes

The current pinctrl code and H5 device tree have an error: the bank number of IRQs are wrongly set to 2, which makes PG bank interrupts not usable. Fixes in both the pinctrl driver and the device tree. Please apply the DT fix after applying the pinctrl fix. Icenowy Zheng (2): pinctrl: sunxi

[PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

arm64: allwinner: h5: add Allwinner H5 .dtsi") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi in

[PATCH] ARM: sun8i: a33: add dts for Q8 tablets with different resolution

driver still has some problems to support the LCDs, the real LCD device nodes are not added to the device tree files. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dt

Re: [linux-sunxi] Re: [PATCH 1/2] pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

于 2017年7月10日 GMT+08:00 下午4:44:00, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Fri, Jul 07, 2017 at 07:21:19AM +0800, icen...@aosc.io wrote: >> 在 2017-07-07 04:46，Maxime Ripard 写道： >> > Hi, >> > >> > On Thu, Jul 06, 2017 at 10:28:21PM +0800

Re: [PATCH 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

于 2017年7月7日 GMT+08:00 下午5:18:38, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Fri, Jul 07, 2017 at 07:13:30AM +0800, Icenowy Zheng wrote: >> >> >> 于 2017年7月7日 GMT+08:00 上午4:50:30, Maxime Ripard ><maxime.rip...@free-electrons.com> 写到: >>

[PATCH] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use an out-of-band interrupt pin instead of SDIO in-band interrupt. Add the device tree binding of this chip, in order to make it possible to add this interrupt pin to device trees. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v2 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Fixed some lines' format. drivers/pinctrl/sunxi/K

[PATCH v2 1/2] pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

heet V1.41 contain this pin function, and it's discovered during implementing R40 pinctrl driver. Add it to the driver. As we now merged A20 pinctrl driver to the A10 one, we need to only fix the A10 driver now. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Commit

[PATCH v2 0/2] Last step to working Allwinner R40 pinctrl

, with fixes suggested by Chen-Yu and Maxime. Icenowy Zheng (2): pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver pinctrl: sunxi: add support of R40 to A10 pinctrl driver drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 274

[PATCH] dt-bindings: add compatible string of Allwinner H5 Mali-450 MP4 GPU

Allwinner H5 has a Mali-450 MP4 GPU, which has a reset line like other Allwinner SoCs with Mali Utgard, but it's a Mali-450, so it needs a new compatible. Add the new compatible to Mali Utgard binding document. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bi

Re: [linux-sunxi] [PATCH v6 8/9] arm64: allwinner: a64: enable AXP803 regulators for Pine64

于 2017年7月18日 GMT+08:00 上午10:58:52, Chen-Yu Tsai <w...@csie.org> 写到: >On Fri, May 19, 2017 at 4:55 PM, Andre Przywara ><andre.przyw...@arm.com> wrote: >> Hi, >> >> On 19/05/17 09:29, Icenowy Zheng wrote: >>> >>> >>> 于 2017年5月19日 G

[PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

Banana Pi M64 board uses an AXP803 PMIC. Enable the PMIC and its regulators. As we have now proper regulators support, missing or dummy regulators are changed to the correct ones. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts

[PATCH 1/3] arm64: allwinner: a64: enable USB host controller for BPi M64

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts

[PATCH 3/3] arm64: allwinner: a64: add proper support for the Wi-Fi on BPi M64

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m

Re: [linux-sunxi] [PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

于 2017年7月21日 GMT+08:00 下午3:42:07, Chen-Yu Tsai <w...@csie.org> 写到: >On Fri, Jul 21, 2017 at 7:07 AM, Icenowy Zheng <icen...@aosc.io> wrote: >> Banana Pi M64 board uses an AXP803 PMIC. >> >> Enable the PMIC and its regulators. >> >> As we have no

[PATCH v3 0/2] Last step to working Allwinner R40 pinctrl

, with fixes suggested by Chen-Yu and Maxime. Icenowy Zheng (2): pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver pinctrl: sunxi: add support of R40 to A10 pinctrl driver drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 274

[PATCH v2 2/2] arm64: allwinner: a64: add AXP803 PMIC support to SoPine and the baseboard

The SoPine SoM has an AXP803 PMIC connected to the RSB bus of the A64 SoC, and the regulators of the PMIC are used both on the SoM itself and on the official baseboard Add related device tree parts to the SoPine SoM DTSI file and the baseboard DT. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v2 1/2] arm64: allwinner: a64: enable AXP803 regulators for Pine64

Add support of AXP803 regulators in the Pine64 device tree. The phy-supply regulator is also set in EMAC device node, in order to prevent Ethernet regression by regulator get disabled by regulator framework. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Change t

[PATCH v2 0/2] AXP803 regulators support for Pine64 and SoPine

regulators in v1 are removed. Icenowy Zheng (2): arm64: allwinner: a64: enable AXP803 regulators for Pine64 arm64: allwinner: a64: add AXP803 PMIC support to SoPine and the baseboard .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 102 + .../dts/allwinner/sun50i-a64

[PATCH v3 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v3: - Fixed a m

[PATCH v3 1/2] pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

iver of its own") Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v3: - Added Chen-Yu's review tag. - Added fix tag suggested by Chen-Yu. Changes in v2: - Commit message changes. (mentioning the datasheet versions which are us

[PATCH 3/3] arm64: allwinner: a64: add ethernet0 alias for SoPine EMAC node

The SoPine official baseboard uses the A64 chip's EMAC to provide an Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-

[PATCH 1/3] arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node

The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m

[PATCH 0/3] Add ethernet0 alias for several A64 boards

t0 aliases to these boards. I hope this patchset can be queued in 4.13, otherwise 4.13 kernels won't get non-volatile MAC addresses, and will use random ones instead, which is annoying to many users. Icenowy Zheng (3): arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node arm64: allw

[PATCH 2/3] arm64: allwinner: a64: add ethernet0 alias for Pine64 EMAC node

The Pine64 (including the Plus models) board uses the A64 chip's EMAC to provide Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/

[PATCH v2 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

Banana Pi M64 board uses an AXP803 PMIC. Enable the PMIC and its regulators. As we have now proper regulators support, missing or dummy regulators are changed to the correct ones. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Changed vdd-cpux constraints. - Added v

[PATCH v2 3/3] arm64: allwinner: a64: add proper support for the Wi-Fi on BPi M64

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m

[PATCH v2 1/3] arm64: allwinner: a64: enable USB host controller for BPi M64

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v2: - Added Chen-Yu's review tag. arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinne

Re: [PATCH 0/3] Add ethernet0 alias for several A64 boards

> > On Sat, Jul 22, 2017 at 10:28:49AM +0800, Icenowy Zheng wrote: >> > > > Allwinner A64 SoC has an EMAC which is used to provide Ethernet >> > > > function on several boards. >> > > > >> > > > The EMAC itself doesn't have a

[PATCH 01/10] dt-bindings: add binding for the SY8160A voltage regulator

From: Ondrej Jirman <meg...@megous.com> SY8106A is an I2C-controlled adjustable voltage regulator made by Silergy Corp. Add its device tree binding. Signed-off-by: Ondrej Jirman <meg...@megous.com> [Icenowy: Change commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io>

[PATCH 02/10] regulator: add support for SY8106A regulator

nowy: Change commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/regulator/Kconfig | 8 +- drivers/regulator/Makefile| 2 +- drivers/regulator/sy8106a-regulator.c | 163 ++ 3 files changed, 171 insertions(+), 2 de

[PATCH 00/10] A trial to Allwinner H3 DVFS support

mentioned. Chen-Yu Tsai (1): clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change Icenowy Zheng (4): clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 cpufreq: dt: Add support for some new Allwinner SoCs ARM: sun8i: h3: add operating-points-v2 table for CPU ARM

[PATCH 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller

From: Ondrej Jirman <meg...@megous.com> Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank. Add support for it in the device tree. Signed-off-by: Ondrej Jirman <meg...@megous.com> [Icenowy: Change to use r_ccu and change pinmux node name] Signed-off-by: Icenowy Zheng <

[PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node

] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 6f2162608006..b240099bc865 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +

[PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

n-Yu Tsai <w...@csie.org> Tested-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 62e4f0d2b2fc..406d0aac9fd6 100644

[PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs

Some new Allwinner SoCs get supported in the kernel after the compatibles are added to cpufreq-dt-platdev driver. Add their compatible strings in the cpufreq-dt-platdev driver. Cc: "Rafael J. Wysocki" <r...@rjwysocki.net> Cc: Viresh Kumar <viresh.ku...@linaro.org> Signed

[PATCH 08/10] ARM: sun8i: h3: add operating-points-v2 table for CPU

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3.dtsi | 38 +- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..a0cee17fe44b

[PATCH 09/10] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board

of this regulator and set the cpu's cpu-supply property to it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/bo

[PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC

atch, slight changes and change commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 19 +++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-ora

[PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

The CPUX clock, which is the main clock of the ARM core on Allwinner H3, can be adjusted by changing the frequency of the PLL_CPUX clock. Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX clock can be adjusted when adjusting the CPUX clock. Signed-off-by: Icenowy Zheng <i

Re: [linux-sunxi] [PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

于 2017年7月23日 GMT+08:00 下午11:15:04, Chen-Yu Tsai <w...@csie.org> 写到: >On Fri, Jul 21, 2017 at 7:38 PM, <icen...@aosc.io> wrote: >> 在 2017-07-21 15:49，Chen-Yu Tsai 写道： >>> >>> On Fri, Jul 21, 2017 at 3:44 PM, Icenowy Zheng <icen...@aosc.io> >wrote

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