: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (1):
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
arch/arm/boot/dts/Makefile| 4 +-
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++
arch/arm/boot/dts/sun8i-r40.dtsi
retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Dropped all max-frequency properties in MMC nodes.
Changes in v2
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not use
control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Added 3.3V vqmmc regulator for mmc2 (eMMC).
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boo
于 2017年10月10日 GMT+08:00 上午5:03:40, Maxime Ripard
写到:
>On Sun, Oct 08, 2017 at 04:29:02AM +0000, Icenowy Zheng wrote:
>> From: Icenowy Zheng
>>
>> Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
>>
>> Add support for the host ports
于 2017年10月10日 GMT+08:00 上午5:04:07, Maxime Ripard
写到:
>On Sun, Oct 08, 2017 at 04:29:03AM +0000, Icenowy Zheng wrote:
>> On newer revisions of the Banana Pi M2 Ultra boards, the 5V power
>output
>> (used by HDMI, SATA and USB) is controller via a GPIO.
>>
>>
Add the operating table for the CPU (ARM cores) on Allwinner A64 SoC.
OPPs higher to 816MHz is temporarily dropped, to prevent overheat on
boards with AXP803 support and undervoltage on boards without AXP803
support.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64
driver of A64, and the remaining patches
set up the device tree bits of the DVFS on Pine64.
Icenowy Zheng (3):
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
arm64: allwinner: a64: add CPU opp table
arm64: allwinner: a64: set CPU regulator for Pine64
.../arm64/boot/dts/allwinner
The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.
Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.
Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-b
The DCDC2 regulator of the AXP803 PMIC is used for the voltage scaling
of the ARM cores on the A64 SoC.
Add this definition to enable it on Pine64.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch
于 2017年9月25日 GMT+08:00 下午5:11:57, Quentin Schulz
写到:
>Hi Icenowy,
>
>On 20/09/2017 17:18, Icenowy Zheng wrote:
>> AXP803 PMIC features AC/USB/Battery power supplies.
>>
>> As we have now the device tree bindings for them, add device tree
>> nodes for them.
&g
于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
写到:
>Hi,
>
>On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
>> This patchset imports simple DVFS support for Allwinner A64 SoC.
>>
>> As the thermal sensor driver is not yet implemented and some board
于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard
写到:
>On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:
>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
> 写到:
>> >Hi,
>> >
>> >On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
, then adds the interrupt to the device tree of
Orange Pi Zero.
Icenowy Zheng (1):
dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
Sergey Matyukevich (1):
ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero
.../bindings/net/wireless/allwinner,xr819.txt | 38
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
Acked-by: Rob
-by: Icenowy Zheng
---
Changes in v3 by Icenowy:
- Change the compatible string vendor prefix to "allwinner".
- Modify the commit message.
Changes in v2 by Sergey:
- Adds the compatible string.
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 3 +++
1 file changed, 3 insertions(+)
di
retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change the MMC frequencies to conservative verified values.
- Add
: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (1):
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
arch/arm/boot/dts/Makefile| 4 +-
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++
arch/arm/boot/dts/sun8i-r40.dtsi
control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boo
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not use
于 2017年9月28日 GMT+08:00 下午11:12:25, Maxime Ripard
写到:
>On Thu, Sep 28, 2017 at 09:25:42AM +0000, Icenowy Zheng wrote:
>> +&mmc2 {
>> +vmmc-supply = <®_dcdc1>;
>> +bus-width = <8>;
>> +non-removable;
>> +status = "okay"
于 2017年9月28日 GMT+08:00 下午11:11:03, Maxime Ripard
写到:
>Hi,
>
>On Thu, Sep 28, 2017 at 09:25:41AM +, Icenowy Zheng wrote:
>> +/*
>> + * The max-frequency properties in all MMC controller nodes
>> + * are conservative values pro
于 2017年9月20日 GMT+08:00 下午3:52:23, Maxime Ripard
写到:
>On Mon, Sep 18, 2017 at 03:47:25PM +, icen...@aosc.io wrote:
>> 在 2017-09-18 16:30，Maxime Ripard 写道：
>> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:
>> > > 于 2017年9月18日 GMT+08:00 下午3:3
patchset because it's not
present on Pine series boards.
In order to enable battery monitoring the ADC for battery is also enabled
for AXs.
In order to enable battery monitoring the ADC for battery is also enabled
for AXP803.
Icenowy Zheng (7):
dt-bindings: add compatibles for AXP803 Batter
AXP803 Battery/USB power supplies. For AC
power supply the one on AXP803 is compatible with the one on AXP22x.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/power/supply/axp20x_battery.txt | 1 +
Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt | 1 +
2
The ADC rate setup on AXP803 is more complex than AXP20x/22x.
As it's not a necessary setup, allow it to be skipped, to allow simpler
AXP803 support now.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/axp20x_adc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --
GPADC channels
are complex and will be support after more investigation.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/axp20x_adc.c | 108 +++
1 file changed, 108 insertions(+)
diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
The AXP803 PMIC has battery support like other AXP PMICs, but with
different definition of max target charging voltage and constant
charging current.
Add support for AXP803 battery in axp20x-battery driver.
Signed-off-by: Icenowy Zheng
---
drivers/power/supply/axp20x_battery.c | 88
As we have now support for AXP803 ADC/Battery, and the AC Power part of
AXP803 is the same as AXP22x, add MFD cells for these drivers.
Signed-off-by: Icenowy Zheng
---
drivers/mfd/axp20x.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd
d-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..955f392af6a2 100644
--- a/arch/
AXP803 PMIC features AC/USB/Battery power supplies.
As we have now the device tree bindings for them, add device tree
nodes for them.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot
于 2017年9月21日 GMT+08:00 下午10:46:21, Jonathan Cameron
写到:
>On Wed, 20 Sep 2017 23:18:07 +0800
>Icenowy Zheng wrote:
>
>> The AXP803 PMIC, used by most Allwinner A64 boards, features 3 power
>inputs:
>> AC, USB and Battery.
>>
>> This patchset adds support fo
The R40 SoC has a watchdog like the one on A20, in the timer memory zone
(which is also the same on A20).
Add the device tree node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
Currently the rtl8723bs driver will print "nolinked power save enter"
and "nolinked power save leave" per minute if it's not connected to any
network.
These messages are meaningless and annoying to regular users.
Hide them when it's not debugging.
Signed-off-b
于 2017年10月5日 GMT+08:00 下午2:58:01, Kalle Valo 写到:
>Icenowy Zheng writes:
>
>> 于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
>> 写到:
>>>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
>>>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>
于 2017年10月8日 GMT+08:00 上午6:37:46, "Levin, Alexander (Sasha Levin)"
写到:
>From: Icenowy Zheng
>
>[ Upstream commit c429ceb1e18252122ba96b52e689dcf87103c186 ]
>
>As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA
>driver should be allowed to be built
Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
drivers/phy/allwinner/phy-sun4i-usb.c | 12
2 files changed, 13 insertions
the two boards, and
the fifth and sixth patch finally adds USB host ports support.
Icenowy Zheng (6):
phy: sun4i-usb: add support for R40 USB PHY
ARM: sun8i: r40: add USB host port nodes for R40
ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
ARM: sun8i: v40: add 5V regulator for
From: Icenowy Zheng
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
1 file changed, 22 insertions
From: Icenowy Zheng
Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
Add support for the host ports in the DTSI file.
The OTG controller still cannot work with existing compatibles, and needs
more investigation. So it's not added yet.
Signed-off-by: Icenowy Zheng
---
sions.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.
Add regulator node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.
Enable it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arc
Allwinner R40 SoC has an AHCI SATA controller like the one in A10/A20,
but with a reset control and two dedicated VDD pins for this controller
(one 1.2v and one 2.5v).
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/ata/ahci_sunxi.c | 118
generic platform AHCI
controller binding document.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/ata/ahci-platform.txt | 1 -
.../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++
2 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644
于 2017年10月9日 GMT+08:00 下午3:18:09, Maxime Ripard
写到:
>On Fri, Oct 06, 2017 at 06:33:31AM +0000, Icenowy Zheng wrote:
>> In the CCU of the Allwinner R40 SoC, there's a GMAC configuration
>register,
>> which is intended to be accessed by the dwmac-sun8i driver. On SoCs
&
From: Icenowy Zheng
Pine64 have made an official baseboard when SoPine SoM is out.
The official baseboard is like the original Pine64 -- but with SD card
slot replaced with Pine64's eMMC module slot.
Add a device tree for SoPine with the baseboard.
Signed-off-by: Icenowy Zheng
---
From: Icenowy Zheng
SoPine is a SoM by Pine64, which have a gold finger compatible with the
slot of DDR3 SODIMM (signals are not compatible), and have an A64, an
AXP803, a LPDDR3 DRAM chip, a power led and a MicroSD slot on it.
The card detect pin of the MicroSD slot on the SoM is pulled down
Thus the TV
output shouldn't be defaultly enabled now.
Icenowy Zheng (11):
dt-bindings: update the binding for Allwinner H3 TVE support
drm: sun4i: add support for H3 mixers
drm: sun4i: ignore swapped mixer<->tcon connection for DE2
drm: sun4i: add support for H3's TCON
Allwinner H3 features a "DE2.0" and a TV Encoder.
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- The connection between H3 TCONs and H3 Mixers
- H3 TV Encoder
- H3 Display engine
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Changed endpoint reg def
The CLK_PLL_DE is needed to be referenced in device tree for H3, for
both forcing the parent of PLL_DE.
So export it to the device tree binding header.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +--
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++
2 files
.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Changes according to new dt bindings.
arch/arm/boot/dts/sun8i-h3.dtsi | 186
1 file changed, 186 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39
Orange Pi PC features a 3.5mm jack with TV output in it.
Enable the TV output.
As it currently do not have jack detection feature, do not merge this
patch.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 12
1 file changed, 12 insertions(+)
diff
they stands for the swapped
connection.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change to use new endpoint reg definition.
drivers/gpu/drm/sun4i/sun4i_drv.c | 45
drivers/gpu/drm/sun4i/sun4i_tcon.c | 61 --
driver
From: Icenowy Zheng
Allwinner H3 has two special TCONs, both come without channel0. And the
TCON1 of H3 has no special clocks even for the channel1.
Add support for these kinds of TCON.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Merged TCON0 and TCON1 quirks and compatibles.
drivers
Add a compatible string for H3 display engine in sun4i_drv code.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 775eee82d8a9..2003507b41a6 100644
_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 62e4f0d2b2fc..b6a1636c2f6b 10
Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
but has a internal fixed clock divider that divides the TCON1 clock
(called TVE clock in datasheet) by 11.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Quirk part rewritten.
drivers/gpu/drm/sun4i
The DE2 mixer can do color space correction needed by TV Encoder with
its DCSC sub-engine.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 35 +++
drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 +-
2 files changed, 40
From: Icenowy Zheng
Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI.
Add support for these two variants.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 ++
1 file changed, 18 insertions
hot-plugged in.
Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i")
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethe
于 2017年6月5日 GMT+08:00 上午2:46:24, "Jernej Škrabec" 写到:
>Hi,
>
>Dne nedelja, 04. junij 2017 ob 18:01:42 CEST je Icenowy Zheng
>napisal(a):
>> From: Icenowy Zheng
>>
>> Allwinner H3 has two special TCONs, both come without channel0. And
>the
>&g
于 2017年6月5日 GMT+08:00 下午3:53:50, Marc Zyngier 写到:
>On 05/06/17 06:57, Chen-Yu Tsai wrote:
>> Hi Marc,
>>
>> On Mon, May 22, 2017 at 10:25 PM, Chen-Yu Tsai wrote:
>>> On Mon, May 22, 2017 at 5:41 PM, Icenowy Zheng
>wrote:
>>>>
>>>>
This is a dedicated patchset of Allwinner V3s DMA support, which used
to be part of the audio codec support patchset.
It's a derivation of the DMA part of v3 of the codec patchset.
Icenowy Zheng (2):
dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk
dmaeng
From: Icenowy Zheng
Allwinner V3s has a DMA engine similar to the ones from A31, but with
fewer channels and DRQs.
Add support for it.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
Acked-by: Rob Herring
---
Changes since the original codec patchset v3:
- Added Rob'
From: Icenowy Zheng
Originally we enable a special gate bit when the compatible indicates
A23/33.
But according to BSP sources and user manuals, more SoCs will need this
gate bit.
So make it a common quirk configured in the config struct.
Signed-off-by: Icenowy Zheng
---
Changes since
This is the ASoC part of the Allwinner V3s audio codec support.
The audio codec is like the ones on A23/H3, but much simpler.
As it lacks two features that used to be common (MIC2 and LINEIN),
some structures are altered to exclude these features.
Icenowy Zheng (3):
ASoC: sun8i-codec-analog
: Icenowy Zheng
---
Changes in v4:
- Added TODO comment.
- Check the return value of sun8i_codec_analog_add_mixer().
sound/soc/sunxi/sun8i-codec-analog.c | 101 ++-
1 file changed, 100 insertions(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun8i-codec-analog.c
b
From: Icenowy Zheng
The V3s SoC features an analog codec with headphone support but without
mic2 and linein.
Add support for it.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
Acked-by: Rob Herring
---
Changes in v4:
- Added Chen-Yu's Reviewed-By.
- Added Rob's ACK.
Doc
From: Icenowy Zheng
The codec in the V3s is similar to the one found on the A31. One key
difference is the analog path controls are routed through the PRCM
block. This is supported by the sun8i-codec-analog driver, and tied
into this codec driver with the audio card's aux_dev.
In addition
于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai 写到:
>Hi,
>
>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng wrote:
>> From: Jernej Skrabec
>>
>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>set.
>>
>> Add CLK_SET_RATE_PARENT f
于 2017年8月4日 GMT+08:00 下午4:59:03, "Jernej Škrabec" 写到:
>Hi Chen-Yu,
>
>Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
>> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng
>wrote:
>> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai
Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use both
old and new timings")
Signed-off-by: Icenowy Zheng
---
drivers/mmc/host/sunxi-mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
ind
tting it to true in
the configuration struct.
Fixes: 4fb3ce07eafa ("mmc: sunxi: Add EMMC (MMC2) controller compatible")
Signed-off-by: Icenowy Zheng
---
drivers/mmc/host/sunxi-mmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/su
于 2017年8月6日 GMT+08:00 上午10:39:54, Chen-Yu Tsai 写到:
>On Sat, Aug 05, 2017 at 05:35:55AM +0800, Icenowy Zheng wrote:
>> The configuration struct of A64 EMMC(MMC2) compatible used to
>> have the needs_new_timings variable missing, which lead to NULL
>> pointer dereference now
d now.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v2:
- Added Chen-Yu's review tag.
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/
Banana Pi M64 board uses an AXP803 PMIC.
Enable the PMIC and its regulators.
As we have now proper regulators support, missing or dummy regulators
are changed to the correct ones.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Changed vdd-cpux constraints.
- Added vcc-1v2-hsic regulator
.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index ec72ca8c8b30
mainline kernel so I think it's safe to change the name.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 4 ++--
drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 4 ++--
drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 4 ++--
3 files changed, 6 insertions(+), 6 d
Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
both old and new timings")
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v2:
- Slightly adjusted the format of the Fixes: line/
- Added review tag from Chen-Yu.
drivers/mmc/host/
iver; this patch fixed probe defering when claiming
SRAM region.
Patch 3 adds the remapping code.
Patch 4 adds necessary codes for A64 SRAM C.
Icenowy Zheng (4):
dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C
drivers: soc: sunxi: fix error processing on base address when
Allwinner A64's display engine claims the SRAM C section to work.
Add support for the A64 SRAM controller and the SRAM C section of it.
Signed-off-by: Icenowy Zheng
---
drivers/soc/sunxi/sunxi_sram.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/soc/
-EPROBE_DEFER in the former situation, and ignored the latter
situation (which will lead to the kernel to panic).
Fix the behavior on abnormal base address processing when claiming.
Signed-off-by: Icenowy Zheng
---
drivers/soc/sunxi/sunxi_sram.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a
E, and for
Allwinner A64's SRAM C the needed register value to claim it to DE2 is
0, and the value that enables CPU's access to the SRAM is 1.
Add a value remapping in sunxi_sram_func structure, and let the
sunxi_sram_of_parse function set the remapped register value.
Signed-off-by: I
The display engine on Allwinner A64 wants to claim the SRAM C section.
Add a SRAM controller compatible for A64, and a SRAM section compatible
for its SRAM C.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/sram/sunxi-sram.txt | 9 +++--
1 file changed, 7 insertions
0/A20).
Patch 2 adds postdiv support for NKM type clock, which is needed for
pll-sata (with a postdiv of 6).
Patch 3 is the main patch, which adds the support for R40 CCU.
Icenowy Zheng (2):
clk: sunxi-ng: nkm: add support for fixed post-divider
clk: sunxi-ng: support R40 SoC
Priit Laes (1):
clk:
From: Priit Laes
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes
---
It's based on the patch in v6 of the A10/A20 CCU patchset, but with
ccu_div_round_rate fixed.
drivers/clk/sunxi-ng/ccu_div.c | 22 +++---
drivers
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x
SATA PLL on Allwinner R40 is of type (parent) * N * K / M / 6 where 6 is
the fixed post-divider.
Add post-divider support for NKM type clock.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu_nkm.c | 22 +++---
drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++
2 files changed, 21
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" cl
now due to no TVE)
The last 6 patches are only used for testing this patchset, and they're
going to be sent by Jernej Skrabec after this patchset is applied.
Icenowy Zheng (9):
dt-bindings: update the binding for Allwinner H3 DE2 support
drm: sun4i: add support for H3 mixers
drm: sun4i:
From: Icenowy Zheng
Allwinner H3 has two special TCONs without channel 0.
Add support for this kind of TCON.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +++---
drivers/gpu/drm/sun4i
Add a compatible string for H3 display engine in sun4i_drv code.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index fd99fe8a4df7..02c80bb7b385 100644
The CLK_PLL_DE is needed to be referenced in device tree for H3, for
both forcing the parent of PLL_DE.
So export it to the device tree binding header.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +--
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++
2 files
_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index d1ab0d713fa6..b1127e8629d9 10
As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.
The H5 pipeline has some differences and will be enabled later.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 170
From: Jernej Skrabec
Some custom phys don't support hpd interrupts. Add support for polling
such events.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.
From: Jernej Skrabec
Some platform glues of DesignWare HDMI controller require some
initialization to be performed before probing the main HDMI controller.
Add a pre_init function for this kind of work.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
inclu
From: Jernej Skrabec
When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
Signed-off-by: Jernej Skrabec
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Jernej Skrabec
Allwinner H3 features DesignWare HDMI Transmitter paired with custom
PHY.
For now, only video is supported by the driver. However, audio and CEC
are also supported by the hardware.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/Kconfig | 9 +
drivers/gp
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