From: Robert Richter
Generalize northbridge constraints code for family 10h so that later
we can reuse the same code path with other AMD processor families that
have the same northbridge event constraints.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu
x27;s review
* https://lkml.org/lkml/2012/11/16/484
* https://lkml.org/lkml/2012/11/26/162
V2:
Separate out Robert's patches, and add properly ordered certificate of
origins.
Jacob Shin (3):
perf, x86: Move MSR address offset calculation to architecture
specific files
perf, amd: Enable n
performance counters starting at 0xc0010240.
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event.h | 21 +---
arch/x86/kernel/cpu/perf_event_amd.c | 35 ++
2 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel
counters, and their indexes correspond to RDPMC ECX
values.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/cpufeature.h|2 +
arch/x86/include/asm/msr-index.h |2 +
arch/x86/include/asm/perf_event.h|9 +++
arch/x86/kernel/cpu/perf_event_amd.c | 131
From: Robert Richter
Code simplification. No functional changes.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event_amd.c | 68 +-
1 file changed, 26 insertions(+), 42 deletions(-)
diff --git a/arch/x86/kernel/cpu
Update these AMD bit field names to be consistent with naming
convention followed by the rest of the file.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/perf_event.h|4 ++--
arch/x86/kernel/cpu/perf_event_amd.c |8
2 files changed, 6 insertions(+), 6 deletions(-)
diff
On Tue, Nov 27, 2012 at 01:10:51PM +0100, Robert Richter wrote:
> One minor comment:
>
> On 26.11.12 16:48:30, Jacob Shin wrote:
> > __init int amd_pmu_init(void)
> > {
> > /* Performance-monitoring supported from K7 and later: */
> > @@ -666,6 +749,1
Robert,
On Fri, Nov 16, 2012 at 08:32:24PM +0100, Robert Richter wrote:
> On 16.11.12 13:00:30, Jacob Shin wrote:
> > On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
> > > On 15.11.12 15:31:53, Jacob Shin wrote:
> > > > @@ -323,6 +368,16 @@ __amd_g
Separate out Robert's patches, and add properly ordered certificate of
origins.
Jacob Shin (4):
perf, amd: Use proper naming scheme for AMD bit field definitions
perf, x86: Move MSR address offset calculation to architecture
specific files
perf, x86: Allow for architecture specific
Similar to config_base and event_base, allow architecture specific
RDPMC ECX values.
Signed-off-by: Jacob Shin
Acked-by: Stephane Eranian
---
arch/x86/kernel/cpu/perf_event.c |2 +-
arch/x86/kernel/cpu/perf_event.h |6 ++
arch/x86/kernel/cpu/perf_event_amd.c |6
performance counters starting at 0xc0010240.
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event.h | 21 -
arch/x86/kernel/cpu/perf_event_amd.c | 42 ++
2 files changed, 47 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel/cpu
From: Robert Richter
Generalize northbridge constraints code for family 10h so that later
we can reuse the same code path with other AMD processor families that
have the same northbridge event constraints.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu
counters, these MSRs are shared between multiple
cores (that share the same northbridge). We will reuse the same code
path as existing family 10h northbridge event constraints handler
logic to enforce this sharing.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/cpufeature.h |2 +
arch/x86
From: Robert Richter
Code simplification. No functional changes.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
Acked-by: Stephane Eranian
---
arch/x86/kernel/cpu/perf_event_amd.c | 68 +-
1 file changed, 26 insertions(+), 42 deletions(-)
diff
Update these AMD bit field names to be consistent with naming
convention followed by the rest of the file.
Signed-off-by: Jacob Shin
Acked-by: Stephane Eranian
---
arch/x86/include/asm/perf_event.h|4 ++--
arch/x86/kernel/cpu/perf_event_amd.c |8
2 files changed, 6
On Wed, Feb 06, 2013 at 11:26:23AM -0600, Jacob Shin wrote:
> The following patchset enables 4 additional performance counters in
> AMD family 15h processors that count northbridge events -- such as
> number of DRAM accesses.
>
Here is the libpfm4 counterpart,
Th
On Wed, Feb 06, 2013 at 11:26:29AM -0600, Jacob Shin wrote:
> On AMD family 15h processors, there are 4 new performance counters
> (in addition to 6 core performance counters) that can be used for
> counting northbridge events (i.e. DRAM accesses). Their bit fields are
> almost iden
On Fri, Feb 08, 2013 at 12:16:28PM +0100, Stephane Eranian wrote:
> On Wed, Feb 6, 2013 at 6:26 PM, Jacob Shin wrote:
> > On AMD family 15h processors, there are 4 new performance counters
> > (in addition to 6 core performance counters) that can be used for
> > counting no
On Tue, Apr 02, 2013 at 01:40:13PM +0200, Thomas Renninger wrote:
> On Thursday, March 28, 2013 01:24:17 PM Jacob Shin wrote:
> > Future AMD processors, starting with Family 16h, can provide software
> > with feedback on how the workload may respond to frequency change --
&
On Tue, Apr 02, 2013 at 02:43:32PM +0200, Borislav Petkov wrote:
> On Thu, Mar 28, 2013 at 01:24:16PM -0500, Jacob Shin wrote:
> > This allows for another [arch specific] driver to hook into existing
> > powersave bias function of the ondemand governor. i.e. This allows AMD
> &g
On Tue, Apr 02, 2013 at 03:42:55PM +0200, Borislav Petkov wrote:
> On Thu, Mar 28, 2013 at 01:24:17PM -0500, Jacob Shin wrote:
> > Future AMD processors, starting with Family 16h, can provide software
> > with feedback on how the workload may respond to frequency change --
&
On Wed, Mar 27, 2013 at 06:07:01PM -0500, Jacob Shin wrote:
> Upcoming AMD Family 16h Processors provide 4 new performance counters
> to count L2 related events. Similar to northbridge counters, these new
> counters are shared across multiple CPUs that share the same L2 cache.
> This p
r.
* Other small changes per feedback from:
https://lkml.org/lkml/2013/4/2/349
V2:
* Added proper include files to amd_freq_sensitivity.c
* Only register powersave_bias_target function pointer and not the entire
od_ops.
Jacob Shin (2):
cpufreq: ondemand: allow custom powersave_bias_target han
This allows for another [arch specific] driver to hook into existing
powersave bias function of the ondemand governor. i.e. This allows AMD
specific powersave bias function (in a separate AMD specific driver)
to aid ondemand governor's frequency transition deicisions.
Signed-off-by: Jacob
dback" to aid the ondemand governor to make better
frequency change decisions by hooking into the powersave bias.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/cpufeature.h |1 +
arch/x86/kernel/cpu/scattered.c|3 +-
drivers/cpufreq/Kconfig.x86| 17 +++
On Tue, Apr 02, 2013 at 09:23:52PM +0200, Borislav Petkov wrote:
> On Tue, Apr 02, 2013 at 01:11:44PM -0500, Jacob Shin wrote:
> > Future AMD processors, starting with Family 16h, can provide software
> > with feedback on how the workload may respond to frequency change --
&
On Tue, Apr 02, 2013 at 11:01:24PM +0200, Borislav Petkov wrote:
> On Tue, Apr 02, 2013 at 10:51:51PM +0200, Thomas Renninger wrote:
> > powersave_bias is undocumented in Documentation/cpu-freq/...
> > I guess its use-case is for people who want to get some percent more
> > power savings out of the
On Wed, Apr 03, 2013 at 07:04:56PM +0200, Borislav Petkov wrote:
> On Wed, Apr 03, 2013 at 11:53:24AM -0500, Jacob Shin wrote:
> > Then Thomas, Boris, would it be acceptable if enable the frequency
> > feedback feature by default with a sane powersave_bias tunable value?
> >
This allows for another [arch specific] driver to hook into existing
powersave bias function of the ondemand governor. i.e. This allows AMD
specific powersave bias function (in a separate AMD specific driver)
to aid ondemand governor's frequency transition decisions.
Signed-off-by: Jacob
dback" to aid the ondemand governor to make better
frequency change decisions by hooking into the powersave bias.
Signed-off-by: Jacob Shin
---
Documentation/cpu-freq/governors.txt | 21 +
arch/x86/include/asm/cpufeature.h |1 +
arch/x86/kernel/cpu/scattered.c|3 +
y.c
* Only register powersave_bias_target function pointer and not the entire
od_ops.
Jacob Shin (2):
cpufreq: ondemand: allow custom powersave_bias_target handler to be
registered
cpufreq: AMD "frequency sensitivity feedback" powersave bias for
ondemand governor
Do
On Thu, Apr 04, 2013 at 10:06:35PM +0530, Viresh Kumar wrote:
> On 4 April 2013 21:49, Jacob Shin wrote:
> > diff --git a/drivers/cpufreq/cpufreq_ondemand.c
> > b/drivers/cpufreq/cpufreq_ondemand.c
>
> > +static void od_set_powersave_bias(unsigned int powersave_bias)
>
On Thu, Apr 04, 2013 at 09:12:25PM +0200, Borislav Petkov wrote:
> On Thu, Apr 04, 2013 at 12:18:04PM -0500, Jacob Shin wrote:
> > @@ -574,6 +577,45 @@ static struct common_dbs_data od_dbs_cdata = {
> > .exit = od_exit,
> > };
> >
> > +static void o
On Thu, Apr 04, 2013 at 09:23:23PM +0200, Borislav Petkov wrote:
> On Thu, Apr 04, 2013 at 11:19:04AM -0500, Jacob Shin wrote:
> > Future AMD processors, starting with Family 16h, can provide software
> > with feedback on how the workload may respond to frequency change --
&
On Thu, Jan 24, 2013 at 02:31:59PM +0100, Stephane Eranian wrote:
> On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> > The following patchset enables 4 additional performance counters in
> > AMD family 15h processors that count northbridge events -- such as
> > nu
M range will be ignored.
>
> Signed-off-by: Yinghai Lu
> Cc: Jacob Shin
Acked-by: Jacob Shin
Thanks,
> ---
> arch/x86/kernel/setup.c | 36 ++--
> 1 file changed, 22 insertions(+), 14 deletions(-)
>
> diff --git a/arch/x86/kernel/se
.16.6?
> Are those NOT supported by your kernel patchset?
Oh, you are right, they are supported. I'm not sure why I overlooked
them. I will send out a V2 that includes all of those events as well.
Sorry about that.
-Jacob
>
>
> On Thu, Jan 24, 2013 at 11:06 PM, Jacob Shin wrote
On Fri, Jan 25, 2013 at 12:07:40PM +0100, Stephane Eranian wrote:
> On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> > From: Robert Richter
> >
> > Generalize northbridge constraints code for family 10h so that later
> > we can reuse the same code path with other
On Fri, Jan 25, 2013 at 12:15:37PM +0100, Stephane Eranian wrote:
> On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> > Move counter index to MSR address offset calculation to architecture
> > specific files. This prepares the way for perf_event_amd to enable
> > counter a
On Fri, Aug 24, 2012 at 09:54:04PM -0700, Yinghai Lu wrote:
> On Fri, Aug 24, 2012 at 9:24 PM, Jacob Shin wrote:
> > On Fri, Aug 24, 2012 at 06:07:01PM -0700, Yinghai Lu wrote:
> >> On Fri, Aug 24, 2012 at 4:55 PM, Jacob Shin wrote:
> >>
> >> looks like yo
From: Yinghai Lu
detect if need to use 1G or 2M and store them in page_size_mask.
Only probe them one time.
Suggested-by: Ingo Molnar
Signed-off-by: Yinghai Lu
---
arch/x86/include/asm/pgtable.h |1 +
arch/x86/kernel/setup.c|1 +
arch/x86/mm/init.c | 66
From: Yinghai Lu
from init_memory_mapping, so make init_memory_mapping readable.
Suggested-by: Ingo Molnar
Signed-off-by: Yinghai Lu
---
arch/x86/mm/init.c | 42 ++
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/arch/x86/mm/init.c b/a
:
https://lkml.org/lkml/2012/8/11/83
Signed-off-by: Jacob Shin
---
arch/x86/mm/init.c | 62 +---
1 file changed, 35 insertions(+), 27 deletions(-)
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 41e615b..916b15b 100644
--- a/arch/x86
Currently direct mappings are created for [ 0 to max_low_pfn<
---
arch/x86/include/asm/page_types.h |9
arch/x86/kernel/setup.c | 100 +++--
arch/x86/mm/init.c|2 +
arch/x86/mm/init_64.c |6 +--
4 files changed
Update code that previously assumed pfns [ 0 - max_low_pfn_mapped ) and
[ 4GB - max_pfn_mapped ) were always direct mapped, to now look up
pfn_mapped ranges instead.
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/amd.c |6 +-
arch/x86/platform/efi/efi.c |8
2 files
://lkml.org/lkml/2012/8/22/680
* https://lkml.org/lkml/2012/8/13/512
* https://lkml.org/lkml/2012/8/9/536
* https://lkml.org/lkml/2011/10/20/323
Jacob Shin (4):
x86/mm: find_early_table_space based on memory ranges that are being
mapped
x86: Only direct map addresses that are marked as
There could be cases where user supplied memmap=exactmap memory
mappings do not mark the region where the kernel .text .data and
.bss reside as E820_RAM, as reported here:
https://lkml.org/lkml/2012/8/14/86
Handle it by complaining, and adding the range back into the e820.
Signed-off-by: Jacob
On Wed, Aug 29, 2012 at 02:17:51PM -0700, Yinghai Lu wrote:
> On Wed, Aug 29, 2012 at 12:04 PM, Jacob Shin wrote:
> > Currently direct mappings are created for [ 0 to max_low_pfn< > and [ 4GB to max_pfn< > backed by actual DRAM. This is fine for holes under 4GB which are cov
On Thu, Aug 30, 2012 at 04:06:07PM -0700, Yinghai Lu wrote:
> Only create mapping for E820_820 and E820_RESERVED_KERN.
>
> Also seperate find_early_page_table out with init_memory_mapping.
>
> Jacob Shin (3):
> x86: if kernel .text .data .bss are not marked as E820_RAM, comp
On Wed, Sep 05, 2012 at 03:08:15PM -0500, Jacob Shin wrote:
> On Tue, Sep 04, 2012 at 10:46:17PM -0700, Yinghai Lu wrote:
> > Only create mapping for E820_820 and E820_RESERVED_KERN.
> >
> > Seperate calculate_table_space_size and find_early_page_table out with
&g
On Mon, Oct 01, 2012 at 12:00:26PM +0100, Stefano Stabellini wrote:
> On Sun, 30 Sep 2012, Yinghai Lu wrote:
> > After
> >
> > | commit 8548c84da2f47e71bbbe300f55edb768492575f7
> > | Author: Takashi Iwai
> > | Date: Sun Oct 23 23:19:12 2011 +0200
> > |
> > |x86: Fix S4 regression
> > |
> >
that's a given.
> >
> > We can trim those ranges, though. Who cares if we lose some RAM.
> >
>
> please check attached two patches that handle partial pages for 3.7.
>
> and you still need patch in
>https://lkml.org/lkml/2012/8/24/469
>
> to address
On Wed, Oct 24, 2012 at 11:53:16AM -0700, H. Peter Anvin wrote:
> On 10/24/2012 09:48 AM, Jacob Shin wrote:
> >
> > hpa, we need this patch: https://lkml.org/lkml/2012/8/24/469 and the above
> > 2 from Yinghai to handle corner case E820 layouts.
> >
>
> I can
d in 7b16bbf9
> >
> > Could you please send a delta patch against tip:x86/urgent?
>
> please check attached one.
Acked-by: Jacob Shin
Sorry about that, I just retrofitted the patch and didn't see those lines got
reverted out,
Thanks!
>
> Thanks
>
> Yinghai
if (ei->type == E820_RESERVED)
> > >> +continue;
> > >> +
> > >> +max_pfn_mapped = init_memory_mapping(
> > >> +ei->addr < 1UL << 32 ? 1UL &l
On Mon, Oct 29, 2012 at 09:58:23AM -0700, Greg Kroah-Hartman wrote:
> On Mon, Oct 29, 2012 at 09:47:22AM -0500, Jacob Shin wrote:
> > On Mon, Oct 29, 2012 at 02:40:58PM +, Ben Hutchings wrote:
> > > On Mon, 2012-10-29 at 10:22 -0400, Mark Lord wrote:
> > > > On 12
nit mapping
> only for E820 RAM and E820_RESERVED_KERN.
>
> Could be found at:
> git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linux-yinghai.git
> for-x86-mm
>
> Thanks
> Yinghai
>
>
> Jacob Shin (4):
> x86: if kernel .text .data .bss are n
On Thu, Sep 06, 2012 at 10:22:19AM +0300, Pekka Enberg wrote:
> On Wed, Sep 5, 2012 at 1:02 AM, Pekka Enberg wrote:
> > > How significant is the speed gain? The "isa_done" flag makes code flow
> > > more difficult to follow.
>
> On Wed, 5 Sep 2012, Yinghai Lu wrote:
> > Not really much.
> >
> >
hes.
V3:
Addressed the following feedback/comments from Robert's review
* https://lkml.org/lkml/2012/11/16/484
* https://lkml.org/lkml/2012/11/26/162
V2:
Separate out Robert's patches, and add properly ordered certificate of
origins.
Jacob Shin (4):
perf, amd: Use proper naming schem
From: Robert Richter
Generalize northbridge constraints code for family 10h so that later
we can reuse the same code path with other AMD processor families that
have the same northbridge event constraints.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu
From: Robert Richter
Code simplification. No functional changes.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event_amd.c | 68 +-
1 file changed, 26 insertions(+), 42 deletions(-)
diff --git a/arch/x86/kernel/cpu
performance counters starting at 0xc0010240.
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event.h | 21 -
arch/x86/kernel/cpu/perf_event_amd.c | 42 ++
2 files changed, 47 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel/cpu
Similar to config_base and event_base, allow architecture specific
RDPMC ECX values.
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event.c |2 +-
arch/x86/kernel/cpu/perf_event.h |6 ++
arch/x86/kernel/cpu/perf_event_amd.c |6 ++
3 files changed, 13
Update these AMD bit field names to be consistent with naming
convention followed by the rest of the file.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/perf_event.h|4 ++--
arch/x86/kernel/cpu/perf_event_amd.c |8
2 files changed, 6 insertions(+), 6 deletions(-)
diff
counters, these MSRs are shared between multiple
cores (that share the same northbridge). We will reuse the same code
path as existing family 10h northbridge event constraints handler
logic to enforce this sharing.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/cpufeature.h|2 +
arch/x86
On Thu, Oct 18, 2012 at 05:17:28PM +0100, Stefano Stabellini wrote:
> On Thu, 11 Oct 2012, Yinghai Lu wrote:
> > On Wed, Oct 10, 2012 at 9:40 AM, Stefano Stabellini
> > wrote:
> > >
> > > So you are missing the Xen patches entirely in this iteration of the
> > > series?
> >
> > please check updat
On Thu, Oct 18, 2012 at 01:40:21PM -0700, Yinghai Lu wrote:
> On Thu, Oct 18, 2012 at 9:26 AM, Jacob Shin wrote:
>
> i tested dom0 conf on 32 bit and 64 bit, they are all working.
>
> and just now I tried with mem=8944m, and they are still working.
>
> anyway, can you p
On Sat, Oct 20, 2012 at 09:01:43PM -0700, Yinghai Lu wrote:
> On Sat, Oct 20, 2012 at 5:17 PM, Tom Rini wrote:
> > On 10/20/12 17:11, Shin, Jacob wrote:
> >> Hi could you please attach the dmesg output? Before rc2 is fine as well.
> >> I would like to see the E820 table. Thank you,
> >
> > dmesg i
On Sun, Oct 21, 2012 at 10:51:35AM -0700, Tom Rini wrote:
> On 10/20/12 21:18, Jacob Shin wrote:
> > On Sat, Oct 20, 2012 at 09:01:43PM -0700, Yinghai Lu wrote:
> >> On Sat, Oct 20, 2012 at 5:17 PM, Tom Rini wrote:
> >>> On 10/20/12 17:11, Shin, Jacob wrote:
> &g
On Sun, Oct 21, 2012 at 02:23:58PM -0700, Tom Rini wrote:
> On 10/21/12 14:06, Jacob Shin wrote:
> > Ah, sorry, this one should apply on top of 3.7-rc2:
> >
> > https://lkml.org/lkml/2012/8/24/469
> >
> > Could you try that? Just that single patch, not the w
On Mon, Oct 22, 2012 at 11:05:29AM -0700, Yinghai Lu wrote:
> On Mon, Oct 22, 2012 at 7:40 AM, Jacob Shin wrote:
> > On Sun, Oct 21, 2012 at 02:23:58PM -0700, Tom Rini wrote:
> >> On 10/21/12 14:06, Jacob Shin wrote:
> >> > Ah, sorry, this one should apply on top o
On Wed, Dec 05, 2012 at 05:04:12PM -0600, Jacob Shin wrote:
> The following patchset enables 4 additional performance counters in
> AMD family 15h processors that count northbridge events -- such as
> number of DRAM accesses.
>
> This patchset is based on previous work done by
On Mon, Nov 12, 2012 at 03:22:33PM +0100, Robert Richter wrote:
> Stephane,
>
> On 12.11.12 13:24:38, Stephane Eranian wrote:
> > Anybody from AMD or formerly @ AMD care to submit a libpfm4 patch
> > to add the Fam15th NB events?
> >
> > I'd like to avoid having to type them in manually.
>
> Sur
On Wed, Nov 07, 2012 at 10:48:35AM +0100, H. Peter Anvin wrote:
> Too many of us at LCE right now...
Hi, ping'ing once again, could you take a look at the patchset when
you get the chance, and if no problems commit them into tip?
Thanks!
-Jacob
>
> Jacob Shin wrote:
>
t; Please apply.
Acked-by: Jacob Shin
Ping ?
Any feedback ? If not could we get it into tip ?
Thank you,
>
>
> Thanks,
>
> Andreas
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majord...@v
From: Robert Richter
Code simplification, there is no functional change.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event_amd.c | 68 +-
1 file changed, 26 insertions(+), 42 deletions(-)
diff --git a/arch/x86/kernel
northbridge counters are indexed contiguously right above the
core performance counters.
- MSR address offset calculations are moved to architecture specific
files.
- Interrups are set up to be delivered only to a single core.
Jacob Shin (3):
perf, amd: Refactor northbridge event constraints handler
performance counters starting at 0xc0010240.
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event.h | 21 +---
arch/x86/kernel/cpu/perf_event_amd.c | 36 ++
2 files changed, 41 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel
Breakout and generalize family 10h northbridge event contraints code
so that later we can reuse the same code path with other AMD processor
families that have the same northbridge event constraints.
Based on previous patch by Robert Richter
Signed-off-by: Jacob Shin
Signed-off-by: Robert
between multiple cores (that share the same
northbridge). We will reuse the same code path as existing family 10h
northbridge event constraints handler logic to enforce sharing.
Based on previous patch by Robert Richter
Signed-off-by: Jacob Shin
Signed-off-by: Robert Richter
---
arch/x86/include
On Sat, Nov 10, 2012 at 12:50:27PM +0100, Robert Richter wrote:
> On 09.11.12 19:01:34, Jacob Shin wrote:
> > The following patchset enables 4 additional performance counters in
> > AMD family 15h processors that counts northbridge events -- such as
> > DRAM accesses.
>
On Tue, Dec 18, 2012 at 06:19:15PM +0100, Borislav Petkov wrote:
> On Mon, Dec 17, 2012 at 01:39:48PM -0600, Jacob Shin wrote:
> > Add MCE decoding logic for AMD Family 16h processors.
> >
> > Signed-off-by: Jacob Shin
> > ---
> &g
On Tue, Dec 18, 2012 at 11:30:24AM -0600, Jacob Shin wrote:
> On Tue, Dec 18, 2012 at 06:19:15PM +0100, Borislav Petkov wrote:
> > On Mon, Dec 17, 2012 at 01:39:48PM -0600, Jacob Shin wrote:
> > > +/* internal error type */
> > > +const char * const uu_msgs[] = { &
Currently only AMD Family 15h processors have special handling for MC2
errors, since upcoming Family 16h will also need unique handling,
let's make MC2 handling part of amd_decoder_ops.
Signed-off-by: Jacob Shin
---
drivers/edac/mce_amd.c |
://lkml.org/lkml/2012/12/18/269
* Fixed typo in INT_ERROR decoding.
Jacob Shin (2):
MCE, AMD: Make MC2 decoding part of amd_decoder_ops as well
MCE, AMD: MCE decoding support for AMD Family 16h
drivers/edac/mce_amd.c | 139 +++-
drivers/edac/mce_amd.h
Add MCE decoding logic for AMD Family 16h processors.
Signed-off-by: Jacob Shin
---
drivers/edac/mce_amd.c | 83 +---
drivers/edac/mce_amd.h |3 ++
2 files changed, 75 insertions(+), 11 deletions(-)
diff --git a/drivers/edac/mce_amd.c b/drivers
On Wed, Dec 19, 2012 at 09:37:51PM +0100, Borislav Petkov wrote:
> On Sat, Dec 15, 2012 at 03:17:05PM -0800, H. Peter Anvin wrote:
> > On 12/15/2012 03:15 PM, Yinghai Lu wrote:
> > >>
> > >>That is for the kernel region itself (that code is actually unchanged from
> > >>the current code), and yes,
al RAM there.
-Jacob
>
> Jacob Shin wrote:
>
> >On Wed, Dec 19, 2012 at 09:37:51PM +0100, Borislav Petkov wrote:
> >> On Sat, Dec 15, 2012 at 03:17:05PM -0800, H. Peter Anvin wrote:
> >> > On 12/15/2012 03:15 PM, Yinghai Lu wrote:
> >> > &g
On Wed, Dec 19, 2012 at 02:25:44PM -0800, H. Peter Anvin wrote:
> On 12/19/2012 02:05 PM, Jacob Shin wrote:
> >On Wed, Dec 19, 2012 at 01:48:33PM -0800, H. Peter Anvin wrote:
> >>There are a few very serious problems we need to figure out related to
> >>generalizin
On Wed, Dec 19, 2012 at 11:51:55PM +0100, Borislav Petkov wrote:
> On Wed, Dec 19, 2012 at 02:25:44PM -0800, H. Peter Anvin wrote:
> > The real question is what we can do to mitigate the damage.
>
> Let's try the first thing that comes to mind: waste a variable MTRR on
> it:
>
> [0.00] MT
On Thu, Dec 20, 2012 at 12:03:29AM +0100, Borislav Petkov wrote:
> On Wed, Dec 19, 2012 at 04:59:41PM -0600, Jacob Shin wrote:
> > I can check but right, they might be used up. But even if we had slots
> > available, the memory range that needs to be covered is in large
> &g
On Wed, Dec 19, 2012 at 03:22:13PM -0800, H. Peter Anvin wrote:
> On 12/19/2012 03:03 PM, Borislav Petkov wrote:
> > On Wed, Dec 19, 2012 at 04:59:41PM -0600, Jacob Shin wrote:
> >> I can check but right, they might be used up. But even if we had slots
> >> available,
On Wed, Dec 19, 2012 at 03:50:14PM -0800, H. Peter Anvin wrote:
> On 12/19/2012 03:40 PM, Jacob Shin wrote:
> >>
> >>Just make the hole a bit bigger, so it starts at 0xfc, then you
> >>only need one MTRR. This is the correct BIOS-level fix, and it really
&g
On Wed, Dec 19, 2012 at 04:24:09PM -0800, H. Peter Anvin wrote:
> On 12/19/2012 04:07 PM, Jacob Shin wrote:
> >
> > From what I remember, accessing memory around the memory hole (not
> > just the HT hole, but e03800 ~ 100 on our mentioned system
> > ) gener
On Wed, Dec 19, 2012 at 06:37:45PM -0800, H. Peter Anvin wrote:
> On 12/19/2012 04:29 PM, Jacob Shin wrote:
> > On Wed, Dec 19, 2012 at 04:24:09PM -0800, H. Peter Anvin wrote:
> >> On 12/19/2012 04:07 PM, Jacob Shin wrote:
> >>>
> >>> From what I remembe
On Wed, Dec 19, 2012 at 11:11:09PM -0200, Henrique de Moraes Holschuh wrote:
> Jacob,
>
> Since you seem to be dealing with AMD microcode, do you know anything about
> the amd64.org demise? Where do we get the microcode update data, now?
Hi,
Yes, the server amd64.org was hosted on is down at th
performance counters starting at 0xc0010240.
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event.h | 21 +---
arch/x86/kernel/cpu/perf_event_amd.c | 35 ++
2 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel
From: Robert Richter
Code simplification. No functional changes.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu/perf_event_amd.c | 68 +-
1 file changed, 26 insertions(+), 42 deletions(-)
diff --git a/arch/x86/kernel/cpu
dered certificate of
origins.
Jacob Shin (2):
perf, x86: Move MSR address offset calculation to architecture
specific files
perf, amd: Enable northbridge performance counters on AMD family 15h
Robert Richter (2):
perf, amd: Rework northbridge event constraints handler
perf, amd: Gener
From: Robert Richter
Generalize northbridge constraints code for family 10h so that later
we can reuse the same code path with other AMD processor families that
have the same northbridge event constraints.
Signed-off-by: Robert Richter
Signed-off-by: Jacob Shin
---
arch/x86/kernel/cpu
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