On Fri, May 03, 2019 at 12:38:08PM +0900, Akinobu Mita wrote:
> 2019年5月2日(木) 22:03 Keith Busch :
> > On Thu, May 02, 2019 at 05:59:17PM +0900, Akinobu Mita wrote:
> > > This enables to capture snapshot of controller information via device
> > > coredump machanism, and
On Thu, May 02, 2019 at 08:59:39PM -0700, Frederick Lawler wrote:
> +#define dev_fmt(fmt) "DPC: " fmt
> +
> @@ -110,7 +111,7 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
> + pci_warn(pdev, "DPC root port still busy\n");
> @@ -229,18 +229,17 @@ static irqreturn_t
On Mon, Apr 29, 2019 at 10:59:26AM -0600, Alex Williamson wrote:
> On Mon, 29 Apr 2019 09:45:28 -0700
> Sinan Kaya wrote:
>
> > On 4/29/2019 10:51 AM, Alex Williamson wrote:
> > > So where do we go from here? I agree that dmesg is not necessarily a
> > > great choice for these sorts of events
On Tue, Apr 30, 2019 at 11:11:51AM -0500, Bjorn Helgaas wrote:
> > I'm not convinced a revert is the best call.
>
> I have very limited options at this stage of the release, but I'd be
> glad to hear suggestions. My concern is that if we release v5.1
> as-is, we'll spend a lot of energy on those
On Tue, Apr 30, 2019 at 12:05:09PM -0600, Keith Busch wrote:
> On Tue, Apr 30, 2019 at 11:11:51AM -0500, Bjorn Helgaas wrote:
> > > I'm not convinced a revert is the best call.
> >
> > I have very limited options at this stage of the release, but I'd be
> > glad to
a memory notifier callback and register the memory attributes
the first time its node is brought online if it wasn't registered.
Signed-off-by: Keith Busch
---
v1 -> v2:
Fixed an unintended __init attribute that generated compiler warnings
(Brice).
drivers/acpi/hmat/hmat.c |
Instead of registering the hmat cache attributes in line with parsing
the table, save the attributes in the memory target and register them
after parsing completes. This will make it easier to register the
attributes later when hot add is supported.
Signed-off-by: Keith Busch
---
v1 ->
that it always restores the
> device state from the originally saved data, and avoid calling
> pci_prepare_to_sleep() for the device.
>
> Fixes: 33e4f80ee69b ("ACPI / PM: Ignore spurious SCI wakeups from
> suspend-to-idle")
> Signed-off-by: Rafael J. Wysocki
LGTM
Reviewed-by: Keith Busch
Hi Greg,
Just wanted to check with you on how we may proceed with this series.
The main feature is exporting new sysfs attributes through driver core,
so I think it makes most sense to go through you unless you'd prefer
this go through a different route.
The proposed interface has been pretty
On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
> -> Share the NVMe device between host and guest.
> Even in fully virtualized configurations,
> some partitions of nvme device could be used by guests as block devices
> while others passed through with nvme-mdev
On Mon, Mar 18, 2019 at 08:12:04PM -0500, Alexandru Gagniuc wrote:
> I was able to test this on edge-triggered interrupts. None of my
> machines have PCIe ports that use level-triggered interrupts. This
> might not be too straightforward to test without a hardware yanker,
> but if there's a way to
On Mon, Mar 25, 2019 at 12:49:21PM -0700, Yang Shi wrote:
> On 3/24/19 3:20 PM, Keith Busch wrote:
> > How do these pages eventually get to swap when migration fails? Looks
> > like that's skipped.
>
> Yes, they will be just put back to LRU. Actually, I don't expect it
On Tue, Mar 26, 2019 at 08:41:15PM -0700, Yang Shi wrote:
> On 3/26/19 5:35 PM, Keith Busch wrote:
> > migration nodes have higher free capacity than source nodes. And since
> > your attempting THP's without ever splitting them, that also requires
> > lower fragmentation for a
On Wed, Feb 27, 2019 at 04:42:05PM +, alex_gagn...@dellteam.com wrote:
> On 2/26/19 7:02 PM, Linus Torvalds wrote:
> > On Tue, Feb 26, 2019 at 2:37 PM wrote:
> >>
> >> Then nobody gets the (error) message. You can go a bit further and try
> >> 'pcie_ports=native". Again, nobody gets the memo.
deY/access0/initiators/nodeX ->
../../nodeX
The new attributes are added to the sysfs stable documentation.
Signed-off-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 25 -
drivers/base/node.c | 142 +++-
include/linux/
rticular CPU they're running on in order to
make more informed choices for where they want to allocate hot and cold
data. This works with mbind() or the numactl library.
Keith Busch (10):
acpi: Create subtable parsing infrastructure
acpi: Add HMAT to generic parsing tables
acpi/hm
parsing
the entries array may be more reused for all ACPI system tables and
the common code doesn't need to be duplicated.
Reviewed-by: Rafael J. Wysocki
Cc: Dan Williams
Signed-off-by: Keith Busch
---
arch/arm64/kernel/acpi_numa.c | 2 +-
arch/arm64/kernel/smp.c
-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 34 +++
drivers/base/node.c | 151
include/linux/node.h| 39 +++
3 files changed, 224 insertions(+)
diff --git a/Documentation/ABI/stable/sysfs
Register memory side cache attributes with the memory's node if HMAT
provides the side cache iniformation table.
Acked-by: Rafael J. Wysocki
Signed-off-by: Keith Busch
---
drivers/acpi/hmat/hmat.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers
Signed-off-by: Keith Busch
---
drivers/acpi/hmat/Kconfig | 5 -
drivers/acpi/hmat/hmat.c | 10 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/acpi/hmat/Kconfig b/drivers/acpi/hmat/Kconfig
index 13cddd612a52..95a29964dbea 100644
--- a/drivers/acpi/hmat
The Heterogeneous Memory Attribute Table (HMAT) header has different
field lengths than the existing parsing uses. Add the HMAT type to the
parsing rules so it may be generically parsed.
Cc: Dan Williams
Reviewed-by: Rafael J. Wysocki
Signed-off-by: Keith Busch
---
drivers/acpi/tables.c | 9
to query this information.
Reviewed-by: Mike Rapoport
Signed-off-by: Keith Busch
---
Documentation/admin-guide/mm/numaperf.rst | 164 ++
1 file changed, 164 insertions(+)
create mode 100644 Documentation/admin-guide/mm/numaperf.rst
diff --git a/Documentation/admin-guide
sysfs directory.
Since HMAT requires valid address ranges have an equivalent SRAT entry,
verify each memory target satisfies this requirement.
Signed-off-by: Keith Busch
---
drivers/acpi/hmat/Kconfig | 3 +-
drivers/acpi/hmat/hmat.c | 395 +-
2 files
omitted from the any access class' initiators.
Descriptions for memory access initiator performance access attributes
are added to sysfs stable documentation.
Signed-off-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 28 ++
drivers/base/Kconfig
-by: Keith Busch
---
drivers/acpi/Kconfig | 1 +
drivers/acpi/Makefile | 1 +
drivers/acpi/hmat/Kconfig | 7 ++
drivers/acpi/hmat/Makefile | 1 +
drivers/acpi/hmat/hmat.c | 237 +
5 files changed, 247 insertions(+)
create mode 100644
On Thu, Feb 28, 2019 at 10:11:00AM -0500, Sasha Levin wrote:
> From: Keith Busch
>
> [ Upstream commit 5c959d73dba6495ec01d04c206ee679d61ccb2b0 ]
This patch was broken, so please make sure to include the one that
fixes this:
Upstream commit 4726bcf30fad37cc555cd9dcd6c73f2b2668c879
On Thu, Feb 28, 2019 at 11:10:11PM +, austin.bo...@dell.com wrote:
> I'd also note that in PCIe, things that intentionally take the link down
> like SBR or Link Disable suppress surprise down error reporting. But
> NSSR doesn't have this requirement to suppress surprise down reporting.
> I
On Thu, Feb 28, 2019 at 11:43:46PM +, austin.bo...@dell.com wrote:
> On 2/28/2019 5:20 PM, Keith Busch wrote:
> > SBR and Link Disable are done from the down stream port, though, so the
> > host can still communicate with the function that took the link down.
> > That's en
On Sat, Apr 06, 2019 at 09:12:22PM -0400, Qian Cai wrote:
> The commit 665ac7e92757 ("acpi/hmat: Register processor domain to its
> memory") introduced an uninitialized "struct memory_target" that could
> cause an incorrect branching.
Thanks for the catch. We do have another patch submitted a few
a memory notifier callback and set the memory attributes when
a node is initially brought online with hot added memory, and don't try
to register node attributes if the node is not online during initial
scanning.
Signed-off-by: Keith Busch
---
drivers/acpi/hmat/hmat.c | 63
On Thu, Apr 11, 2019 at 04:42:45PM +0200, Rafael J. Wysocki wrote:
> On Tue, Apr 9, 2019 at 11:42 PM Keith Busch wrote:
> > -static __init void hmat_register_targets(void)
> > +static void hmat_register_targets(void)
> > {
> > s
Uninitialized pointer read")
> Signed-off-by: Colin Ian King
I would have sworn this was fixed as it's in my tree already, but the
submitted patch sure enough doesn't have it.
I've double checked to see if there are any other discrepencies, and
there are no other differences
On Wed, Mar 20, 2019 at 06:30:29PM +0200, Maxim Levitsky wrote:
> Or instead I can use the block backend,
> (but note that currently the block back-end doesn't support polling which is
> critical for the performance).
Oh, I think you can do polling through there. For reference, fs/io_uring.c
has
On Thu, Mar 21, 2019 at 04:12:39PM +, Stefan Hajnoczi wrote:
> mdev-nvme seems like a duplication of SPDK. The performance is not
> better and the features are more limited, so why focus on this approach?
>
> One argument might be that the kernel NVMe subsystem wants to offer this
>
Refactor unmap_and_move() handling for the new page into a separate
function from locking and preparing the old page.
No functional change here: this is just making it easier to reuse this
part of the page migration from contexts that already locked the old page.
Signed-off-by: Keith Busch
Trace the source and destination node of a page migration to help debug
memory usage.
Signed-off-by: Keith Busch
---
include/trace/events/migrate.h | 26 ++
mm/migrate.c | 1 +
2 files changed, 27 insertions(+)
diff --git a/include/trace/events
On Thu, Mar 28, 2019 at 02:59:30PM -0700, Yang Shi wrote:
> Yes, it still could fail. I can't tell which way is better for now. I
> just thought scanning another round then migrating should be still
> faster than swapping off the top of my head.
I think it depends on the relative capacities
On Fri, Mar 29, 2019 at 02:15:03PM -0700, Dan Williams wrote:
> On Mon, Mar 11, 2019 at 1:55 PM Keith Busch wrote:
> > +static __init struct memory_target *find_mem_target(unsigned int mem_pxm)
> > +{
> > + struct memory_target *target;
> > +
> > + l
lock, ensuring onlining multiple regions
is single threaded to prevent duplicate hmat registration races.
Keith Busch (2):
hmat: Register memory-side cache after parsing
hmat: Register attributes for memory hot add
drivers/acpi/hmat/hmat.c | 108
Instead of registering the hmat cache attributes in line with parsing
the table, save the attributes in the memory target and register them
after parsing completes. This will make it easier to register the
attributes later when hot add is supported.
Signed-off-by: Keith Busch
---
drivers/acpi
and register the memory attributes
the first time its node is brought online if it wasn't registered,
ensuring a node's attributes may be registered only once.
Reported-by: Brice Goglin
Signed-off-by: Keith Busch
---
drivers/acpi/hmat/hmat.c | 72
1
On Fri, Mar 22, 2019 at 07:54:50AM +, Felipe Franciosi wrote:
> >
> > Note though that SPDK doesn't support sharing the device between host and
> > the
> > guests, it takes over the nvme device, thus it makes the kernel nvme driver
> > unbind from it.
>
> That is absolutely true. However, I
On Sat, Mar 23, 2019 at 12:44:31PM +0800, Yang Shi wrote:
> /*
> + * Demote DRAM pages regardless the mempolicy.
> + * Demot anonymous pages only for now and skip MADV_FREE
> + * pages.
> + */
> + if (PageAnon(page) &&
On Mon, Feb 18, 2019 at 04:42:27PM -0800, 陈华才 wrote:
> I've tested, this patch can fix the nvme problem, but it can't be applied
> to 4.19 because of different context. And, I still think my original solution
> (genirq/affinity: Assign default affinity to pre/post vectors) is correct.
> There may
On Mon, Feb 18, 2019 at 03:25:31PM +0100, Brice Goglin wrote:
> Le 14/02/2019 à 18:10, Keith Busch a écrit :
> > Determining the cpu and memory node local relationships is quite
> > different this time (PATCH 7/10). The local relationship to a memory
> > target will be e
On Mon, Mar 11, 2019 at 04:38:43AM -0700, Jonathan Cameron wrote:
> On Wed, 27 Feb 2019 15:50:38 -0700
> Keith Busch wrote:
>
> > Platforms may provide system memory where some physical address ranges
> > perform differently than others, or is side cached by the system.
>
parsing
the entries array may be more reused for all ACPI system tables and
the common code doesn't need to be duplicated.
Reviewed-by: Rafael J. Wysocki
Acked-by: Jonathan Cameron
Tested-by: Jonathan Cameron
Signed-off-by: Keith Busch
---
arch/arm64/kernel/acpi_numa.c | 2 +-
arch
wishing to query this information.
Reviewed-by: Mike Rapoport
Reviewed-by: Jonathan Cameron
Signed-off-by: Keith Busch
---
Documentation/admin-guide/mm/numaperf.rst | 169 ++
1 file changed, 169 insertions(+)
create mode 100644 Documentation/admin-guide/mm
deY/access0/initiators/nodeX ->
../../nodeX
The new attributes are added to the sysfs stable documentation.
Reviewed-by: Jonathan Cameron
Signed-off-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 25 -
drivers/base/node.c
sysfs directory.
Since HMAT requires valid address ranges have an equivalent SRAT entry,
verify each memory target satisfies this requirement.
Reviewed-by: Jonathan Cameron
Signed-off-by: Keith Busch
---
drivers/acpi/hmat/Kconfig | 3 +-
drivers/acpi/hmat/hmat.c | 392
Register memory side cache attributes with the memory's node if HMAT
provides the side cache iniformation table.
Acked-by: Rafael J. Wysocki
Signed-off-by: Keith Busch
---
drivers/acpi/hmat/hmat.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers
. Those applications may query performance
attributes relative to a particular CPU they're running on in order to
make more informed choices for where they want to allocate hot and cold
data. This works with mbind() or the numactl library.
Keith Busch (10):
acpi: Create subtable parsing infrastructure
The Heterogeneous Memory Attribute Table (HMAT) header has different
field lengths than the existing parsing uses. Add the HMAT type to the
parsing rules so it may be generically parsed.
Reviewed-by: Rafael J. Wysocki
Acked-by: Jonathan Cameron
Tested-by: Jonathan Cameron
Signed-off-by: Keith
Signed-off-by: Keith Busch
---
drivers/acpi/hmat/Kconfig | 5 -
drivers/acpi/hmat/hmat.c | 10 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/acpi/hmat/Kconfig b/drivers/acpi/hmat/Kconfig
index 13cddd612a52..95a29964dbea 100644
--- a/drivers/acpi/hmat
-by: Jonathan Cameron
Tested-by: Jonathan Cameron
Signed-off-by: Keith Busch
---
drivers/acpi/Kconfig | 1 +
drivers/acpi/Makefile | 1 +
drivers/acpi/hmat/Kconfig | 7 ++
drivers/acpi/hmat/Makefile | 1 +
drivers/acpi/hmat/hmat.c | 236 +
5
omitted from the any access class' initiators.
Descriptions for memory access initiator performance access attributes
are added to sysfs stable documentation.
Acked-by: Jonathan Cameron
Tested-by: Jonathan Cameron
Signed-off-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 28 +++
-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 34 +++
drivers/base/node.c | 151
include/linux/node.h| 39 +++
3 files changed, 224 insertions(+)
diff --git a/Documentation/ABI/stable/sysfs
On Thu, Feb 14, 2019 at 10:10:07AM -0700, Keith Busch wrote:
> Platforms may provide multiple types of cpu attached system memory. The
> memory ranges for each type may have different characteristics that
> applications may wish to know about when considering what node they want
>
On Wed, Feb 20, 2019 at 11:21:45PM +0100, Rafael J. Wysocki wrote:
> On Wed, Feb 20, 2019 at 11:11 PM Dave Hansen wrote:
> > On 2/20/19 2:02 PM, Rafael J. Wysocki wrote:
> > >> diff --git a/drivers/acpi/hmat/Kconfig b/drivers/acpi/hmat/Kconfig
> > >> index c9637e2e7514..08e972ead159 100644
> > >>
On Wed, Feb 20, 2019 at 06:46:11PM +0900, Takao Indoh wrote:
> On Thu, Feb 14, 2019 at 08:44:48PM +, Elliott, Robert (Persistent Memory)
> wrote:
> > * how does this interact with an iommu, if there is one? Must the
> > address with bit 56 also be granted permission, or is that
> > stripped
On Fri, Feb 22, 2019 at 11:12:38AM +0100, Brice Goglin wrote:
> Le 14/02/2019 à 18:10, Keith Busch a écrit :
> > +What:
> > /sys/devices/system/node/nodeX/memory_side_cache/indexY/size
> > +Date: December 2018
> > +Contact: Ke
On Fri, Feb 22, 2019 at 11:22:12AM +0100, Brice Goglin wrote:
> Le 14/02/2019 à 18:10, Keith Busch a écrit :
> > +What:
> > /sys/devices/system/node/nodeX/memory_side_cache/indexY/associativity
> > +Date: December 2018
> > +Contact: Ke
On Wed, Feb 20, 2019 at 11:02:01PM +0100, Rafael J. Wysocki wrote:
> On Thu, Feb 14, 2019 at 6:10 PM Keith Busch wrote:
> > config ACPI_HMAT
> > bool "ACPI Heterogeneous Memory Attribute Table Support"
> > depends on ACPI_NUMA
> > + s
On Fri, Feb 22, 2019 at 01:28:42PM -0800, Linus Torvalds wrote:
> On Thu, Feb 21, 2019 at 5:07 PM Jon Derrick
> wrote:
> >
> > Some platforms don't seem to easily tolerate non-posted mmio reads on
> > lost (hot removed) devices. This has been noted in previous
> > modifications to other layers
v3 for the other minor comments.
Reviewed-by: Keith Busch
> +static void nvme_calc_irq_sets(struct irq_affinity *affd, int nvecs)
> +{
> + struct nvme_dev *dev = affd->priv;
> +
> + nvme_calc_io_queues(dev, nvecs);
> +
> + affd->set_vectors[HCTX_TYPE_DEFA
On Tue, Feb 12, 2019 at 08:49:03AM +, Jonathan Cameron wrote:
> On Mon, 11 Feb 2019 08:23:04 -0700
> Keith Busch wrote:
>
> > On Sun, Feb 10, 2019 at 09:19:58AM -0800, Jonathan Cameron wrote:
> > > On Sat, 9 Feb 2019 09:20:53 +0100
> > > Brice Goglin wr
On Tue, Feb 12, 2019 at 04:49:24PM +, Jonathan Cameron wrote:
> + case ACPI_SRAT_TYPE_GENERIC_INITIATOR_AFFINITY:
> + {
> + struct acpi_srat_gi_affinity *p =
> + (struct acpi_srat_gi_affinity *)header;
> + char name[9] = {};
> +
> +
t #36 AttnBtn- PwrCtrl- MRL- AttnInd+
> PwrInd+ HotPlug+ Surprise+ Interlock- NoCompl- LLActRep+
Acked-by: Keith Busch
> diff --git a/drivers/pci/hotplug/pciehp_hpc.c
> b/drivers/pci/hotplug/pciehp_hpc.c
> index 7dd443aea5a5..2761778f2ecc 100644
> --- a/drivers/pci/hotplu
On Mon, Mar 11, 2019 at 11:20:41AM +, Jonathan Cameron wrote:
> On Wed, 27 Feb 2019 15:50:35 -0700
> Keith Busch wrote:
> > +static __init void hmat_register_target_initiators(struct memory_target
> > *target)
> > +{
> > + static DECLARE_BITMAP(p_nodes,
Hi Brice,
Please see v7 of this series from last week instead for reviews:
https://patchwork.kernel.org/cover/10832365/
On Sun, Feb 24, 2019 at 03:27:09PM -0800, alex_gagn...@dellteam.com wrote:
>
> More like "fatal error, just panic". It looks like this (from a serial
> console):
>
> [ 57.680494] {1}[Hardware Error]: Hardware error from APEI Generic
> Hardware Error Source: 1
> [ 57.680495] {1}[Hardware
On Sun, Feb 24, 2019 at 08:59:45PM +0100, Rafael J. Wysocki wrote:
> On Fri, Feb 22, 2019 at 7:48 PM Keith Busch wrote:
> > If I do it the other way around, that's going to make HMEM_REPORTING
> > complicated if a non-ACPI implementation wants to report HMEM
On Fri, Feb 01, 2019 at 09:46:15PM +0900, Takao Indoh wrote:
> From: Takao Indoh
>
> Fujitsu A64FX processor has a feature to accelerate data transfer of
> internal bus by relaxed ordering. It is enabled when the bit 56 of dma
> address is set to 1.
Wait, what? RO is a standard PCIe TLP
On Sun, Jan 20, 2019 at 05:16:05PM +0100, Rafael J. Wysocki wrote:
> On Sat, Jan 19, 2019 at 10:01 AM Greg Kroah-Hartman
> wrote:
> >
> > If you do a subdirectory "correctly" (i.e. a name for an attribute
> > group), that's fine.
>
> Yes, that's what I was thinking about: along the lines of the
gt;
> if (ctrl->cntlid != le16_to_cpu(id->cntlid))
>
> below will always be a no-op.
Yeah, this bug defeats the fabrics sanity check. Good catch.
Reviewed-by: Keith Busch
> diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
> index 2e65be8b1387..1ec87b30fa
to query this information.
Signed-off-by: Keith Busch
---
Documentation/admin-guide/mm/numaperf.rst | 184 ++
1 file changed, 184 insertions(+)
create mode 100644 Documentation/admin-guide/mm/numaperf.rst
diff --git a/Documentation/admin-guide/mm/numaperf.rst
b
Systems may provide different memory types and export this information
in the ACPI Heterogeneous Memory Attribute Table (HMAT). Parse these
tables provided by the platform and report the memory access and caching
attributes.
Signed-off-by: Keith Busch
---
drivers/acpi/Kconfig | 8
The Heterogeneous Memory Attribute Table (HMAT) header has different
field lengths than the existing parsing uses. Add the HMAT type to the
parsing rules so it may be generically parsed.
Cc: Dan Williams
Signed-off-by: Keith Busch
---
drivers/acpi/tables.c | 9 +
include/linux/acpi.h
Add descriptions for memory class initiator performance access attributes.
Signed-off-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 28
1 file changed, 28 insertions(+)
diff --git a/Documentation/ABI/stable/sysfs-devices-node
b/Documentation
est performing class, "class0".
Various changelog and documentation updates and clarifications.
Keith Busch (13):
acpi: Create subtable parsing infrastructure
acpi: Add HMAT to generic parsing tables
acpi/hmat: Parse and report heterogeneous memory
node: Link memory nodes to their com
requires valid address ranges have an equivalent SRAT entry,
verify each memory target satisfies this requirement.
Signed-off-by: Keith Busch
---
drivers/acpi/hmat.c | 143 +---
1 file changed, 136 insertions(+), 7 deletions(-)
diff --git a/drivers
Add the attributes for the system memory side caches.
Signed-off-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 34 +
1 file changed, 34 insertions(+)
diff --git a/Documentation/ABI/stable/sysfs-devices-node
b/Documentation/ABI/stable/sysfs
parsing
the entries array may be more reused for all ACPI system tables and
the common code doesn't need to be duplicated.
Reviewed-by: Rafael J. Wysocki
Cc: Dan Williams
Signed-off-by: Keith Busch
---
arch/arm64/kernel/acpi_numa.c | 2 +-
arch/arm64/kernel/smp.c
Register memory side cache attributes with the memory's node if HMAT
provides the side cache iniformation table.
Signed-off-by: Keith Busch
---
drivers/acpi/hmat.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/acpi/hmat.c b/drivers/acpi/hmat.c
system/node/nodeX/class0/target_nodelist
Y
# cat /sys/devices/system/node/nodeY/class0/initiator_nodelist
X
Signed-off-by: Keith Busch
---
drivers/base/node.c | 127 ++-
include/linux/node.h | 6 ++-
2 files changed, 131 insertions(+), 2 del
re. When a subsystem makes use of this interface, initiators
of a lower class number, "Z", have better performance relative to higher
class numbers. When provided, class 0 is the highest performing access
class.
Signed-off-by: Keith Busch
---
drivers/base/Kconfig | 8 +
Add entries for memory initiator and target node class attributes.
Signed-off-by: Keith Busch
---
Documentation/ABI/stable/sysfs-devices-node | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/stable/sysfs-devices-node
b
Save the best performace access attributes and register these with the
memory's node if HMAT provides the locality table. While HMAT does make
it possible to know performance for all possible initiator-target
pairings, we export only the best pairings at this time.
Signed-off-by: Keith Busch
are the cache size, the line size, associativity,
and write back policy.
Signed-off-by: Keith Busch
---
drivers/base/node.c | 142 +++
include/linux/node.h | 39 ++
2 files changed, 181 insertions(+)
diff --git a/drivers/base/node.c b
On Wed, Jan 09, 2019 at 05:54:59PM -0800, Yao HongBo wrote:
> On 1/10/2019 2:39 AM, Christoph Hellwig wrote:
> > On Mon, Jan 07, 2019 at 10:22:07AM +0800, Hongbo Yao wrote:
> >> There is an out of bounds array access in nvme_cqe_peding().
> >>
> >> When enable irq_thread for nvme interrupt, there
On Thu, Jan 10, 2019 at 06:07:02PM +0530, Aneesh Kumar K.V wrote:
> Keith Busch writes:
>
> > Heterogeneous memory systems provide memory nodes with different latency
> > and bandwidth performance attributes. Provide a new kernel interface for
> > subsystems to regis
On Fri, Jan 11, 2019 at 11:32:38AM +, Jonathan Cameron wrote:
> On Thu, 10 Jan 2019 10:30:17 -0700
> Keith Busch wrote:
> > I am not aware of a real platform that has an initiator-target pair with
> > better latency but worse bandwidth than any different initiator pair
On Fri, Dec 07, 2018 at 12:05:37PM -0800, Sagi Grimberg wrote:
>
> > Could you please take a look at this bug and code review?
> >
> > We are seeing more instances of this bug and found that reconnect_work
> > could hang as well, as can be seen from below stacktrace.
> >
> > Workqueue:
On Mon, Jul 23, 2018 at 04:24:31PM -0600, Alex Williamson wrote:
> Take advantage of NVMe devices using a standard interface to quiesce
> the controller prior to reset, including device specific delays before
> and after that reset. This resolves several NVMe device assignment
> scenarios with
On Wed, Jun 13, 2018 at 05:14:34PM +0100, Ben Hutchings wrote:
> On Mon, 2018-05-28 at 12:01 +0200, Greg Kroah-Hartman wrote:
> > result = adapter_alloc_sq(dev, qid, nvmeq);
> > if (result < 0)
> > @@ -1597,9 +1597,12 @@ static int nvme_create_queue(struct nvme
> > return result;
> >
On Wed, Jun 13, 2018 at 05:37:35PM +0100, Ben Hutchings wrote:
> On Wed, 2018-06-13 at 10:30 -0600, Keith Busch wrote:
> > Thank you very much the catching that. This particular patch is indeed
> > not correct without the following:
> >
> > 161b8be2bd6ab ("n
On Thu, Jun 14, 2018 at 04:18:15PM +0530, Srinath Mannam wrote:
> The issue is, For CMB cards SQs are allocated inside device BAR memory
> which is different from normal cards.
> In Normal cards SQ memory allocated at host side.
> In both the cases physical address of CQ memory is programmed in
On Fri, Jun 08, 2018 at 03:05:41PM -0500, Bjorn Helgaas wrote:
> The aer_irq() declaration is the only thing needed by aer_inject.c. Move
> it to portdrv.h so we eventually get rid of aerdrv.h completely. No
> functional change intended.
Nothing against what you're doing here, but it does seem
e it
> up one level to drivers/pci/pcie/aer.c.
>
> This is all pure code moves; no functional changes intended.
Thanks for doing this. I got a head start on reviewing when I saw this
merged to your tree earlier today, and the driver is much more pleasant
to read than before!
Reviewed-by: Keith Busch
On Thu, Jun 07, 2018 at 09:47:42PM -0700, p...@codeaurora.org wrote:
> Keith,
>
> do you know why in ERR_FATAL case following was done ?
> have a look at pcie_portdrv_slot_reset() handling (for bridges, switches
> etc..)
Not sure, but I was looking into some issues in this area anyway.
I'm
1101 - 1200 of 1501 matches
Mail list logo
