From: huang lin h...@rock-chips.com
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
---
Changes in v2:
Advices by Douglas Anderson
-use
From: huang lin h...@rock-chips.com
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
---
Changes in v3:
-match the author
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
---
Changes in v3:
-match author and Signed-off-by name
drivers/pinctrl/pinctrl-rockchip.c
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Lin Huang h...@rock-chips.com
Reviewed-by: Heiko Stuebner he...@sntech.de
---
Changes in v5:
-rebase patch
drivers/pinctrl/pinctrl-rockchip.c | 55
From: Heiko Stuebner he...@sntech.de
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Lin Huang h...@rock-chips.com
Reviewed-by: Heiko Stuebner he...@sntech.de
---
Changes in v4:
-delete some unrelated new blank line
drivers/pinctrl/pinctrl-rockchip.c
pclk_pd_pmu needs to keep running and with the upcoming gpio clock
handling this is not always the case anymore. So add it to the list
of critical clocks for now.
From: Heiko Stuebner he...@sntech.de
Signed-off-by: Lin Huang h...@rock-chips.com
---
Changes in v4:
- Add From: Heiko Stuebner he
rk3399 do ddr frequency scaling use devfreq framework,
use simple_ondemand policy, and use rk3399 dfi controller
to get ddr busy time.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/devfreq/Kconfig | 1 +
drivers/devfreq/Makefile | 1 +
drivers/d
support rk3399 dmc clock driver. Note, ddr set rate function will
use dcf controller which run in ATF, it need to fishish it when rk3399
arm trust firmware ready.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-
these patchset bring up rk3399 ddr frequency scaling flow,
use devfreq framework and simple_ondemand policy. Ddr set
rate function will implement in dcf controller which run in
the ATF, and rk3399 ATF not ready now, so we need finish it
when rk3399 ATF ready.
Lin Huang (2):
clk: rockchip: dmc
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag
- move cl
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- use GENMASK instead va
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v2:
- use clk_disable_unprepare and clk_enable_prep
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..8a
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang <h...@r
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- None
Changes in v1:
- move dfi controller to event
- fix set voltage sequence when set rat
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..8a0f0442 100644
--- a/incl
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang <h...@r
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- move dfi controller to event, Suggestion by Chanwoo Choi
- fix set voltage sequence when set rat
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- None
drivers/clk/ro
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
rockchip: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- NOne
drivers/devfreq/event/Kconfig| 7 +
drivers/devfreq/event/Makefile | 1 +
d
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag, Suggestion by Doug
- move clk_ddrc and clk_ddrc_dpll_src to critical, Suggestion b
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/clk/rockchip/Makefile | 1 +
d
there is dfi controller on rk3399 platform, it can monitor
ddr load, register this controller to devfreq framework, and
default to use simple_ondeamnd policy, and do ddr frequency
scaling base on this result.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/devfreq/K
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang <h...@r
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (4):
rockchip: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add ddrc clock support
PM / d
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3399.c | 16
include/dt-bindings/clock/rk3399-cru.h | 1 +
2 files changed, 17 insertions(+)
diff
From: Heiko St??bner <he...@sntech.de>
add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.
Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4
Signed-off-by: Heiko St??bner <he...@sntech.de>
Signed-off-by: Lin Huang <h...
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bi
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc
enabled, we need
to disable dmc, since dcf only base on one vop vblank time, so the
other panel will flicker when do ddr frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- register notifier to devfreq_register_notifier
- use DEVFREQ_PRECHANGE and DEVFREQ_POST
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- use arm_smccc_smc() function talk to bl31
- delete rockchip_dmc.c file and config
- delete dmc_
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v4:
- None
Changes in v3:
- None
Changes
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- use arm_smccc_smc() to se
From: Heiko Stübner <he...@sntech.de>
add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.
Signed-off-by: Heiko Stübner <he...@sntech.de>
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v4:
- None
Cha
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
- improve dmc driver suggest by Chanwoo Choi
Changes in v4:
- use arm_smccc_smc() function talk t
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
- fit for the ddr type
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical cloc
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
C
enabled, we need
to disable dmc, since dcf only base on one vop vblank time, so the
other panel will flicker when do ddr frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
- improve some nits
Changes in v4:
- register notifier to devfreq_register_notifier
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (8):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
- delete unuse mux_flag
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../devicetree/bindings/devfreq/rk3399_dmc.txt
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cr
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../bindings/devfreq/event/rockchip-dfi.txt
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang <h...@r
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v3:
- use sip call to set/read dd
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v3:
- None
Changes in v2:
- use clk_disab
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v3:
- operate dram setting through sip call
- imporve set rate flow
Changes in v2:
- None
Changes
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v3:
-None
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
From: Shengfei xu <x...@rock-chips.com>
This patch adds support for the SiP interface, we can pass dram
paramtert to bl31, and control ddr frequency scaling in bl31.
Signed-off-by: Shengfei xu <x...@rock-chips.com>
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v6:
-Add more detail in Documentation
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../devi
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
C
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v6:
- fix some nit suggest by Chanwoo Choi
C
enabled, we need
to disable dmc, since dcf only base on one vop vblank time, so the
other panel will flicker when do ddr frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v6:
- fix a build error
Changes in v
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v6:
- None
Changes in v5:
- fit for the ddr type
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_sr
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v6:
- none
Changes in v5:
-
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (8):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bi
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../bindings/devfreq/event/ro
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v7:
-access need to *4 to get right DDR loading
Changes
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v7:
-None
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v7:
-None
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../bi
frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v7:
- None
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
Changes in v4:
- register notifier to devfreq_register_no
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v7:
-None
Changes in v6:
-Add more detail in Documentation
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v7:
- remove a blank line
Changes in v6:
-
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v7:
- add rockchip_ddrclk_sip_ops
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v7:
- change SCLK_DDRC name from clk_ddrc to sclk_ddrc
Changes in v6:
- None
Changes in v5:
- fit for the ddr type
Changes in v4:
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (8):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
there define two devfreq_event_get_drvdata() function in devfreq-event.h
when disable CONFIG_PM_DEVFREQ_EVENT, it will lead to build fail. So
remove devfreq_event_get_drvdata() function.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
include/linux/devfreq-event.h | 5 -
1 file chan
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (5):
Documentation: bindings: add dt documentation for dfi controller
PM / devfreq: event: support rockchip dfi cont
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Signed-off-by: MyngJoo Ham <myngjoo@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v9:
- None
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
Changes in v4:
- regis
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v9:
- add ddr timing property to node
Changes in v8:
- add ddr timing properties
Changes in v7:
- None
Changes in v6:
-Add more detail in Documentation
Changes
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Signed-off-by: MyungJoo Ham <myungjoo@samsung.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Ch
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v9:
- reorder compatible and reg
Changes in v8:
- delete a unuse blank line
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- None
Changes
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v8:
- delete a unuse blank line
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- None
Changes in v4:
- None
Changes in v3:
- None
Changes
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (5):
Documentation: bindings: add dt documentation for dfi controller
PM / devfreq: event: support rockchip dfi cont
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Signed-off-by: MyungJoo Ham <myungjoo@samsung.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Ch
frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
Changes in v4:
- regis
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v8:
- delete a unuse blank line
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- None
Changes in v4:
- None
Changes in v3:
- None
Changes
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (5):
Documentation: bindings: add dt documentation for dfi controller
PM / devfreq: event: support rockchip dfi cont
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v8:
- add ddr timing properties
Changes in v7:
-None
Changes in v6:
-Add more detail in Documentation
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Signed-off-by: MyngJoo Ham <myngjoo@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
C
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Signed-off-by: MyungJoo Ham <myungjoo@samsung.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Cha
frequency scaling.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v10:
- None
Changes in v9:
- None
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
C
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v10:
- None
Changes in v9:
- reorder compatible and reg
Changes in v8:
- delete a unuse blank line
C
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Signed-off-by: MyngJoo Ham <myngjoo@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang <h...@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.c...@samsung.com>
---
Changes in v10:
- add rockchip prefix in property describe
Changes in v9:
- add ddr timing property to node
Changes
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (5):
Documentation: bindings: add dt documentation for dfi controller
PM / devfreq: event: support rockchip dfi cont
Add suspend frequency support and if needed set it to
the frequency obtained from the suspend opp (can be defined
using opp-v2 bindings and is optional).
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- use update_devfreq() instead devfreq_update_status()
Changes in v3:
Add suspend frequency support and if needed set it to
the frequency obtained from the suspend opp (can be defined
using opp-v2 bindings and is optional).
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- use update_devfreq() instead devfreq_update_status()
Changes in v3:
Add suspend frequency support and if needed set it to
the frequency obtained from the suspend opp (can be defined
using opp-v2 bindings and is optional).
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- use update_devfreq() instead devfreq_update_status()
Changes in v3:
We need ddr run a specific frequency when ddr dvfs stop
working. For example: if we enable two monitor, then we will
stop ddr dvfs, but we hope ddr can run in highest frequency
obviously.
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- None
Changes in v3:
- None
d
Add suspend frequency support and if needed set it to
the frequency obtained from the suspend opp (can be defined
using opp-v2 bindings and is optional).
Signed-off-by: Lin Huang <h...@rock-chips.com>
---
Changes in v2:
- use update_devfreq() instead devfreq_update_status()
Changes in v3:
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