[RFC PATCH 16/20] coresight: etm-perf: implementing trace related APIs

Implementing the API that connect trace control, i.e initiation and termination, to the Perf core. That way trace collection can be started when the process it is associated to is executed by a CPU, and stopped when yanked away. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[RFC PATCH 06/20] coresight: etm3x: unlocking tracer in default arch init

to 'smp_call_function_single()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c

[RFC PATCH 19/20] coresight: etm3x: implementing perf's user/kernel mode

. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 36 +++ 1 file changed, 36 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c

[RFC PATCH 15/20] coresight: etm-perf: implementing 'setup_aux()' API

-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index a21171

[RFC PATCH 20/20] coresight: updating documentation to reflect integration with perf

Adding a new section giving information on how coresight has been integrated with the perf subsystem along with a general idea of how to control tracing from the perf tool cmd line. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- Documentation/trace/coresight.txt

[RFC PATCH 13/20] coresight: etm-perf: new PMU driver for ETM tracers

Perf is a well known and used tool for performance monitoring and much more. A such it is an ideal condaditate for integration with coresight based HW tracing. This patch introduce a minimal PMU that represent a coresight tracer to the Perf core. Signed-off-by: Mathieu Poirier <mathieu.p

[RFC PATCH 17/20] coresight: etm-perf: adding symbolic link for CPUs

/sys/bus/event_source/devices/cs_etm/cpuX that reference the coresight device a CPU is associated with. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 22 +++ drivers/hwtracing/coresight/coresight-etm-perf.

[RFC PATCH 18/20] coresight: etm3x: pushing down perf configuration to tracer

were set. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 12 +-- drivers/hwtracing/coresight/coresight-etm3x.c| 27 +++- include/linux/coresight.h| 3 ++- 3 files chang

[RFC PATCH 14/20] coresight: etm-perf: implementing 'event_init()' API

Enhancing skeleton PMU with event initialisation. The function makes sure tracers aren't already enabled before going through with the powe up and configuration sequences. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm-perf.c

[RFC PATCH 12/20] coresight: keeping track of enabled sink buffers

Keep track of enabled sink buffers as paths between source and sinks are being built. That way sinks associated to a source can be accessed quickly. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-priv.h | 3 ++- drivers/hwtracing/cor

[RFC PATCH 11/20] coresight: making coresight_build_paths() public

That way a path can be built outside of the core framework, something useful when a PMU is initialised from the perf sub system. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-priv.h | 3 +++ drivers/hwtracing/coresight/coresight.c

[RFC PATCH 10/20] coresight: etb10: adding snapshot mode feature

by not checking for the end of the ring buffer and setting the 'head' of the buffer to the next available address. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etb10.c | 30 +++ 1 file changed, 26 insertions(+), 4 del

[RFC PATCH 03/20] coresight: etm3x: implementing 'cpu_id()' API

Adding an interface to lookup the CPU a tracer has been affined to along with a source operation allowing external customers to access it. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 14 ++ include/linux/cores

[RFC PATCH 04/20] coresight: etm3x: using chip logic to start/stop traces

Driving the external ETMEN pins to start and stop trace collection isn't reliable when doing rapid, successive trace collection runs. Using the internal event enable register logic to control tracing is much more dependable. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[RFC PATCH 08/20] coresight: etb10: implementing buffer set and unset APIs

Implementing perf related APIs to activate and terminate a trace session. More specifically dealing with the sink buffer's internal mechanic along with perf's API to start and stop interactions with the ring buffers. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- d

[RFC PATCH 05/20] coresight: etm3x: adapting default tracer setting for perf

The perf command line tool has options to trace in kernel or user space mode. As such configuring tracers to trace the entire address range, leaving to the perf mechanic the task of collecting traces in accordance with the requested mode. Signed-off-by: Mathieu Poirier <mathieu.p

[RFC PATCH 09/20] coresight: etb10: implementing buffer update API

Implementing buffer API to update the location of the ETB internal ring buffer once a trace session has ended. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etb10.c | 113 ++ include/linux/cores

[RFC PATCH 01/20] coresight: etm3x: splitting 'etm_enable_hw()' operations

When dealing with other kernel subsystems or automated tools it is desirable to split the current etm_enable_hw() operation in three: power up, configuration and enabling of the tracer. That way it is possible to have more control on the operations done by a tracer. Signed-off-by: Mathieu

[RFC PATCH 07/20] coresight: etb10: implementing the setup_aux() API

Adding an ETB10 specific auxiliary area setup operation to be used by the perf framework when events are initialised. Part of this operation involves modeling the mmap'ed area based on the specific ways a sink buffer gathers information. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[RFC PATCH 00/20] Coresight integration with perf

]. It is based on v4.2 but a rebase to v4.3-rcX will be available shortly. Best regards, Mathieu [1]. https://git.linaro.org/people/mathieu.poirier/coresight.git/shortlog/refs/heads/perf-v4.2 Mathieu Poirier (20): coresight: etm3x: splitting 'etm_enable_hw()' operations coresight: etm3x

[RFC PATCH 02/20] coresight: etm3x: implementing 'is_enabled()' API

Adding an interface to lookup the status of a tracer along with a source operation allowing external customers to access it. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 13 + include/linux/cores

Re: [PATCH V6 00/26] Coresight integration with perf

On 3 December 2015 at 14:04, Mathieu Poirier <mathieu.poir...@linaro.org> wrote: > This patchset aims to integrate configuration and control of > the Coresight tracers with the perf sub-system. > > The goal is to use PMUs to represent tracers and the auxiliary > buffer e

Re: [PATCH V6 00/26] Coresight integration with perf

On 3 December 2015 at 14:04, Mathieu Poirier <mathieu.poir...@linaro.org> wrote: > This patchset aims to integrate configuration and control of > the Coresight tracers with the perf sub-system. > > The goal is to use PMUs to represent tracers and the auxiliary > buffer e

Re: [PATCH] staging: skein: macros moved to header file

On 4 December 2015 at 00:09, Sanidhya Solanki wrote: > Staging: Skein: Moved macros from skein_block.c to header file. > > The original code defined macros in the source code, making it harder to > read. Move them to the header file. The patch didn't end up mangled on my side

[PATCH V6 21/26] coresight: etm-perf: new PMU driver for ETM tracers

com> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Makefile | 3 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 447 +++ drivers/hwtracing/coresight/coresight-etm-perf.h | 32 ++ drivers/hwtraci

[PATCH V6 19/26] coresight: updating documentation to reflect integration with perf

Adding a new section giving information on how coresight has been integrated with the perf subsystem along with a general idea of how to control tracing from the perf tool cmd line. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- Documentation/trace/coresight.txt

[PATCH V6 13/26] coresight: etm3x: implementing user/kernel mode tracing

Adding new mode to limit tracing to kernel or user space. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h| 7 ++- .../hwtracing/coresight/coresight-etm3x-sysfs.c| 4 ++ drivers/hwtracing/coresight/coresight-e

[PATCH V6 14/26] coresight: etm3x: adding perf_get/set_config() API

, the possibility of associating a tracer with a configuration is also provided. As such Perf can assign session configuration to tracers as it see fit. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/cor

[PATCH V6 06/26] coresight: associating path with session rather than tracer

methods a per-cpu place holder is used to keep a handle on the path built when tracers are enabled. Lastly APIs to build paths and enable tracers are made public so that other subsystem can interact with the Coresight framework. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- d

[PATCH V6 08/26] coresight: etm3x: adding operation mode for etm_enable()

Adding a new mode to source API enable() in order to distinguish where the request comes from. That way it is possible to perform different operations based on where the request was issued from. The ETM4x driver is also modified to keep in sync with the new interface. Signed-off-by: Mathieu

[PATCH V6 05/26] coresight: etm3x: implementing 'cpu_id()' API

Other than plainly parsing the device tree there is no way to know which CPU a tracer is affined to. As such adding an interface to lookup the CPU field enclosed in the etm_drvdata structure that was initialised at boot time. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V6 00/26] Coresight integration with perf

changes and rebased everything to v4.3-rc5. Mathieu Poirier (26): coresight: etm3x: moving etm_readl/writel to header file coresight: etm3x: moving sysFS entries to dedicated file coresight: etm3x: unlocking tracers in default arch init coresight: etm3x: splitting struct etm_drvdata coresight:

[PATCH V6 02/26] coresight: etm3x: moving sysFS entries to dedicated file

SysFS entries are big enough to justify their own file. As such moving all sysFS related declarations to a dedicated location. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Makefile |3 +- drivers/hwtracing/coresight/coresight

[PATCH V6 10/26] coresight: etm3x: set progbit to stop trace collection

There is no need to use the event enable's "always false" event to stop trace collection. For that purpose setting the programming bit (ETMCR:10) is enough. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 3 --- 1

[PATCH V6 12/26] coresight: etm3x: consolidating initial config

There is really no point in having two functions to take care of doing the initials tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.

[PATCH V6 17/26] coresight: adding operation mode for sink->enable()

Adding an operation mode to sink->enable() API in order to prevent simultaneous access from different callers. TPIU and TMC won't be supplemented with the AUX area API immediately and as such ignore the new mode. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/

[PATCH V6 01/26] coresight: etm3x: moving etm_readl/writel to header file

Moving functions etm_readl/writel to file "coresight-etm.h" so that the main ETM3x driver can be split in more than one file. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h | 29 +++ d

[PATCH V6 23/26] perf tools: making function set_max_cpu_num() non static

by cpu__max_cpu(). Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/util/cpumap.c | 2 +- tools/perf/util/cpumap.h | 1 + 2 fil

[PATCH V6 25/26] perf tools: making coresight PMU listable

Adding the required mechanic allowing 'perf list pmu' to discover coresight ETM/PTM tracers. Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V6 22/26] coresight: introducing a global trace ID function

TraceID values have to be unique for all tracers and consistent between drivers and user space. As such introducing a central function to be used whenever a traceID value is required. The patch also account for data traceIDs, which are usually I(N) + 1. Signed-off-by: Mathieu Poirier

[PATCH V6 04/26] coresight: etm3x: splitting struct etm_drvdata

the code affected by this new arrangement. No loss or gain of functionality (other than what is mentioned above) is introduced by this patch. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h| 102 ++--- .../hwtracing/coresi

[PATCH V6 09/26] coresight: add API to get sink from path

Add an API allowing external code to quickly get a handle on the sink within a path. The sink is always last, but adding an API allows to keep the path's node structure private and remove redundant checks. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwt

[PATCH V6 11/26] coresight: etm3x: changing default trace configuration

Changing default configuration to include the entire address range rather than just the kernel. That way traces are more inclusive and it is easier to narrow down if needed. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h

Re: [PATCH 5/7] perf: Document aux api usage

s this requirement for perf_aux_output_{begin,end}() > apis. > > Signed-off-by: Alexander Shishkin <alexander.shish...@linux.intel.com> > Cc: Mathieu Poirier <mathieu.poir...@linaro.org> > --- > kernel/events/ring_buffer.c | 10 ++ > 1 file changed, 10 insertions(+) &g

[PATCH V6 20/26] perf: changing pmu::setup_aux() parameter to include event

@kernel.org> Cc: Alexander Shishkin <alexander.shish...@linux.intel.com> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- arch/x86/kernel/cpu/perf_event_intel_bts.c | 4 +++- arch/x86/kernel/cpu/perf_event_intel_pt.c | 5 +++-- include/linux/perf_event.h | 2 +

[PATCH V6 26/26] perf tools: adding coresight etm PMU record capabilities

alho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS | 3 + tools/perf/arch/arm/util/Build | 2 +- tools/perf/arch/arm/util/auxtrace.c | 48 tools/perf/arch/a

[PATCH V6 15/26] coresight: etm3x: implementing perf_enable/disable() API

That way traces can be enabled and disabled automatically from the Perf subystem using the PMU abstraction. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 47 --- 1 file changed, 43 insertions

[PATCH V6 24/26] perf tools: adding perf_evlist to *info_priv_size()

parameter into account. Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/arch/x86/util/intel-bts.c | 4 +++- tools/

[PATCH V6 16/26] coresight: etb10: moving to local atomic operations

Moving to use local atomic operations to take advantage of the lockless implementation, something that will come handy when the ETB is accessed from the Perf subsystem. Also changing the name of the variable to something more meaningful. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V6 18/26] coresight: etb10: implementing AUX space API

Adding an ETB10 specific AUX area operations to be used by the perf framework when events are initialised. Part of this operation involves modeling the mmap'ed area based on the specific ways a sink buffer gathers information. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V6 03/26] coresight: etm3x: unlocking tracers in default arch init

to 'smp_call_function_single()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-e

[PATCH V6 07/26] coresight: moving PM runtime operations to core framework

Moving PM runtime operations in Coresight devices enable() and disable() API to the framework core when a path is setup. That way the runtime core doesn't have to be involved everytime a path is enabled. It also avoids calling runtime PM operations in IRQ context. Signed-off-by: Mathieu Poirier

Re: [PATCH V5 21/26] coresight: etm-perf: new PMU driver for ETM tracers

On 30 November 2015 at 16:23, Alexander Shishkin <alexander.shish...@linux.intel.com> wrote: > Mathieu Poirier <mathieu.poir...@linaro.org> writes: > >> +static void etm_event_destroy(struct perf_event *event) {} >> + >> +static int etm_event_init(struct perf_ev

Re: [PATCH V6 00/26] Coresight integration with perf

On 8 December 2015 at 13:34, Arnaldo Carvalho de Melo <a...@kernel.org> wrote: > Em Tue, Dec 08, 2015 at 01:29:00PM -0700, Mathieu Poirier escreveu: >> On 3 December 2015 at 14:04, Mathieu Poirier <mathieu.poir...@linaro.org> >> wrote: >> >> Arnaldo, Pete

Re: [PATCH V6 18/26] coresight: etb10: implementing AUX space API

On 11 December 2015 at 07:00, Alexander Shishkin <alexander.shish...@linux.intel.com> wrote: > Mathieu Poirier <mathieu.poir...@linaro.org> writes: > >> +static void *etb_get_config(struct coresight_device *csdev, int cpu, >> + void **pages

Re: [PATCH V6 21/26] coresight: etm-perf: new PMU driver for ETM tracers

On 11 December 2015 at 08:18, Alexander Shishkin <alexander.shish...@linux.intel.com> wrote: > Mathieu Poirier <mathieu.poir...@linaro.org> writes: > >> +static void etm_event_start(struct perf_event *event, int flags) >> +{ >> + int cpu = smp_processo

Re: [PATCH V6 20/26] perf: changing pmu::setup_aux() parameter to include event

On 11 December 2015 at 07:12, Alexander Shishkin <alexander.shish...@linux.intel.com> wrote: > Mathieu Poirier <mathieu.poir...@linaro.org> writes: > >> For Coresight ETMv3/4 tracers the event carries information >> about trace modes such as user or kernel space

Re: [PATCH v0 0/5] perf: Introduce instruction trace filtering

On 11 December 2015 at 06:36, Alexander Shishkin wrote: > Hi Peter, > > Newer version of Intel PT supports address-based filtering, and this > patchset adds support for it to perf core and the PT pmu driver. It > works by configuring a number of address ranges

Re: [PATCH v0 0/5] perf: Introduce instruction trace filtering

On 14 December 2015 at 01:50, Alexander Shishkin <alexander.shish...@linux.intel.com> wrote: > Mathieu Poirier <mathieu.poir...@linaro.org> writes: > >> On 11 December 2015 at 06:36, Alexander Shishkin >> <alexander.shish...@linux.intel.com> wrote: >>

Re: [PATCH v0 3/5] perf: Introduce instruction trace filtering

On 11 December 2015 at 06:36, Alexander Shishkin wrote: > Many instruction trace pmus out there support address range-based > filtering, which would, for example, generate trace data only for a > given range of instruction addresses, which is useful for tracing

Re: [PATCH v0 5/5] perf/x86/intel/pt: Add support for instruction trace filtering in PT

pt_pmu.pmu.read = pt_event_read; > pt_pmu.pmu.setup_aux= pt_buffer_setup_aux; > pt_pmu.pmu.free_aux = pt_buffer_free_aux; > + pt_pmu.pmu.itrace_filter_setup = > + pt_event_itrace_filter_setup; > ret = perf_pmu_register(_pmu

[PATCH 1/2] coresight: checking for NULL string in coresight_name_match()

: <sta...@vger.kernel.org> # v3.18+ Reported-by: Tyler Baker <tyler.ba...@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresi

[PATCH 0/2] coresight: next v4.4-rc5

Good day Greg, Please queue the following patches for the 4.5 cycle. Regards, Mathieu Andrew F. Davis (1): coresight: Fix a typo in Kconfig Mathieu Poirier (1): coresight: checking for NULL string in coresight_name_match() drivers/hwtracing/coresight/Kconfig | 2 +- drivers/hwtracing

[PATCH 2/2] coresight: Fix a typo in Kconfig

From: "Andrew F. Davis" <a...@ti.com> Signed-off-by: Andrew F. Davis <a...@ti.com> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hw

Re: [PATCH] Staging: Skein: Moved macros from skein_block.c to header file.

On 14 December 2015 at 17:08, Sanidhya Solanki wrote: > The original code defined macros in the source code, making it > harder to read. Moved them to the header file, as per the TODO file. > > Updated the TODO file. > > Signed-off-by: Sanidhya Solanki

Re: [PATCH V7 02/24] coresight: associating path with session rather than tracer

On 20 December 2015 at 08:29, Rabin Vincent <ra...@rab.in> wrote: > On Fri, Dec 18, 2015 at 01:58:58PM -0700, Mathieu Poirier wrote: >> When using the Coresight framework from the sysFS interface a >> tracer is always handling a single session and as such, a path >> can

Re: [PATCH V7 00/24] Coresight integration with perf

On 19 December 2015 at 10:42, Rabin Vincent <ra...@rab.in> wrote: > On Fri, Dec 18, 2015 at 01:58:56PM -0700, Mathieu Poirier wrote: >> This patchset aims to integrate configuration and control of >> the Coresight tracers with the perf sub-system. >> >> The goal is

Re: [PATCH V7 04/24] coresight: moving PM runtime operations to core framework

On 19 December 2015 at 10:13, Rabin Vincent <ra...@rab.in> wrote: > On Fri, Dec 18, 2015 at 01:59:00PM -0700, Mathieu Poirier wrote: >> @@ -415,9 +418,13 @@ struct list_head *coresight_build_path(struct >> coresight_device *csdev) >> */ >> void coresight_re

Re: [PATCH V7 02/24] coresight: associating path with session rather than tracer

On 20 December 2015 at 08:29, Rabin Vincent <ra...@rab.in> wrote: > On Fri, Dec 18, 2015 at 01:58:58PM -0700, Mathieu Poirier wrote: >> When using the Coresight framework from the sysFS interface a >> tracer is always handling a single session and as such, a path >> can

Re: [PATCH V7 24/24] perf tools: adding coresight etm PMU record capabilities

On 19 December 2015 at 10:27, Rabin Vincent <ra...@rab.in> wrote: > On Fri, Dec 18, 2015 at 01:59:20PM -0700, Mathieu Poirier wrote: >> +struct auxtrace_record >> +*auxtrace_record__init(struct perf_evlist *evlist, int *err) >> +{ >> + struct perf_pmu *cs_et

Re: [PATCH V7 17/24] coresight: etb10: implementing AUX space API

On 19 December 2015 at 10:23, Rabin Vincent <ra...@rab.in> wrote: > On Fri, Dec 18, 2015 at 01:59:13PM -0700, Mathieu Poirier wrote: >> +static void etb_update_buffer(struct coresight_device *csdev, >> + struct perf_

[PATCH V7 20/24] coresight: introducing a global trace ID function

TraceID values have to be unique for all tracers and consistent between drivers and user space. As such introducing a central function to be used whenever a traceID value is required. The patch also account for data traceIDs, which are usually I(N) + 1. Signed-off-by: Mathieu Poirier

[PATCH V7 24/24] perf tools: adding coresight etm PMU record capabilities

alho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS | 3 + tools/perf/arch/arm/util/Build | 2 +- tools/perf/arch/arm/util/auxtrace.c | 48 tools/perf/arch/a

[PATCH V7 23/24] perf tools: making coresight PMU listable

Adding the required mechanic allowing 'perf list pmu' to discover coresight ETM/PTM tracers. Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V7 22/24] perf tools: adding perf_evlist to *info_priv_size()

parameter into account. Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/arch/x86/util/intel-bts.c | 4 +++- tools/

[PATCH V7 00/24] Coresight integration with perf

rface from driver core to dedicated file. * Removed spinlock in "etm_cpu_id()". * Aggregated PMU driver pieces in a single patch. * Added user space changes and rebased everything to v4.3-rc5. Mathieu Poirier (24): coresight: implementing 'cpu_id()' API coresight: associating path with

[PATCH V7 01/24] coresight: implementing 'cpu_id()' API

Other than plainly parsing the device tree there is no way to know which CPU a tracer is affined to. As such adding an interface to lookup the CPU field enclosed in the etm_drvdata structure that was initialised at boot time. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V7 07/24] coresight: etm3x: unlocking tracers in default arch init

to 'smp_call_function_single()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-e

[PATCH V7 10/24] coresight: etm3x: set progbit to stop trace collection

There is no need to use the event enable's "always false" event to stop trace collection. For that purpose setting the programming bit (ETMCR:10) is enough. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 3 --- 1

[PATCH V7 11/24] coresight: etm3x: changing default trace configuration

Changing default configuration to include the entire address range rather than just the kernel. That way traces are more inclusive and it is easier to narrow down if needed. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h

[PATCH V7 17/24] coresight: etb10: implementing AUX space API

Adding an ETB10 specific AUX area operations to be used by the perf framework when events are initialised. Part of this operation involves modeling the mmap'ed area based on the specific ways a sink buffer gathers information. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V7 15/24] coresight: etb10: moving to local atomic operations

Moving to use local atomic operations to take advantage of the lockless implementation, something that will come handy when the ETB is accessed from the Perf subsystem. Also changing the name of the variable to something more meaningful. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V7 12/24] coresight: etm3x: consolidating initial config

There is really no point in having two functions to take care of doing the initial tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.

[PATCH V7 18/24] coresight: updating documentation to reflect integration with perf

Adding a new section giving information on how coresight has been integrated with the perf subsystem along with a general idea of how to control tracing from the perf tool cmd line. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- Documentation/trace/coresight.txt

[PATCH V7 13/24] coresight: etm3x: implementing user/kernel mode tracing

Adding new mode to limit tracing to kernel or user space. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h| 6 ++- .../hwtracing/coresight/coresight-etm3x-sysfs.c| 4 ++ drivers/hwtracing/coresight/coresight-e

[PATCH V7 14/24] coresight: etm3x: implementing perf_enable/disable() API

That way traces can be enabled and disabled automatically from the Perf subystem using the PMU abstraction. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/coresight/coresight-etm3x.

[PATCH V7 21/24] perf tools: making function set_max_cpu_num() non static

by cpu__max_cpu(). Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/util/cpumap.c | 2 +- tools/perf/util/cpumap.h | 1 + 2 fil

[PATCH V7 19/24] coresight: etm-perf: new PMU driver for ETM tracers

com> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Makefile | 3 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 386 +++ drivers/hwtracing/coresight/coresight-etm-perf.h | 32 ++ drivers/hwtraci

[PATCH V7 06/24] coresight: etm3x: moving sysFS entries to dedicated file

SysFS entries are big enough to justify their own file. As such moving all sysFS related declarations to a dedicated location. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Makefile |3 +- drivers/hwtracing/coresight/coresight

[PATCH V7 08/24] coresight: etm3x: splitting struct etm_drvdata

l the code affected by this new arrangement. No loss or gain of functionality (other than what is mentioned above) is introduced by this patch. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h| 102 .../hwtracing/cor

[PATCH V7 09/24] coresight: etm3x: adding operation mode for etm_enable()

Adding a new mode to source API enable() in order to distinguish where the request comes from. That way it is possible to perform different operations based on where the request was issued from. The ETM4x driver is also modified to keep in sync with the new interface. Signed-off-by: Mathieu

[PATCH V7 16/24] coresight: etb10: adding operation mode for sink->enable()

Adding an operation mode to the sink->enable() API in order to prevent simultaneous access from different callers. TPIU and TMC won't be supplemented with the AUX area API immediately and as such ignore the new mode. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> ---

[PATCH V7 04/24] coresight: moving PM runtime operations to core framework

Moving PM runtime operations in Coresight devices enable() and disable() API to the framework core when a path is setup. That way the runtime core doesn't have to be involved everytime a path is enabled. It also avoids calling runtime PM operations in IRQ context. Signed-off-by: Mathieu Poirier

[PATCH V7 05/24] coresight: etm3x: moving etm_readl/writel to header file

Moving functions etm_readl/writel to file "coresight-etm.h" so that the main ETM3x driver can be split in more than one file. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h | 29 +++ d

[PATCH V7 02/24] coresight: associating path with session rather than tracer

methods a per-cpu place holder is used to keep a handle on the path built when tracers are enabled. Lastly APIs to build paths and enable tracers are made public so that other subsystem can interact with the Coresight framework. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- d

[PATCH V7 03/24] coresight: add API to get sink from path

Add an API allowing external code to quickly get a handle on the sink within a path. The sink is always last, but adding an API allows to keep the path's node structure private and remove redundant checks. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwt

[RESEND PATCH V4 14/26] coresight: etm3x: adding perf_get/set_config() API

, the possibility of associating a tracer with a configuration is also provided. As such Perf can assign session configuration to tracers as it see fit. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/cor

[RESEND PATCH V4 00/26] Coresight integration with perf

nterface from driver core to dedicated file. * Removed spinlock in "etm_cpu_id()". * Aggregated PMU driver pieces in a single patch. * Added user space changes and rebased everything to v4.3-rc5. Mathieu Poirier (26): coresight: etm3x: moving etm_readl/writel to header file coresigh

[RESEND PATCH V4 07/26] coresight: moving PM runtime operations to core framework

Moving PM runtime operations in Coresight devices enable() and disable() API to the framework core when a path is setup. That way the runtime core doesn't have to be involved everytime a path is enabled. It also avoids calling runtime PM operations in IRQ context. Signed-off-by: Mathieu Poirier

[RESEND PATCH V4 11/26] coresight: etm3x: changing default trace configuration

Changing default configuration to include the entire address range rather than just the kernel. That way traces are more inclusive and it is easier to narrow down if needed. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h

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