[RESEND PATCH V4 23/26] perf tools: making function set_max_cpu_num() non static

by cpu__max_cpu(). Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/util/cpumap.c | 2 +- tools/perf/util/cpumap.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/cpumap.c b/tools/perf/util/cpumap.c index 3667e2123e5b..97ef46e4a0f6

[RESEND PATCH V4 22/26] coresight: updating documentation to reflect integration with perf

Adding a new section giving information on how coresight has been integrated with the perf subsystem along with a general idea of how to control tracing from the perf tool cmd line. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- Documentation/trace/coresight.txt

[RESEND PATCH V4 25/26] perf tools: making coresight PMU listable

Adding the required mechanic allowing 'perf list pmu' to discover coresight ETM/PTM tracers. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS| 1 + tools/perf/arch/arm/util/Build | 2 ++ tools/perf/arch/arm/util/pmu.

[RESEND PATCH V4 13/26] coresight: etm3x: implementing user/kernel mode tracing

Adding new mode to limit tracing to kernel or user space. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h| 7 ++- .../hwtracing/coresight/coresight-etm3x-sysfs.c| 4 ++ drivers/hwtracing/coresight/coresight-e

[RESEND PATCH V4 12/26] coresight: etm3x: consolidating initial config

There is really no point in having two functions to take care of doing the initials tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.

[RESEND PATCH V4 06/26] coresight: associating path with session rather than tracer

methods a per-cpu place holder is used to keep a handle on the path built when tracers are enabled. Lastly APIs to build paths and enable tracers are made public so that other subsystem can interact with the Coresight framework. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- d

[RESEND PATCH V4 08/26] coresight: etm3x: adding operation mode for etm_enable()

Adding a new mode to source API enable() in order to distinguish where the request comes from. That way it is possible to perform different operations based on where the request was issued from. The ETM4x driver is also modified to keep in sync with the new interface. Signed-off-by: Mathieu

[RESEND PATCH V4 26/26] perf tools: adding coresight etm PMU record capabilities

Coresight ETMs are IP blocks used to perform HW assisted tracing on a CPU core. This patch introduce the required auxiliary API functions allowing the perf core to interact with a tracer. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS

[RESEND PATCH V4 20/26] coresight: etm-perf: new PMU driver for ETM tracers

Perf is a well known and used tool for performance monitoring and much more. A such it is an ideal candidate for integration with coresight based HW tracing. This patch introduces a PMU that represent a coresight tracer to the Perf core. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[RESEND PATCH V4 24/26] perf tools: adding perf_session to *info_prive_size()

parameter into account. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/arch/x86/util/intel-bts.c | 4 +++- tools/perf/arch/x86/util/intel-pt.c | 4 +++- tools/perf/util/auxtrace.c | 7 --- tools/perf/util/auxtrace.h | 6 -- 4 f

[RESEND PATCH V4 21/26] coresight: introducing a global trace ID function

TraceID values have to be unique for all tracers and consistent between drivers and user space. As such introducing a central function to be used whenever a traceID value is required. The patch also account for data traceIDs, which are usually I(N) + 1. Signed-off-by: Mathieu Poirier

[RESEND PATCH V4 16/26] perf: changing pmu::setup_aux() parameter to include event

to be of type struct perf_event * so that all the necessary information can be conveyed. Also changing current customer of the API to reflect the modification. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- arch/x86/kernel/cpu/perf_event_intel_bts.c | 4 +++- arch/x86/kern

[RESEND PATCH V4 19/26] coresight: etb10: implementing AUX space API

Adding an ETB10 specific AUX area operations to be used by the perf framework when events are initialised. Part of this operation involves modeling the mmap'ed area based on the specific ways a sink buffer gathers information. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[RESEND PATCH V4 18/26] coresight: adding operation mode for sink->enable()

Adding an operation mode to sink->enable() API in order to prevent simultaneous access from different callers. TPIU and TMC won't be supplemented with the AUX area API immediately and as such ignore the new mode. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/

[RESEND PATCH V4 15/26] coresight: etm3x: implementing perf_enable/disable() API

That way traces can be enabled and disabled automatically from the Perf subystem using the PMU abstraction. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 47 --- 1 file changed, 43 insertions

[RESEND PATCH V4 17/26] coresight: etb10: moving to local atomic operations

Moving to use local atomic operations to take advantage of the lockless implementation, something that will come handy when the ETB is accessed from the Perf subsystem. Also changing the name of the variable to something more meaningful. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[RESEND PATCH V4 10/26] coresight: etm3x: set progbit to stop trace collection

There is no need to use the event enable's "always false" event to stop trace collection. For that purpose setting the programming bit (ETMCR:10) is enough. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 3 --- 1

[RESEND PATCH V4 09/26] coresight: add API to get sink from path

Add an API allowing external code to quickly get a handle on the sink within a path. The sink is always last, but adding an API allows to keep the path's node structure private and remove redundant checks. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwt

[RESEND PATCH V4 03/26] coresight: etm3x: unlocking tracers in default arch init

to 'smp_call_function_single()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-e

[RESEND PATCH V4 05/26] coresight: etm3x: implementing 'cpu_id()' API

Other than plainly parsing the device tree there is no way to know which CPU a tracer is affined to. As such adding an interface to lookup the CPU field enclosed in the etm_drvdata structure that was initialised at boot time. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[RESEND PATCH V4 02/26] coresight: etm3x: moving sysFS entries to dedicated file

SysFS entries are big enough to justify their own file. As such moving all sysFS related declarations to a dedicated location. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Makefile |3 +- drivers/hwtracing/coresight/coresight

[RESEND PATCH V4 04/26] coresight: etm3x: splitting struct etm_drvdata

the code affected by this new arrangement. No loss or gain of functionality (other than what is mentioned above) is introduced by this patch. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h| 102 ++--- .../hwtracing/coresi

[RESEND PATCH V4 01/26] coresight: etm3x: moving etm_readl/writel to header file

Moving functions etm_readl/writel to file "coresight-etm.h" so that the main ETM3x driver can be split in more than one file. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h | 29 +++ d

[PATCH V5 01/26] coresight: etm3x: moving etm_readl/writel to header file

Moving functions etm_readl/writel to file "coresight-etm.h" so that the main ETM3x driver can be split in more than one file. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h | 29 +++ d

[PATCH V5 00/26] Coresight integration with perf

o sink_ops::reset_buffer(). * Moves ETM's sysFS interface from driver core to dedicated file. * Removed spinlock in "etm_cpu_id()". * Aggregated PMU driver pieces in a single patch. * Added user space changes and rebased everything to v4.3-rc5. Mathieu Poirier (26): coresight: etm3x: mov

[PATCH V5 02/26] coresight: etm3x: moving sysFS entries to dedicated file

SysFS entries are big enough to justify their own file. As such moving all sysFS related declarations to a dedicated location. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Makefile |3 +- drivers/hwtracing/coresight/coresight

[PATCH V5 03/26] coresight: etm3x: unlocking tracers in default arch init

to 'smp_call_function_single()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-e

[PATCH V5 13/26] coresight: etm3x: implementing user/kernel mode tracing

Adding new mode to limit tracing to kernel or user space. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h| 7 ++- .../hwtracing/coresight/coresight-etm3x-sysfs.c| 4 ++ drivers/hwtracing/coresight/coresight-e

[PATCH V5 08/26] coresight: etm3x: adding operation mode for etm_enable()

Adding a new mode to source API enable() in order to distinguish where the request comes from. That way it is possible to perform different operations based on where the request was issued from. The ETM4x driver is also modified to keep in sync with the new interface. Signed-off-by: Mathieu

[PATCH V5 07/26] coresight: moving PM runtime operations to core framework

Moving PM runtime operations in Coresight devices enable() and disable() API to the framework core when a path is setup. That way the runtime core doesn't have to be involved everytime a path is enabled. It also avoids calling runtime PM operations in IRQ context. Signed-off-by: Mathieu Poirier

[PATCH V5 06/26] coresight: associating path with session rather than tracer

methods a per-cpu place holder is used to keep a handle on the path built when tracers are enabled. Lastly APIs to build paths and enable tracers are made public so that other subsystem can interact with the Coresight framework. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- d

[PATCH V5 10/26] coresight: etm3x: set progbit to stop trace collection

There is no need to use the event enable's "always false" event to stop trace collection. For that purpose setting the programming bit (ETMCR:10) is enough. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 3 --- 1

[PATCH V5 05/26] coresight: etm3x: implementing 'cpu_id()' API

Other than plainly parsing the device tree there is no way to know which CPU a tracer is affined to. As such adding an interface to lookup the CPU field enclosed in the etm_drvdata structure that was initialised at boot time. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V5 15/26] coresight: etm3x: implementing perf_enable/disable() API

That way traces can be enabled and disabled automatically from the Perf subystem using the PMU abstraction. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.c | 47 --- 1 file changed, 43 insertions

[PATCH V5 17/26] coresight: adding operation mode for sink->enable()

Adding an operation mode to sink->enable() API in order to prevent simultaneous access from different callers. TPIU and TMC won't be supplemented with the AUX area API immediately and as such ignore the new mode. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/

[PATCH V5 20/26] perf: changing pmu::setup_aux() parameter to include event

org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- arch/x86/kernel/cpu/perf_event_intel_bts.c | 4 +++- arch/x86/kernel/cpu/perf_event_intel_pt.c | 5 +++-- include/linux/perf_event.h | 2 +- kernel/events/ring_buffer.c| 2 +- 4 files cha

[PATCH V5 18/26] coresight: etb10: implementing AUX space API

Adding an ETB10 specific AUX area operations to be used by the perf framework when events are initialised. Part of this operation involves modeling the mmap'ed area based on the specific ways a sink buffer gathers information. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V5 22/26] coresight: introducing a global trace ID function

TraceID values have to be unique for all tracers and consistent between drivers and user space. As such introducing a central function to be used whenever a traceID value is required. The patch also account for data traceIDs, which are usually I(N) + 1. Signed-off-by: Mathieu Poirier

[PATCH V5 24/26] perf tools: adding perf_session to *info_prive_size()

parameter into account. Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/arch/x86/util/intel-bts.c | 4 +++- tools/

[PATCH V5 26/26] perf tools: adding coresight etm PMU record capabilities

alho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS | 3 + tools/perf/arch/arm/util/Build | 2 +- tools/perf/arch/arm/util/auxtrace.c | 48 tools/perf/arch/a

[PATCH V5 25/26] perf tools: making coresight PMU listable

Adding the required mechanic allowing 'perf list pmu' to discover coresight ETM/PTM tracers. Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V5 23/26] perf tools: making function set_max_cpu_num() non static

by cpu__max_cpu(). Cc: Peter Zijlstra <a.p.zijls...@chello.nl> Cc: Ingo Molnar <mi...@redhat.com> Cc: Arnaldo Carvalho de Melo <a...@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- tools/perf/util/cpumap.c | 2 +- tools/perf/util/cpumap.h | 1 + 2 fil

[PATCH V5 19/26] coresight: updating documentation to reflect integration with perf

Adding a new section giving information on how coresight has been integrated with the perf subsystem along with a general idea of how to control tracing from the perf tool cmd line. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- Documentation/trace/coresight.txt

[PATCH V5 21/26] coresight: etm-perf: new PMU driver for ETM tracers

Perf is a well known and used tool for performance monitoring and much more. A such it is an ideal candidate for integration with coresight based HW tracing. This patch introduces a PMU that represent a coresight tracer to the Perf core. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V5 16/26] coresight: etb10: moving to local atomic operations

Moving to use local atomic operations to take advantage of the lockless implementation, something that will come handy when the ETB is accessed from the Perf subsystem. Also changing the name of the variable to something more meaningful. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.

[PATCH V5 14/26] coresight: etm3x: adding perf_get/set_config() API

, the possibility of associating a tracer with a configuration is also provided. As such Perf can assign session configuration to tracers as it see fit. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/cor

[PATCH V5 12/26] coresight: etm3x: consolidating initial config

There is really no point in having two functions to take care of doing the initials tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm3x.

[PATCH V5 09/26] coresight: add API to get sink from path

Add an API allowing external code to quickly get a handle on the sink within a path. The sink is always last, but adding an API allows to keep the path's node structure private and remove redundant checks. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwt

[PATCH V5 11/26] coresight: etm3x: changing default trace configuration

Changing default configuration to include the entire address range rather than just the kernel. That way traces are more inclusive and it is easier to narrow down if needed. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h

[PATCH V5 04/26] coresight: etm3x: splitting struct etm_drvdata

the code affected by this new arrangement. No loss or gain of functionality (other than what is mentioned above) is introduced by this patch. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-etm.h| 102 ++--- .../hwtracing/coresi

Re: [PATCH 1/2] regulator: Add coupled regulator

On 30 November 2015 at 08:29, Maxime Ripard wrote: > Some boards, in order to power devices that have a quite high power > consumption, wire multiple regulators in parallel. > > In such a case, the regulators need to be kept in sync, all of them being > enabled

Re: [PATCH] coresight: Fix erroneous memset in tmc_read_unprepare_etr

gt; [] task_work_run+0xb0/0xe4 > [] do_notify_resume+0x64/0x6c > [] work_pending+0x10/0x14 > Code: 91010108 544a 8b040108 cb050042 (d50b7428) > > Since we clear the buffer anyway in the following call to > tmc_etr_enable_hw(), remove the erroneous memset(). > > F

Re: [PATCH v2 3/9] coresight: Remove erroneous dma_free_coherent in tmc_probe

ge. The error path is consolidated in patch 8/9. > > Fixes: commit de5461970b3e9e194 ("coresight: tmc: allocating memory when > needed") > Cc: Mathieu Poirier <mathieu.poir...@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> > --- &

Re: [PATCH v2 9/9] coresight: Add better messages for coresight_timeout

we wait for. Also, one needs to lookup the > TRM to figure out, what was wrong. This patch changes all > such error messages to print something more meaningful. > > Cc: j...@perches.com > Cc: Mathieu Poirier <mathieu.poir...@linaro.org> > Signed-off-by: Suzuki K Poulose

Re: [PATCH v2 4/9] coresight: Fix csdev connections initialisation

ev->nr_outport check, > hence we don't try to dereference the ZERO_SIZE_PTR. This patch cleans > up the csdev->conns and csdev->refcnt, initialisation to make sure we This patch no longer deals with csdev->refcnt. > initialise it properly(i.e, either NULL or valid conns array). >

Re: [PATCH v2 4/9] coresight: Fix csdev connections initialisation

On 13 June 2016 at 02:54, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: > On 12/06/16 21:39, Mathieu Poirier wrote: >> >> On 6 June 2016 at 03:11, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: >>> >>> This is a cleanup patch. >>&g

[PATCH 2/3] coresight: Fix tmc_read_unprepare_etr

memory again. Cc: mathieu.poir...@linaro.org Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwt

[PATCH 0/3] coresight: fix for v4.7-rcX

Hi Greg, These 3 patches address problems that lead to kernel crashes. As such I think there is value in fixing them in this cycle rather than waiting for next merge window. Best regards, Mathieu Suzuki K Poulose (3): coresight: Fix NULL pointer dereference in _coresight_build_path

[PATCH 1/3] coresight: Fix NULL pointer dereference in _coresight_build_path

0/0x68 [] coresight_enable+0x74/0x1bc [] enable_source_store+0x3c/0x6c [] dev_attr_store+0x18/0x28 [] sysfs_kf_write+0x40/0x50 [] kernfs_fop_write+0x140/0x1cc [] __vfs_write+0x28/0x110 [] vfs_write+0xa0/0x174 [] SyS_write+0x44/0xa0 [] el0_svc_naked+0x24/0x28 Cc: Mathieu Poirier <mat

[PATCH 3/3] coresight: Fix erroneous memset in tmc_read_unprepare_etr

e clear the buffer anyway in the following call to tmc_etr_enable_hw(), remove the erroneous memset(). Fixes: commit de5461970b3e9e1 ("coresight: tmc: allocating memory when needed") Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.po

Re: [PATCH 2/5] coresight: etmv4: Fix ETMv4x peripheral ID table

JEP106 ID code > > The existing table entry checks only the bits [1:0], which is not > sufficient enough. Fix it to match bits [3:0], just like the other > entries do. While at it, correct the comment for A57 and the A53 entry. > > Cc: Mathieu Poirier <mathieu.poir.

Re: [PATCH 5/5] coresight: Cleanup TMC status check

On 31 May 2016 at 05:57, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: > Use the defined symbol rather than hardcoding the value to > check whether the TMC buffer is full. > > Cc: Mathieu Poirier <mathieu.poir...@linaro.org> > Signed-off-by: Suzuki K Poul

[PATCH 0/2] perf tools: coresight PMU recording capabilities

x0, x1 7fab583308: 54c1b.ne7fab583300 <free@plt+0x37c0> ... ... Regards, Mathieu [1]. http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/404232.html [2]. https://github.com/Linaro/OpenCSD/ [3]. http://pastebin.com/u9tgdwjF [4]. http://past

[PATCH 2/2] perf tools: adding coresight etm PMU record capabilities

Coresight ETMs are IP blocks used to perform HW assisted tracing on a CPU core. This patch introduce the required auxiliary API functions allowing the perf core to interact with a tracer. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS

Re: [PATCH 1/5] coresight: Fix NULL pointer dereference in _coresight_build_path

/0x50 > [] kernfs_fop_write+0x140/0x1cc > [] __vfs_write+0x28/0x110 > [] vfs_write+0xa0/0x174 > [] SyS_write+0x44/0xa0 > [] el0_svc_naked+0x24/0x28 > > Cc: Mathieu Poirier <mathieu.poir...@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poul...@ar

Re: [PATCH 3/5] coresight: Fix csdev connections initialisation

> is bounded by the csdev->nr_outport check, hence we don't try to dereference > the > ZERO_SIZE_PTR. This patch cleans up the csdev->conns and csdev->refcnt, > initialisation > to make sure we initialise it properly(i.e, either NULL or valid conns array). > > Cc: Mathieu Poirier <ma

Re: [PATCH 4/5] coresight: Add better messages for coresight_timeout

we wait for. Also, one needs to lookup the > TRM to figure out, what was wrong. This patch changes all > such error messages to print something more meaningful. > > Cc: Mathieu Poirier <mathieu.poir...@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm

[PATCH 1/2] perf tools: making coresight PMU listable

Adding the required mechanic allowing 'perf list pmu' to discover coresight ETM/PTM tracers. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS| 1 + tools/perf/MANIFEST| 1 + tools/perf/arch/arm/util/Build | 2 ++ tools/perf/ar

Re: [PATCH] coresight: Handle build path error

On 1 June 2016 at 12:04, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: > On 06/05/16 15:43, Mathieu Poirier wrote: >> >> On 6 May 2016 at 08:35, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: >>> >>> Enabling a component via sysfs (echo 1 > e

Re: [PATCH] coresight: Remove erroneous dma_free_coherent in tmc_probe

e the "devm_free_coherent" in tmc_probe > when the probe fails due to other reasons. This patch gets rid of the > incorrect dma_free_coherent() call. Also consolidates the error return > paths. > > Fixes: commit de5461970b3e9e194 ("coresight: tmc: allocating memory when >

Re: [PATCH 4/5] coresight: Add better messages for coresight_timeout

On 1 June 2016 at 03:34, Suzuki K Poulose wrote: > On 31/05/16 18:58, Joe Perches wrote: >> >> On Tue, 2016-05-31 at 12:57 +0100, Suzuki K Poulose wrote: >>> >>> When we encounter a timeout waiting for a status change via >>> coresight_timeout, the caller always print the

[PATCH V2] coresight: document binding acronyms

It can be hard for people not familiar with the CoreSight IP blocks to make sense of the acronyms found in the current bindings. As such this patch expands each acronym in the hope of providing a better description of the IP block they represent. Signed-off-by: Mathieu Poirier <mathieu.p

Re: [PATCH V2] coresight-stm: support mmapping channel regions with mmio_addr

On 20 June 2016 at 20:24, Chunyan Zhang wrote: > CoreSight STM device allows direct mapping of the channel regions to > userspace for zero-copy writing. To support this ability, the STM > framework has provided a hook 'mmio_addr', this patch just implemented > this hook

[PATCH] coresight: add PM runtime calls to coresight_simple_func()

It is mandatory to enable a coresight block's power domain before trying to access management registers. Otherwise the transaction simply stalls, leading to a system hang. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/coresight-priv.h | 3

[PATCH RESEND 0/2] perf tools: coresight PMU recording capabilities

x0, x1 7fab583308: 54c1b.ne7fab583300 <free@plt+0x37c0> ... ... Regards, Mathieu [1]. http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/404232.html [2]. https://github.com/Linaro/OpenCSD/ [3]. http://pastebin.com/u9tgdwjF [4]. http://past

[PATCH RESEND 1/2] perf tools: making coresight PMU listable

Adding the required mechanic allowing 'perf list pmu' to discover coresight ETM/PTM tracers. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS| 1 + tools/perf/MANIFEST| 1 + tools/perf/arch/arm/util/Build | 2 ++ tools/perf/ar

[PATCH RESEND 2/2] perf tools: adding coresight etm PMU record capabilities

Coresight ETMs are IP blocks used to perform HW assisted tracing on a CPU core. This patch introduce the required auxiliary API functions allowing the perf core to interact with a tracer. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- MAINTAINERS

Re: [PATCH v3 0/7] coresight: Miscellaneous fixes

On 21 June 2016 at 10:10, Suzuki K Poulose wrote: > This is a collection of cleanups and minor enhancements to the > coresight driver. Applies on v4.7-rc4 > > Changes since V2: > - Removed patches already queued as fixes for 4.7 > - Addressed comments on V2. > > Changes

Re: [PATCH] coresight: always use stashed trace id value in etm4_trace_id

ht_id_match is executed from enable_source_store. > > This patch simplifies etm4_trace_id by returning the stashed trace id > value similar to etm4_cpu_id. > > Cc: Mathieu Poirier <mathieu.poir...@linaro.org> > Signed-off-by: Sudeep Holla <sudeep.ho...@arm.com> > --- &

Re: [PATCH] coresight: always use stashed trace id value in etm4_trace_id

On 21 June 2016 at 11:32, Sudeep Holla <sudeep.ho...@arm.com> wrote: > > > On 21/06/16 18:05, Mathieu Poirier wrote: >> >> On 20 June 2016 at 08:25, Sudeep Holla <sudeep.ho...@arm.com> wrote: >>> >>> etm4_trace_id is not guaranteed to be

[PATCH] coresight: delay initialisation when children are missing

the problem by asking the driver core to try initialising the device at a later time when the children of a CoreSight node are missing. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- drivers/hwtracing/coresight/of_coresight.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH] coresight: document binding acronyms

It can be hard for people not familiar with the CoreSight IP blocks to make sense of the acronyms found in the current bindings. As such this patch expands each acronym in the hope of providing a better description of the IP block they represent. Signed-off-by: Mathieu Poirier <mathieu.p

Re: [PATCH] coresight-stm: support mmapping channel regions with mmio_addr

On 13 June 2016 at 20:16, Chunyan Zhang wrote: > CoreSight STM device allows direct mapping of the channel regions to > userspace for zero-copy writing. To support this ability, the STM > freamwork has provided a hook 'mmio_addr', this patch just implemented > this hook

Re: [PATCH] coresight: access conn->child_name only if it's initialised

_probe_device+0x94/0xa0 > device_add+0x344/0x580 > amba_device_try_add+0x194/0x238 > amba_deferred_retry_func+0x48/0xd0 > process_one_work+0x118/0x378 > worker_thread+0x48/0x498 > kthread+0xd0/0xe8 > ret_from_fork+0x10/0x40 > > This patch adds a check for non-NULL conn->child_na

Re: [PATCH] coresight: add PM runtime calls to coresight_simple_func()

On 23 June 2016 at 10:37, Sudeep Holla <sudeep.ho...@arm.com> wrote: > > > On 17/06/16 18:41, Mathieu Poirier wrote: >> >> It is mandatory to enable a coresight block's power domain before >> trying to access management registers. Otherwise the transaction >

[PATCH V2] coresight: add PM runtime calls to coresight_simple_func()

It is mandatory to enable a coresight block's power domain before trying to access management registers. Otherwise the transaction simply stalls, leading to a system hang. Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org> --- Change from V1: - Fix erroneous return point in the

Re: [PATCH v2 0/3] firmware: scpi: add device power domain support

6 files changed, 228 insertions(+) > create mode 100644 drivers/firmware/scpi_pm_domain.c > > -- > 2.7.4 > For the set: Tested-by: Mathieu Poirier <mathieu.poir...@linaro.org>

Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs

On 8 February 2016 at 06:26, Alexander Shishkin <alexander.shish...@linux.intel.com> wrote: > Mathieu Poirier <mathieu.poir...@linaro.org> writes: > >> On 5 February 2016 at 05:52, Alexander Shishkin >> <alexander.shish...@linux.intel.com> wrote: >>> Ch

Re: [PATCH v11 4/4] Watchdog: introduce ARM SBSA watchdog driver

; +} > + > +/* Disable watchdog if it is active during suspend */ > +static int __maybe_unused sbsa_gwdt_suspend(struct device *dev) > +{ > + struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); > + > + if (watchdog_active(>wdd)) > + sbsa_gwdt_stop(>wdd); > + > + return 0; > +} > + > +/* Enable watchdog and configure it if necessary */ > +static int __maybe_unused sbsa_gwdt_resume(struct device *dev) > +{ > + struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); > + > + if (watchdog_active(>wdd)) > + sbsa_gwdt_start(>wdd); > + > + return 0; > +} > + > +static const struct dev_pm_ops sbsa_gwdt_pm_ops = { > + SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume) > +}; > + > +static const struct of_device_id sbsa_gwdt_of_match[] = { > + { .compatible = "arm,sbsa-gwdt", }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match); > + > +static const struct platform_device_id sbsa_gwdt_pdev_match[] = { > + { .name = "sbsa-gwdt", }, > + {}, > +}; > +MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match); > + > +static struct platform_driver sbsa_gwdt_driver = { > + .driver = { > + .name = "sbsa-gwdt", > + .pm = _gwdt_pm_ops, > + .of_match_table = sbsa_gwdt_of_match, > + }, > + .probe = sbsa_gwdt_probe, > + .remove = sbsa_gwdt_remove, > + .shutdown = sbsa_gwdt_shutdown, > + .id_table = sbsa_gwdt_pdev_match, > +}; > + > +module_platform_driver(sbsa_gwdt_driver); > + > +MODULE_DESCRIPTION("SBSA Generic Watchdog Driver"); > +MODULE_AUTHOR("Fu Wei <fu@linaro.org>"); > +MODULE_AUTHOR("Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>"); > +MODULE_AUTHOR("Al Stone <al.st...@linaro.org>"); > +MODULE_AUTHOR("Timur Tabi <ti...@codeaurora.org>"); > +MODULE_LICENSE("GPL v2"); > -- > 2.5.0 > For this patch: Reviewed-by: Mathieu Poirier <mathieu.poir...@linaro.org>

Re: [PATCH v5 1/3] mailbox: Add support for APM X-Gene platform mailbox driver

On 9 February 2016 at 20:46, Duc Dang <dhd...@apm.com> wrote: > On Tue, Feb 9, 2016 at 8:40 AM, Mathieu Poirier > <mathieu.poir...@linaro.org> wrote: >> On 8 February 2016 at 15:04, Duc Dang <dhd...@apm.com> wrote: >>> X-Gene mailbox controller provides 8

Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs

On 8 February 2016 at 10:44, Al Grant wrote: >> Mike did write "master IDs are hardwired to individual cores and core >> security >> states", which make assignment for one platform very static. >> On the flip side those will change from one system to another. > > It depends on

Re: [PATCH v5 1/3] mailbox: Add support for APM X-Gene platform mailbox driver

On 8 February 2016 at 15:04, Duc Dang wrote: > X-Gene mailbox controller provides 8 mailbox channels, with > each channel has a dedicated interrupt line. > > Signed-off-by: Feng Kan > Signed-off-by: Duc Dang > --- > Changes since v4: > -

Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs

On 5 February 2016 at 05:52, Alexander Shishkin <alexander.shish...@linux.intel.com> wrote: > Chunyan Zhang <zhang.chun...@linaro.org> writes: > >> From: Mathieu Poirier <mathieu.poir...@linaro.org> >> >> Some architecture like ARM assign masterIDs st

Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half timeout panic support

On 3 February 2016 at 10:18, wrote: > From: Fu Wei > > This patch registers the WS0 interrupt routine to trigger panic, > when the watchdog reachs the first stage (the half timeout). > This function can help administrator to backup the system context > info

Re: [PATCH V3 1/6] stm class: Add ioctl get_options interface

On 12 February 2016 at 08:18, Alexander Shishkin wrote: > Chunyan Zhang writes: > >> There is already an interface of set_options, but no get_options yet. >> Before setting any options, one would may want to see the current >> status

Re: [PATCH V3 6/6] coresight-stm: adding driver for CoreSight STM component

On 12 February 2016 at 07:55, Michael Williams <michael.willi...@arm.com> wrote: > Mathieu Poirier [mailto:mathieu.poir...@linaro.org] wrote: >> On 6 February 2016 at 04:04, Chunyan Zhang <zhang.chun...@linaro.org> wrote: >>> From: Pratik Patel <prat...@codeaur

Re: [PATCH V3 6/6] coresight-stm: adding driver for CoreSight STM component

On 12 February 2016 at 08:28, Alexander Shishkin wrote: > Chunyan Zhang writes: > >> +static long stm_generic_set_options(struct stm_data *stm_data, >> + unsigned int master, >> +

Re: [PATCH v10 4/5] Watchdog: introduce ARM SBSA watchdog driver

On 3 February 2016 at 10:18, wrote: > From: Fu Wei > > According to Server Base System Architecture (SBSA) specification, > the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0) > is for alerting the system by interrupt, the second one

Re: [PATCH V2 3/6] stm class: provision for statically assigned masterIDs

On 12 February 2016 at 09:27, Alexander Shishkin <alexander.shish...@linux.intel.com> wrote: > Mathieu Poirier <mathieu.poir...@linaro.org> writes: > >> On 8 February 2016 at 06:26, Alexander Shishkin >> <alexander.shish...@linux.intel.com> wrote: >&g

Re: [PATCH V8 23/23] perf tools: adding coresight etm PMU record capabilities

On 29 January 2016 at 03:34, Adrian Hunter <adrian.hun...@intel.com> wrote: > On 25/01/16 23:10, Arnaldo Carvalho de Melo wrote: >> Em Mon, Jan 25, 2016 at 01:51:18PM -0700, Mathieu Poirier escreveu: >>> On 14 January 2016 at 14:46, Mathieu Poirier <mathieu.poi

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