[PATCH v5 78/80] dt-bindings: display: vc4: Document BCM2711 VC5

The BCM2711 comes with a new VideoCore. Add a compatible for it. Reviewed-by: Rob Herring Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 1

[PATCH v5 76/80] drm/vc4: hdmi: Support the BCM2711 HDMI controllers

Now that the driver is ready for it, let's bring in the HDMI controllers variants for the BCM2711. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 284

[PATCH v5 80/80] ARM: dts: bcm2711: Enable the display pipeline

Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 48 +++- arch/arm/boot/dts/bcm2711.dtsi| 122 ++- 2 files changed, 169 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi

[PATCH v5 77/80] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings

The HDMI controllers found in the BCM2711 SoC need some adjustments to the bindings, especially since the registers have been shuffled around in more register ranges. Reviewed-by: Rob Herring Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard

[PATCH v5 75/80] drm/vc4: hdmi: Add pixel BVB clock control

From: Hoegeun Kwon The BCM2711 has another clock that needs to be ramped up depending on the pixel rate: the pixel BVB clock. Add the code to adjust that clock when changing the mode. Signed-off-by: Hoegeun Kwon [Maxime: Changed the commit log, used clk_set_min_rate] Signed-off-by: Maxime

[PATCH v5 74/80] drm/vc4: hdmi: Switch to blank pixels when disabled

Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 9 + drivers/gpu/drm/vc4/vc4_regs.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4

[PATCH v5 72/80] drm/vc4: hdmi: Implement finer-grained hooks

-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 39 +++ 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index c9eae5352b9a..128d33c8c2c3 100644

[PATCH v5 60/80] drm/vc4: hdmi: Add CEC support flag

Similarly to the audio support, CEC support is not there yet for the BCM2711, so let's skip entirely the CEC initialization through a variant flag. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers

[PATCH v5 61/80] drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define

The CEC_CLOCK_DIV define is not used anywhere in the driver, let's remove it. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 1 - 1 file changed, 1 deletion(-) diff --git

[PATCH v5 71/80] drm/vc4: hdmi: Always recenter the HDMI FIFO

-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 46 +++ 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 3c7862a1dda8..c9eae5352b9a 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c

[PATCH v5 62/80] drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid

The mode_valid hook on the encoder uses a pointer to a drm_encoder called crtc, which is pretty confusing. Let's rename it to encoder to make it clear what it is. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard

[PATCH v5 58/80] drm/vc4: hdmi: Deal with multiple debugfs files

. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 5 - drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm

[PATCH v5 73/80] drm/vc4: hdmi: Do the VID_CTL configuration at once

The VID_CTL setup is done in several places in the driver even though it's not really required. Let's simplify it a bit to do the configuration in one go. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard

[PATCH v5 59/80] drm/vc4: hdmi: Move CEC init to its own function

-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 108 +- 1 file changed, 67 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 4d0b44a2ac61..bf537c6d413f 100644

[PATCH v5 55/80] drm/vc4: hdmi: Add a CSC setup callback

Similarly to the previous patches, the CSC setup is slightly different in the BCM2711 than in the previous generations. Let's add a callback for it. Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 70

[PATCH v5 65/80] drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers

as a fallback. Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers

[PATCH v5 53/80] drm/vc4: hdmi: Add PHY init and disable function

The HDMI PHY in the BCM2711 HDMI controller is significantly more complicated to setup than in the older BCM283x SoCs. Let's add hooks to enable and disable the PHY. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime

[PATCH v5 52/80] drm/vc4: hdmi: Add reset callback

The BCM2711 and BCM283x HDMI controllers use a slightly different reset sequence, so let's add a callback to reset the controller. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4

[PATCH v5 50/80] drm/vc4: hdmi: Introduce resource init and variant

-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 61 +++ drivers/gpu/drm/vc4/vc4_hdmi.h | 10 ++- 2 files changed, 51 insertions(+), 20 deletions

[PATCH v5 69/80] drm/vc4: hdmi: Deal with multiple ALSA cards

. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 3 ++- drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4

[PATCH v5 70/80] drm/vc4: hdmi: Remove register dumps in enable

. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 17 - 1 file changed, 17 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c

[PATCH v5 66/80] drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming

-by: Stefan Wahren Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 12 drivers/gpu/drm/vc4/vc4_hdmi.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index

[PATCH v5 67/80] drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default.

Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 43e59466b1d8..d8137b838326 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu

[PATCH v5 42/80] drm/vc4: hdmi: Rename hdmi to vc4_hdmi

The driver isn't consistent with the name given to the vc4_hdmi structure pointer in its functions. Make sure to use a consistent name. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4

[PATCH v5 37/80] drm/vc4: crtc: Add BCM2711 pixelvalves

The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add support for them. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 95

[PATCH v5 41/80] drm/vc4: hdmi: Remove DDC argument to connector_init

Now that we are passing the vc4_hdmi structure to the connector init function, we can simply use the pointer in that structure instead of having the pointer as an argument. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime

[PATCH v5 35/80] drm/vc4: drv: Disable the CRTC at boot time

-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 25 + drivers/gpu/drm/vc4/vc4_drv.c | 4 drivers/gpu/drm/vc4/vc4_drv.h | 1 + 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 4156c5f66877

[PATCH v5 46/80] drm/vc4: hdmi: Pass vc4_hdmi to CEC code

Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 24 +--- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index a2053da4e443

[PATCH v5 40/80] drm/vc4: hdmi: rework connectors and encoders

by vc4_hdmi and update the code accordingly. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 87 --- drivers/gpu/drm/vc4/vc4_hdmi.h | 64

[PATCH v5 39/80] drm/vc4: hdmi: Move structure to header

We will need to share the vc4_hdmi and related structures with multiple files, so let's create a header for it. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 76

[PATCH v5 12/80] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable

-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index cdeaa0cd981f

[PATCH v5 15/80] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data

Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that to our vc4_crtc_data structure to be able to compute the fill level properly later on. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard

[PATCH v5 33/80] drm/vc4: hvs: Introduce a function to get the assigned FIFO

-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_drv.h | 1 +- drivers/gpu/drm/vc4/vc4_hvs.c | 54 - 2 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers

[PATCH v5 34/80] drm/vc4: crtc: Move the CRTC disable out

We'll need to reuse the part that disables the HVS and PixelValve during boot too, so let's create a separate function. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 34

[PATCH v5 32/80] drm/vc4: hvs: Make the stop_channel function public

-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_drv.h | 1 + drivers/gpu/drm/vc4/vc4_hvs.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b

[PATCH v5 24/80] drm/vc4: hvs: Make sure our channel is reset

In order to clear our intermediate FIFOs that might end up with a stale pixel, let's make sure our FIFO channel is reset every time our channel is setup. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard

[PATCH v5 14/80] drm/vc4: crtc: Assign output to channel automatically

-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 12 +- drivers/gpu/drm/vc4/vc4_drv.h | 7 +- drivers/gpu/drm/vc4/vc4_hvs.c | 28 ++ drivers/gpu/drm/vc4/vc4_kms.c | 168

[PATCH v5 11/80] drm/vc4: crtc: Use local chan variable

The vc4_crtc_handle_page_flip already has a local variable holding the value of vc4_crtc->channel, so let's use it instead. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crt

[PATCH v5 09/80] drm/vc4: crtc: Move the cob allocation outside of bind

. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 35 +-- drivers/gpu/drm/vc4/vc4_drv.h | 2 +-- 2 files changed, 17 insertions(+), 20 deletions

[PATCH v5 02/80] drm/vc4: Add support for the BCM2711 HVS5

Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_drv.h | 4 +- drivers/gpu/drm/vc4/vc4_hvs.c | 34 -- drivers/gpu/drm/vc4/vc4_plane.c | 194 - drivers/gpu/drm/vc4

[PATCH v5 03/80] drm/vc4: hvs: Boost the core clock during modeset

In order to prevent timeouts and stalls in the pipeline, the core clock needs to be maxed at 500MHz during a modeset on the BCM2711. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4

[PATCH v5 06/80] drm/vc4: plane: Create more planes

. Using 16 seems like a good tradeoff between staying under 32 and yet providing enough planes. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_plane.c | 2 +- 1 file changed, 1 insertion

[PATCH v5 04/80] drm/vc4: plane: Change LBM alignment constraint on LBM

From: Dave Stevenson The HVS5 needs an alignment of 64bytes for its LBM memory, so let's reflect it. Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_plane.c | 4 +++- 1 file

Re: [linux-sunxi] [PATCH 05/16] ASoc: sun4i-i2s: Add 20 and 24 bit support

On Wed, Sep 02, 2020 at 09:22:33PM -0500, Samuel Holland wrote: > On 9/2/20 1:10 PM, Jernej Škrabec wrote: > > Hi Samuel! > > > > Dne petek, 10. julij 2020 ob 07:44:51 CEST je Samuel Holland napisal(a): > >> On 7/4/20 6:38 AM, Clément Péron wrote: > >>> From: Marcus Cooper > >>> > >>> Extend the

Re: [PATCH RESEND 1/2] clk: Implement protected-clocks for all OF clock providers

ond call in > of_clk_init() may be unnecessary, but verifying that would require > auditing all users of CLK_OF_DECLARE to ensure they called one of > the of_clk_add{,_hw}_provider functions. > > Signed-off-by: Samuel Holland Reviewed-by: Maxime Ripard Thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH v2 1/4] clk: bcm: rpi: Add register to control pixel bvb clk

Hi Stephen, Mike, On Tue, Sep 01, 2020 at 01:07:56PM +0900, Hoegeun Kwon wrote: > To use QHD or higher, we need to modify the pixel_bvb_clk value. So > add register to control this clock. > > Signed-off-by: Hoegeun Kwon Reviewed-by: Maxime Ripard Can you merge this patch through

Re: [PATCH v4 13/78] drm/vc4: kms: Convert to for_each_new_crtc_state

Hi! On Wed, Jul 29, 2020 at 04:02:06PM +0100, Dave Stevenson wrote: > Hi Maxime > > On Wed, 8 Jul 2020 at 18:42, Maxime Ripard wrote: > > > > The vc4 atomic commit loop has an handrolled loop that is basically > > identical to for_each_new_crtc_state, let'

Re: [PATCH v4 29/78] drm/vc4: crtc: Add a delay after disabling the PixelValve output

On Tue, Sep 01, 2020 at 06:31:07PM +0200, Stefan Wahren wrote: > Hi Maxime, > > Am 01.09.20 um 11:58 schrieb Maxime Ripard: > > Hi Stefan > > > > On Tue, Aug 25, 2020 at 11:30:58PM +0200, Stefan Wahren wrote: > >> Am 25.08.20 um 17:06 schrieb Maxime Ripard:

Re: [PATCH v4 00/78] drm/vc4: Support BCM2711 Display Pipeline

On Wed, Sep 02, 2020 at 03:32:20PM +0200, Maxime Ripard wrote: > Hi Hoegeun > > On Fri, Aug 21, 2020 at 04:18:34PM +0900, Hoegeun Kwon wrote: > > Hi Maxime, > > > > Thank you for your version 4 patch. > > I tested all 78 patches based on the next-20200708. > &

Re: [PATCH] dt-bindings: crypto: Specify that allwinner,sun8i-a33-crypto needs reset

On Wed, Sep 02, 2020 at 11:17:16AM +0200, Corentin Labbe wrote: > When adding allwinner,sun8i-a33-crypto, I forgot to add that it needs reset. > Furthermore, there are no need to use items to list only one compatible > in compatible list. > > Fixes: f81547ba7a98 ("dt-bindings: crypto: add new

Re: [PATCH v4 03/78] drm/vc4: hvs: Boost the core clock during modeset

Hi, On Tue, Sep 01, 2020 at 08:21:36PM +0900, Chanwoo Choi wrote: > Hi Maxime, > > On 7/9/20 2:41 AM, Maxime Ripard wrote: > > In order to prevent timeouts and stalls in the pipeline, the core clock > > needs to be maxed at 500MHz during a modeset on the BCM2711. >

Re: [PATCH v4 00/78] drm/vc4: Support BCM2711 Display Pipeline

Hi Hoegeun On Fri, Aug 21, 2020 at 04:18:34PM +0900, Hoegeun Kwon wrote: > Hi Maxime, > > Thank you for your version 4 patch. > I tested all 78 patches based on the next-20200708. > > > Dual HDMI opearation does not work normally. > flip_done timed out occurs and doesn't work. > Could you

Re: [PATCH v2 1/3] dt-bindings: crypto: add new compatible for V3s

On Tue, Sep 01, 2020 at 12:57:19PM +0200, Corentin Labbe wrote: > On Tue, Sep 01, 2020 at 11:32:49AM +0200, Maxime Ripard wrote: > > On Mon, Aug 31, 2020 at 09:30:59AM +0200, Martin Cerveny wrote: > > > Like A33 "sun4i-ss" has a difference, it give SHA1 digest >

Re: [PATCH v4 77/78] drm/vc4: drv: Support BCM2711

Hi Dave, On Tue, Jul 28, 2020 at 04:30:16PM +0100, Dave Stevenson wrote: > > @@ -681,10 +684,14 @@ int vc4_kms_load(struct drm_device *dev) > > struct vc4_load_tracker_state *load_state; > > int ret; > > > > - /* Start with the load tracker enabled. Can be disabled through

Re: [PATCH v4 29/78] drm/vc4: crtc: Add a delay after disabling the PixelValve output

Hi Stefan On Tue, Aug 25, 2020 at 11:30:58PM +0200, Stefan Wahren wrote: > Am 25.08.20 um 17:06 schrieb Maxime Ripard: > > Hi Stefan, > > > > On Wed, Jul 29, 2020 at 05:50:31PM +0200, Stefan Wahren wrote: > >> Am 29.07.20 um 16:42 schrieb Maxime Ripard: > >>

Re: [PATCH v4 75/78] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings

Hi, On Tue, Sep 01, 2020 at 01:45:07PM +0900, Chanwoo Choi wrote: > Hi Maxime, > > On 7/9/20 2:42 AM, Maxime Ripard wrote: > > The HDMI controllers found in the BCM2711 SoC need some adjustments to the > > bindings, especially since the registers have been shuffled around

Re: [PATCH v4 62/78] drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate

Hi Chanwoo, On Tue, Sep 01, 2020 at 01:36:17PM +0900, Chanwoo Choi wrote: > On 7/9/20 2:42 AM, Maxime Ripard wrote: > > The HSM clock needs to be setup at around 101% of the pixel rate. This > > was done previously by setting the clock rate to 163.7MHz at probe time and

Re: [PATCH v5 00/16] Allwinner A100 Initial support

Hi Linus On Fri, Aug 28, 2020 at 12:02:29PM +0200, Linus Walleij wrote: > On Fri, Jul 24, 2020 at 8:53 AM Frank Lee wrote: > > > This patch set adds initial support for allwinner a100 soc, > > which is a 64-bit tablet chip. > > Shall I commit the pinctrl patches (if Maxime ACKed) separately >

Re: [PATCH v2 2/3] ARM: dts: sun8i: v3s: Enable crypto engine

On Mon, Aug 31, 2020 at 09:31:00AM +0200, Martin Cerveny wrote: > V3s contains crypto engine that is compatible with "sun4i-ss". > > Tested-by: Martin Cerveny > Signed-off-by: Martin Cerveny > --- > arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++ > 1 file changed, 10 insertions(+) > > diff

Re: [PATCH v2 1/3] dt-bindings: crypto: add new compatible for V3s

On Mon, Aug 31, 2020 at 09:30:59AM +0200, Martin Cerveny wrote: > Like A33 "sun4i-ss" has a difference, it give SHA1 digest > directly in BE. So add new compatible. > > Tested-by: Martin Cerveny The Tested-by tag is for the other developpers. You're very much expected to have tested your patch

Re: [PATCH v2 0/4] Support of MIPI CSI-2 for A83T

Hi Paul, On Fri, Aug 28, 2020 at 04:12:03PM +0200, Paul Kocialkowski wrote: > Hi everyone, > > On Fri 28 Aug 20, 15:17, Kévin L'hôpital wrote: > > This series adds the support for the MIPI CSI-2 controller for the A83T SoC. > > The CSI controller is the same as the V3s SoC that's why I put the

Re: [PATCH v2] drm/sun4i: Fix dsi dcs long write function

On Fri, Aug 28, 2020 at 02:50:32PM +0200, Ondrej Jirman wrote: > It's writing too much data. regmap_bulk_write expects number of > register sized chunks to write, not a byte sized length of the > bounce buffer. Bounce buffer needs to be padded too, so that > regmap_bulk_write will not read past

Re: [PATCH] dt-bindings: gpu: arm,mali-utgard: Correct Maxime's email

On Sun, Aug 30, 2020 at 10:51:22AM +0200, Krzysztof Kozlowski wrote: > Update the address of Maxime Ripard as one in @free-electrons.com does > not work. > > Cc: Maxime Ripard > Signed-off-by: Krzysztof Kozlowski Acked-by: Maxime Ripard Thanks! Maxime signature.asc D

Re: [PATCH 3/3] drm/vc4: hdmi: Add pixel bvb clock control

Hi, On Fri, Aug 28, 2020 at 02:45:49PM +0200, Stefan Wahren wrote: > Am 28.08.20 um 08:30 schrieb Hoegeun Kwon: > > On 8/27/20 6:49 PM, Stefan Wahren wrote: > >> Am 27.08.20 um 06:35 schrieb Hoegeun Kwon: > >>> Hi Stefan, > >>> > >>> Thank you for your review. > >>> > >>> > >>> On 8/26/20 7:04

Re: [PATCH 0/7] Allwinner A64 digital audio codec fixes

On Sat, Jul 25, 2020 at 08:25:50PM -0500, Samuel Holland wrote: > This series fixes a couple of issues with the digital audio codec in the > Allwinner A64 SoC: > 1) Left/right channels were swapped when playing/recording audio > 2) DAPM topology was wrong, breaking some kcontrols > > This is

Re: [PATCH 0/7] Allwinner A64 digital audio codec fixes

On Tue, Aug 25, 2020 at 04:36:52PM +0100, Mark Brown wrote: > On Mon, Aug 24, 2020 at 04:03:34PM +0200, Maxime Ripard wrote: > > > > [5/7] ARM: dts: sun8i: a33: Update codec widget names > > > (no commit info) > > > [6/7] arm64: dts: allwinne

Re: [PATCH 0/3] drm/vc4: Support HDMI QHD or higher output

Hi! On Fri, Aug 21, 2020 at 04:10:42PM +0900, Hoegeun Kwon wrote: > Hi everyone, > > There is a problem that the output does not work at a resolution > exceeding FHD. To solve this, we need to adjust the bvb clock at a > resolution exceeding FHD. > > Rebased on top of next-20200708 and [1]. >

Re: [PATCH 3/3] drm/vc4: hdmi: Add pixel bvb clock control

Hi Stefan, On Thu, Aug 27, 2020 at 11:49:34AM +0200, Stefan Wahren wrote: > Am 27.08.20 um 06:35 schrieb Hoegeun Kwon: > > Hi Stefan, > > > > Thank you for your review. > > > > > > On 8/26/20 7:04 PM, Stefan Wahren wrote: > >> Hi Hoeguen, > >> > >> Am 21.08.20 um 09:10 schrieb Hoegeun Kwon: > >>>

Re: [PATCH V2] drm/sun4i: add missing put_device() call in sun8i_r40_tcon_tv_set_mux()

On Wed, Aug 26, 2020 at 09:08:26AM +0800, Yu Kuai wrote: > If sun8i_r40_tcon_tv_set_mux() succeed, sun8i_r40_tcon_tv_set_mux() > doesn't have a corresponding put_device(). Thus add put_device() > to fix the exception handling for this function implementation. > > Fixes: 0305189afb32 ("drm/sun4i:

Re: [PATCH 5/7] media: sunxi: sun6i-csi: Add support of MIPI CSI-2 for A83T

On Wed, Aug 26, 2020 at 11:17:28AM +0200, Kévin L'hôpital wrote: > > > + mdelay(10); > > > > Why do you need an mdelay here? > > yes a msleep could be more correct here. My question was more about whether/why you need one in the first place, not necessarily how you would implement that delay.

Re: [PATCH 7/7] [NOT FOR MERGE] ARM: dts: sun8i: a83t: bananapi-m3: Enable OV8865 camera

Hi, On Wed, Aug 26, 2020 at 10:58:34AM +0200, Kévin L'hôpital wrote: > > > + { > > > + assigned-clocks = < CLK_CSI_MCLK>; > > > + assigned-clock-parents = <>; > > > + assigned-clock-rates = <2400>; > > > +}; > > > > Why do you need to use assigned-clocks here? > > I could do it in the

Re: [PATCH 0/5] ARM: dts: sun8i: r40: Enable video decoder

On Tue, Aug 25, 2020 at 07:35:18PM +0200, Jernej Skrabec wrote: > Allwinner R40 SoC contains video engine very similar to that in A33. > > First two patches add system controller nodes and the rest of them > add support for Cedrus VPU. > > Please take a look. Applied all 5 patches, thanks

Re: [PATCH 0/3] ARM: dts: sun8i: r40: Enable IR on BananaPi M2U

On Tue, Aug 25, 2020 at 07:13:55PM +0200, Jernej Skrabec wrote: > This series first adds nodes to R40 DTSI and then enable IR receiver > for BananaPi M2 Ultra board. Applied all three, thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH 0/2] ARM: dts: sun8i: r40: Enable DMA

On Tue, Aug 25, 2020 at 12:00:28PM +0200, Jernej Skrabec wrote: > Allwinner R40 contains DMA engine similar to that in A64. > > Following two patches enable it so DMA users can be added later. > > Please take a look. Applied both, thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH v4 29/78] drm/vc4: crtc: Add a delay after disabling the PixelValve output

Hi Stefan, On Wed, Jul 29, 2020 at 05:50:31PM +0200, Stefan Wahren wrote: > Am 29.07.20 um 16:42 schrieb Maxime Ripard: > > Hi, > > > > On Wed, Jul 29, 2020 at 03:09:21PM +0100, Dave Stevenson wrote: > >> On Wed, 8 Jul 2020 at 18:43, Maxime Ripard wrote: > >

Re: [PATCH] clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL

On Tue, Aug 25, 2020 at 03:10:49PM +0200, Jernej Skrabec wrote: > Audio cores need specific clock rates which can't be simply obtained by > adjusting integer multipliers and dividers. HW for such cases supports > delta-sigma modulation which enables fractional multipliers. > > Port H3 delta-sigma

Re: [PATCH 7/7] [NOT FOR MERGE] ARM: dts: sun8i: a83t: bananapi-m3: Enable OV8865 camera

Hi, On Fri, Aug 21, 2020 at 04:59:35PM +0200, Kévin L'hôpital wrote: > The Bananapi M3 supports a camera module which includes an > OV8865 sensor connected via the parallel CSI interface and > an OV8865 sensor connected via MIPI CSI-2. > > The I2C2 bus is shared by the two sensors as well as

Re: [PATCH 5/7] media: sunxi: sun6i-csi: Add support of MIPI CSI-2 for A83T

Hi, On Fri, Aug 21, 2020 at 04:59:33PM +0200, Kévin L'hôpital wrote: > This patch add the support only for the Allwinner A83T MIPI CSI2 > > Currently, the driver is not supported the other Allwinner V3's MIPI CSI2 > > It has been tested with the ov8865 image sensor. > > Signed-off-by: Kévin

Re: [PATCH] ARM: dts: sun4i: Enable HDMI support on the Mele A1000

On Fri, Aug 21, 2020 at 01:18:33PM -0400, Stefan Monnier wrote: > Enable the display pipeline and HDMI output. > > Signed-off-by: Stefan Monnier Applied, thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH 0/2] ARM: dts: sun8i: r40: Enable mali400 GPU

On Mon, Aug 24, 2020 at 05:04:32PM +0200, Jernej Skrabec wrote: > Following two patches enable Mali400 GPU on Allwinner R40 SoC. At this > point I didn't add table for frequency switching because it would > require far more testing and defaults work stable and reasonably well. > > Please take a

Re: [PATCH v5 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller

On Fri, Jul 24, 2020 at 03:05:49PM +0800, Frank Lee wrote: > From: Yangtao Li > > This commit introduces support for the pin controller on A100. > > Signed-off-by: Yangtao Li Acked-by: Maxime Ripard Thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH] arm64: dts: allwinner: h5: remove Mali GPU PMU module

On Sat, Aug 22, 2020 at 02:27:55PM +0800, Qiang Yu wrote: > H5's Mali GPU PMU is not present or working corretly although > H5 datasheet record its interrupt vector. > > Adding this module will miss lead lima driver try to shutdown > it and get waiting timeout. This problem is not exposed before

Re: [PATCH v2 13/14] [DO NOT MERGE] arm64: dts: allwinner: h6: Add GPU OPP table

Hi Clement, On Mon, Aug 03, 2020 at 09:54:05AM +0200, Clément Péron wrote: > Hi Maxime and All, > > On Sat, 4 Jul 2020 at 16:56, Clément Péron wrote: > > > > Hi Maxime, > > > > On Sat, 4 Jul 2020 at 14:13, Maxime Ripard wrote: > > > > > >

Re: [PATCH 0/7] Allwinner A64 digital audio codec fixes

Hi Mark, On Tue, Aug 18, 2020 at 05:54:50PM +0100, Mark Brown wrote: > On Sat, 25 Jul 2020 20:25:50 -0500, Samuel Holland wrote: > > This series fixes a couple of issues with the digital audio codec in the > > Allwinner A64 SoC: > > 1) Left/right channels were swapped when playing/recording

Re: [PATCH] arm64: dts: allwinner: replace numerical constant with CCU_CLKX

On Mon, Aug 03, 2020 at 05:30:22PM +0300, Alexander Kochetkov wrote: > From: Alexander Kochetkov > > Signed-off-by: Alexander Kochetkov Applied, thanks Maxime signature.asc Description: PGP signature

Re: [PATCH 0/7] Support of MIPI CSI-2 for A83T and OV8865 camera

Hi, On Fri, Aug 21, 2020 at 04:59:28PM +0200, Kévin L'hôpital wrote: > > Kévin L'hôpital (7): > media: sun6i-csi: Fix the bpp for 10-bit bayer formats > dt-bindings: media: i2c: Add documentation for ov8865 > media: i2c: Add support for the OV8865 image sensor > media: sunxi: sun6i-csi:

Re: [PATCH 1/7] media: sun6i-csi: Fix the bpp for 10-bit bayer formats

On Fri, Aug 21, 2020 at 04:59:29PM +0200, Kévin L'hôpital wrote: > 10-bit bayer formats are aligned to 16 bits in memory, so this is what > needs to be used as bpp for calculating the size of the buffers to > allocate. > > Signed-off-by: Kévin L'hôpital Generally speaking, you should also

Re: arm: dts: allwinner: a20: Add Drejo DS167 initial support

Hi, On Sun, Aug 02, 2020 at 11:29:24PM +0300, stul...@gmail.com wrote: > From: Sertac TULLUK > > Drejo DS167 is an Allwinner A20 based IoT device, which support > > - Allwinner A20 Cortex-A7 > - Mali-400MP2 GPU > - AXP209 PMIC > - 1GB DDR3 RAM > - 8GB eMMC > - 10/100M Ethernet > - SATA > -

Re: [PATCH] arm64: dts: allwinner: Mark timer as stopped in suspend

Hi! On Sat, Aug 08, 2020 at 09:18:22PM -0500, Samuel Holland wrote: > When possible, system firmware on 64-bit Allwinner platforms disables > OSC24M during system suspend. Since this oscillator is the clock source > for the ARM architectural timer, this causes the timer to stop counting. >

Re: [PATCH] drm/sun4i: Constify static structs

Hi, On Tue, Aug 04, 2020 at 11:53:37PM +0200, Rikard Falkeborn wrote: > A number of static variables are not modified and can be made const to > allow the compiler to put them in read-only memory. > > Signed-off-by: Rikard Falkeborn Applied, thanks! Maxime signature.asc Description: PGP

Re: [PATCH v5 15/16] dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings

On Fri, Jul 24, 2020 at 03:20:12PM +0800, Frank Lee wrote: > From: Yangtao Li > > Document board compatible names for Allwinner A100 Perf1 Board. > > Signed-off-by: Yangtao Li > Reviewed-by: Rob Herring Applied, thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH v5 07/16] dt-bindings: thermal: sun8i: Add binding for A100's THS controller

On Fri, Jul 24, 2020 at 03:10:57PM +0800, Frank Lee wrote: > From: Yangtao Li > > Add a binding for A100's ths controller. > > Signed-off-by: Yangtao Li > Reviewed-by: Rob Herring Acked-by: Maxime Ripard Thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH v5 11/16] dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi

On Fri, Jul 24, 2020 at 03:14:48PM +0800, Frank Lee wrote: > From: Yangtao Li > > There is no one use "allwinner,sun9i-a80-sc-nmi". The A80 uses > "allwinner,sun9i-a80-nmi". > > Let's fix it. > > Signed-off-by: Yangtao Li > Acked-by: Rob Herring Applied, thanks! Maxime signature.asc

Re: [PATCH] drm/sun4i: add missing put_device() call in sun8i_r40_tcon_tv_set_mux()

Hi, On Tue, Aug 25, 2020 at 07:44:03PM +0800, Yu Kuai wrote: > If sun8i_r40_tcon_tv_set_mux() succeed, at_dma_xlate() doesn't have a > corresponding put_device(). Thus add put_device() to fix the exception > handling for this function implementation. > > Fixes: 0305189afb32 ("drm/sun4i: tcon:

Re: [PATCH v5 14/16] arm64: allwinner: A100: add the basical Allwinner A100 DTSI file

On Fri, Jul 24, 2020 at 03:18:24PM +0800, Frank Lee wrote: > From: Yangtao Li > > Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds > the basical DTSI file of it, including the clock, i2c, pins, sid, ths, > nmi, and UART support. > > Signed-off-by: Yangtao Li Applied,

Re: [PATCH v5 16/16] arm64: allwinner: A100: add support for Allwinner Perf1 board

On Fri, Jul 24, 2020 at 03:21:05PM +0800, Frank Lee wrote: > From: Yangtao Li > > A100 perf1 is an Allwinner A100-based SBC, with the following features: > > - 1GiB DDR3 DRAM > - AXP803 PMIC > - 2 USB 2.0 ports > - MicroSD slot and on-board eMMC module > - on-board Nand flash > - ··· > > Adds

Re: [PATCH v5 01/16] dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU

On Fri, Jul 24, 2020 at 02:56:08PM +0800, Frank Lee wrote: > From: Yangtao Li > > This patch adds binding to a100's ccu clock and r-ccu clock. > > Signed-off-by: Yangtao Li > Reviewed-by: Rob Herring Applied, thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH v5 02/16] clk: sunxi-ng: add support for the Allwinner A100 CCU

On Fri, Jul 24, 2020 at 02:58:43PM +0800, Frank Lee wrote: > From: Yangtao Li > > Add support for a100 in the sunxi-ng CCU framework. > > Signed-off-by: Yangtao Li Applied, thanks! Maxime signature.asc Description: PGP signature

Re: [PATCH v5 00/16] Allwinner A100 Initial support

On Mon, Aug 24, 2020 at 09:03:27AM +0100, Lee Jones wrote: > On Mon, 24 Aug 2020, Frank Lee wrote: > > > ping.. > > "Please don't send content free pings and please allow a reasonable > time for review. People get busy, go on holiday, attend conferences > and so on so unless there is some

Re: [PATCH v5 08/16] thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate

eration to read data > to avoid conversion error. > > Signed-off-by: Yangtao Li Acked-by: Maxime Ripard Maxime signature.asc Description: PGP signature

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