at91: fix clk_programmable_set_parent()
Maxime Ripard (2):
clk: sunxi: tcon-ch1: Do not return a negative error in get_parent
clk: sunxi: display: Add per-clock flags
Michael Turquette (1):
Merge tag 'sunxi-clk-fixes-for-4.7' of
https://git.kernel.org/.../mripard/
stuff, so it
would be good to get his ack. Please feel free to add:
Reviewed-by: Michael Turquette
Regards,
Mike
> ---
> include/linux/clk.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/linux/clk.h b/include/linux/clk.h
> index 0df4a51..834179f 1006
clk: sunxi-ng: Add N-K-M-P factor clock
clk: sunxi-ng: Add H3 clocks
clk: sunxi-ng: h3: Fix audio clock divider offset
clk: sunxi-ng: h3: Fix Kconfig symbol typo
ARM: dt: sun8i: switch the H3 to the new CCU driver
Michael Turquette (25):
Merge commit 'f17a0d
Quoting Kevin Hilman (2016-08-19 15:03:06)
> Neil Armstrong writes:
>
> > Add the AO clock controller node for the AmLogic GXBB SoC.
> >
> > Signed-off-by: Neil Armstrong
> > ---
>
> Applying this to the amlogic tree, but will need to wait a cycle due to
> include dependencies on the bindings,
Quoting Gabriel Fernandez (2016-08-22 09:06:20)
> Hi Mike,
>
> you forgot me ?
>
> Best Regards
>
> Gabriel
>
>
> On 07/11/2016 08:58 AM, Gabriel Fernandez wrote:
> >
> >
> > On 07/08/2016 06:08 PM, Michael Turquette wrote:
> >> Quot
Hi Jerome,
Quoting Jerome Brunet (2017-09-24 22:00:29)
> @@ -1778,6 +1867,50 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
> EXPORT_SYMBOL_GPL(clk_set_rate);
>
> /**
> + * clk_set_rate_exclusive - specify a new rate get exclusive control
> + * @clk: the clk whose rate is being chang
Hi Jérôme,
On Tue, Oct 31, 2017 at 5:29 PM, Jerome Brunet wrote:
> On Thu, 2017-10-26 at 07:26 +0200, Michael Turquette wrote:
>> Hi Jerome,
>>
>> Quoting Jerome Brunet (2017-09-24 22:00:29)
>> > @@ -1778,6 +1867,50 @@ int clk_set_rate(struct clk
Quoting Wei Xu (2017-10-13 10:57:02)
> Hi Leo,
>
> On 2017/10/7 13:18, Leo Yan wrote:
> > Hi Stephen, Wei,
> >
> > On Thu, Aug 31, 2017 at 06:33:01PM -0700, Stephen Boyd wrote:
> >> On 09/01, Leo Yan wrote:
> >>> This patch series adds support for coresight on Hi6220; the first patch
> >>> is to
Quoting Tomasz Figa (2015-08-12 02:00:17)
> 2015-08-12 17:58 GMT+09:00 Marek Szyprowski :
> > Commit d5e136a21b2028fb1f45143ea7112d5869bfc6c7 ("clk: samsung: Register
> > clk provider only after registering its all clocks", merged to v3.17-rc1)
> > modified a way that driver registers registers to
Quoting Boris Brezillon (2015-08-27 02:30:35)
> Hi Nicolas,
>
> On Fri, 31 Jul 2015 12:17:44 +0200
> Nicolas Ferre wrote:
>
> > This new clock driver set allows to have a fractional divided clock
> > that would generate a precise clock particularly suitable for
> > audio applications.
> >
> > T
Hi Doug,
Quoting Doug Anderson (2015-08-27 19:03:20)
> Kevin,
>
> On Thu, Aug 27, 2015 at 5:24 PM, Kevin Hilman wrote:
> >> That is not really workable: the attach and detach happen in
> >> probe/remove path; if you do not have driver for the device you will
> >> miss the clocks for it.
> >
> >
Quoting Doug Anderson (2015-08-28 14:08:52)
> Mike,
>
> On Fri, Aug 28, 2015 at 1:02 PM, Michael Turquette
> wrote:
> > Hi Doug,
> >
> > Quoting Doug Anderson (2015-08-27 19:03:20)
> >> Kevin,
> >>
> >> On Thu, Aug 27, 2015 at 5:24 PM,
s
ARM: sun7i: Add clock indices
ARM: sun8i: Add clock indices
ARM: sun9i: Wrap the clock-indices
clk: sunxi: Add a simple gates driver
Michael Turquette (2):
Merge branch 'v4.3-topic/clk-samsung' of
git://git.kernel.org/.../kgene/linux-samsung into clk-next
gt; registers.
>
> In this patch, the following wake up sources are enabled,
> - WKUP0 pin
> - WKUP1 pin to WKUP8 pin (shared with PIOBU0 to PIOBU7)
> - RTC alarm
>
> Signed-off-by: Wenyou Yang
For the changes to the clk header:
Acked-by: Michael Turquett
Quoting Jisheng Zhang (2015-10-11 22:46:35)
> Since we have added the necessary axi clk properties in dts, we can
> remove the "sdio" clk's CLK_IGNORE_UNUSED flag now.
>
> Signed-off-by: Jisheng Zhang
Applied to clk-next.
Regards,
Mike
> ---
> drivers/clk/berlin/bg2q.c | 2 +-
> 1 file change
Quoting Jisheng Zhang (2015-10-11 22:46:36)
> The axi clock properties already exists, so there's no need to set this
> flag for sdio0 and sdio1 clk any more.
>
> Signed-off-by: Jisheng Zhang
Applied to clk-next.
Regards,
Mike
> ---
> drivers/clk/berlin/bg2.c | 4 ++--
> 1 file changed, 2 ins
Quoting Krzysztof Kozlowski (2015-10-15 16:46:27)
> On 15.10.2015 19:31, Tomeu Vizoso wrote:
> > When the DISP1 power domain is powered off, there's two clocks that need
> > to be temporarily reparented to OSC, and back to their original parents
> > when the domain is powered on again.
> >
> > We
Cc'ing Geert.
Quoting Stephen Boyd (2015-10-15 16:19:38)
> If a clock provider has #clock-cells = 1 and we call
> of_clk_get_parent_name() on it we may end up returning the name
> of the provider node if the provider doesn't have a
> clock-output-names property. This doesn't make sense, especially
Quoting Grygorii Strashko (2015-10-20 13:59:19)
> Hi Mike, All,
>
> [not for merge]
>
> As we discussed I've prepared patch which introduces config option
> COMMON_CLK_USE_RAW_LOCKS which, once enabled, switches CCF to use raw locks
> for locking. This way it will be possible to call clk_enable(
Quoting Geert Uytterhoeven (2015-10-20 11:49:58)
> Hi Mike, Stephen,
>
> The following changes since commit 64291f7db5bd8150a74ad2036f1037e6a0428df2:
>
> Linux 4.2 (2015-08-30 11:34:09 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/g
Quoting Jisheng Zhang (2015-10-20 04:16:46)
> Since we have added the necessary two clks' properties in dts, we can
> remove the "sdio" clk's CLK_IGNORE_UNUSED flag now.
>
> Signed-off-by: Jisheng Zhang
Applied to clk-next.
Regards,
Mike
> ---
> drivers/clk/berlin/bg2q.c | 2 +-
> 1 file chan
Quoting Jisheng Zhang (2015-10-20 04:16:47)
> The clocks' properties have been already properly set, so there's no
> need to set this flag for sdio0 and sdio1 clk any more.
>
> Signed-off-by: Jisheng Zhang
Applied to clk-next.
Regards,
Mike
> ---
> drivers/clk/berlin/bg2.c | 4 ++--
> 1 file
Quoting Ray Jui (2015-10-19 15:27:19)
> From: Simran Rai
>
> This patch affects the clocks that use fractional ndivider in their
> PLL output frequency calculation. Instead of 2^20 divide factor, the
> clock's ndiv integer shift was used. Fixed the bug by replacing ndiv
> integer shift with 2^20
Quoting Stephen Boyd (2015-10-19 15:16:05)
> On 10/19/2015 02:55 PM, Ray Jui wrote:
> >
> >
> > On 15-10-19 02:49 PM, Stephen Boyd wrote:
> >> On 10/16, Ray Jui wrote:
> >>> From: Simran Rai
> >>>
> >>> This patch affects the clocks that use fractional ndivider in their
> >>> PLL output frequency
Quoting Michael Turquette (2015-10-21 02:30:39)
> Quoting Jisheng Zhang (2015-10-20 04:16:46)
> > Since we have added the necessary two clks' properties in dts, we can
> > remove the "sdio" clk's CLK_IGNORE_UNUSED flag now.
> >
> > Signed-off-by: J
Quoting Russell King - ARM Linux (2015-10-21 03:59:32)
> On Wed, Oct 21, 2015 at 11:50:07AM +0200, Geert Uytterhoeven wrote:
> > Hi Mike, Russell,
> >
> > On Tue, Oct 20, 2015 at 2:40 PM, Michael Turquette
> > wrote:
> > > Why not keep the reference to the s
Quoting Maxime Ripard (2015-10-22 01:36:47)
> Hi!
>
> On Wed, Oct 21, 2015 at 04:33:53PM -0700, Stephen Boyd wrote:
> > These APIs aren't used, so remove them. This can be reverted if
> > we get a user at some point.
> >
> > Cc: Maxime Ripard
> > Sug
Quoting Heiko Stübner (2015-10-11 03:43:27)
> Hi Sjoerd,
>
> Am Freitag, 9. Oktober 2015, 13:35:55 schrieb Sjoerd Simons:
> > On Thu, 2015-10-08 at 17:10 +0200, Heiko Stuebner wrote:
> > > Am Donnerstag, 8. Oktober 2015, 15:31:16 schrieb Sjoerd Simons:
> > > > The clock branches leading to sclk_sp
Quoting Shengjiu Wang (2015-10-10 03:15:06)
> Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
> one clock of SPDIF, which is missed before.
>
> We found an issue that imx can't enter low power mode with spdif
> if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
Quoting Viresh Kumar (2015-10-08 00:48:28)
> On 07-10-15, 21:12, Arnd Bergmann wrote:
> > I think it clearly makes sense to have a fixed length for each of these
> > members:
> >
> > either 32 bit is enough to represent all possible values, then
> > there is no need to make them 'long' on 64-bit ar
Hi Guenter,
Quoting Guenter Roeck (2015-10-20 06:30:03)
> On 10/20/2015 06:17 AM, Marc Titinger wrote:
> > On 20/10/2015 14:54, Guenter Roeck wrote:
> >> On 10/20/2015 01:20 AM, Marc Titinger wrote:
> >>> With the current implementation, the driver will prevent a readout at a
> >>> pace faster tha
Quoting Rafael J. Wysocki (2015-10-25 06:54:39)
> On Sun, Oct 25, 2015 at 12:06 AM, Mark Brown wrote:
> > On Sat, Oct 24, 2015 at 04:17:12PM +0200, Rafael J. Wysocki wrote:
> >
> >> Well, I'm not quite sure why exactly everyone is so focused on probing
> >> here.
> >
> > Probe deferral is really
> matters. Also, update the comment to be hopefully clearer about the
> purpose of the code.
>
> Fixes: 0a95e630b49a ("cpufreq: arm_big_little: check if the frequency is set
> correctly")
>
> Signed-off-by: Jon Medhurst
> Acked-by: Sudeep Holla
Reviewe
Excerpts from Jerome Brunet's message of February 14, 2018 5:43 am:
This changset is consist of various patches I have recently sent
for the clock framework. They are gathered here for your convinience.
The first two changes exports helpers of the generic clocks (divider and
mux). The goal is to
Excerpts from gabriel.fernan...@st.com's message of March 8, 2018 8:53 am:
From: Gabriel Fernandez
v2:
- Don't use MFD, use existing binding of STM32 RCC.
- Rework Peripheral and Kernel clocks
- cosmetic changes
This patch-set introduces clock driver for STM32MP157 based on Arm Cortex-A7
Bonjour Jerome,
Excerpts from Jerome Brunet's message of February 12, 2018 6:58 am:
This changeset is a rework of meson's clock controllers to use regmap
instead of directly using io memory. It based clk-meson next/drivers
and depends on few core clock patches, mainly to export generic clocks
he
Excerpts from Heiko Stübner's message of February 15, 2018 1:01 pm:
Am Mittwoch, 14. Februar 2018, 14:43:36 CET schrieb Jerome Brunet:
The orphan clocks reparents should migrate any existing count from the
orphan clock to its new acestor clocks, otherwise we may have
inconsistent counts in the t
NOTE for the default off divider, the recalc rate will still return 0 as
> there's still no proper preset rate. Enable such divider will give user
> a reminder error message.
>
> Cc: Stephen Boyd
> Cc: Michael Turquette
> Cc: Shawn Guo
> Signed-off-by: Dong Aishen
Quoting Jerome Brunet (2018-06-19 06:40:50)
> the mmci driver (drivers/mmc/host/mmci.c) does the following sequence:
> * clk_prepare_enable()
> * clk_set_rate()
>
> on SDCx_clk which is a children of SDCx_src. SDCx_src has
> CLK_SET_RATE_GATE so this sequence should not be allowed but this was not
Quoting Jerome Brunet (2018-06-19 06:40:51)
> CLK_SET_RATE_GATE should prevent any operation which may result in a rate
> change or glitch while the clock is prepared/enabled.
>
> IOW, the following sequence is not allowed anymore with CLK_SET_RATE_GATE:
> * clk_get()
> * clk_prepare_enable()
> *
Quoting Jerome Brunet (2018-06-19 07:41:41)
> Add the possibility to apply and query the clock signal duty cycle ratio.
>
> This is useful when the duty cycle of the clock signal depends on some
> other parameters controlled by the clock framework.
>
> For example, the duty cycle of a divider may
Quoting David Lechner (2018-05-25 11:11:45)
> From: Sekhar Nori
>
> PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
> be disabled. Mark it so to prevent unused clock disable
> infrastructure from disabling it.
>
> Signed-off-by: Sekhar Nori
> Reviewed-by: David Lechner
> ---
> driv
Hi Rob,
Quoting Rob Herring (2018-05-14 06:20:57)
> On Mon, May 14, 2018 at 6:38 AM, Bartosz Golaszewski wrote:
> > 2018-05-11 22:13 GMT+02:00 Rob Herring :
> >> On Fri, May 11, 2018 at 11:20 AM, Bartosz Golaszewski
> >> wrote:
> >>> This series is a follow-up to the RFC[1] posted a couple days
Hi David,
Quoting David Lechner (2018-05-25 11:11:47)
> This modifies the TI Davinci PLL clock driver to allow for the case
> when dev == NULL. On some (most) SoCs that use this driver, the PLL
> clock needs to be registered during early boot because it is used
> for clocksource/clkevent and there
Hi David,
Quoting David Lechner (2018-05-25 11:11:41)
> This is a resend of all of the outstanding DaVinci clock patches plus one new
> patch. All of the patches (except the new one) have been reviewed and tested
> by someone other than me.
>
> The new patch ("clk: davinci: Fix link errors when n
Hi Olof, Georgi,
Happy new year! :-)
Quoting Georgi Djakov (2018-12-08 21:15:35)
> Hi Olof,
>
> On 9.12.18 2:33, Olof Johansson wrote:
> > Hi Georgi,
> >
> > On Sat, Dec 8, 2018 at 9:02 AM Georgi Djakov
> > wrote:
> >>
> >> Modern SoCs have multiple processors and various dedicated cores (vid
Cousson
> > Cc: Kevin Hilman
> > Cc: Michael Turquette
> > Signed-off-by: Bartosz Golaszewski
>
> Excellent, patch applied for fixes. Welcome aboard! :D
Completely unnecessary:
Acked-by: Michael Turquette
;-)
Best regards,
Mike
>
> Yours,
> Linus Walleij
Quoting Christian Hewitt (2018-10-13 12:04:46)
> On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems
> with reboot; e.g. a ~60 second delay between issuing reboot and the
> board power cycling (and in some OS configurations reboot will fail
> and require manual power cycling).
>
>
Quoting Sergej Sawazki (2015-03-19 14:50:50)
> Hi Mike,
>
> I came across your "[PATCH v2 0/5] clk: dt: bindings for mux, divider &
> gate clocks" email from 16 Jun 2013. The DT bindings for simple clock
> multiplexers would be very helpful for a board I am working on. Do you
> see any chance t
Quoting Mikko Perttunen (2015-04-14 12:40:36)
> On 04/14/2015 08:21 PM, Boris Brezillon wrote:
> > Hi Mikko,
> >
> > On Tue, 14 Apr 2015 14:25:59 +0300
> > Mikko Perttunen wrote:
> >
> >> On 04/11/2015 12:11 AM, Michael Turquette wrote:
> >>>
Quoting Ray Jui (2015-04-14 12:10:35)
> Hi Mike,
>
> On 4/13/2015 12:40 PM, Ray Jui wrote:
> > Hi Mike,
> >
> > On 4/12/2015 11:02 PM, Michael Turquette wrote:
> >> Quoting Ray Jui (2015-04-12 21:08:32)
> >>>
> >>>
> >>> On
Quoting Sascha Hauer (2015-03-30 10:40:41)
> +static void mtk_pll_set_rate_regs(struct clk_hw *hw, u32 pcw,
> + int postdiv)
> +{
> + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> + u32 con1, pd, val;
> + int pll_en;
> +
> + /* set postdiv */
> + pd = r
Quoting Sascha Hauer (2015-03-30 10:40:39)
> The following changes since commit 9eccca0843205f87c00404b663188b88eb248051:
>
> Linux 4.0-rc3 (2015-03-08 16:09:09 -0700)
>
> are available in the git repository at:
>
> git://git.pengutronix.de/git/imx/linux-2.6.git tags/v4.0-clk-mediatek-v10
H
Quoting Andrew Bresticker (2015-03-30 17:15:43)
> On Mon, Mar 30, 2015 at 4:59 PM, Stephen Boyd wrote:
> > On 02/24/15 19:56, Andrew Bresticker wrote:
> >> +
> >> +void pistachio_clk_force_enable(struct pistachio_clk_provider *p,
> >> + unsigned int *clk_ids, unsigned i
Quoting Javier Martinez Canillas (2015-03-30 09:08:40)
> Hello Tomasz,
>
> On 03/30/2015 06:02 PM, Tomasz Figa wrote:
> > Hi Javier,
> >
> > 2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
> > :
> >> The Samsung helpers functions to register clocks, add the clock instance
> >> returned by the
Quoting Lee Jones (2015-03-02 00:16:06)
> On Sat, 28 Feb 2015, Maxime Coquelin wrote:
>
> > Hi Lee,
> >
> > On 02/27/2015 10:14 PM, Lee Jones wrote:
> > >Lots of platforms contain clocks which if turned off would prove fatal.
> > >The only way to recover from these catastrophic failures is to res
Quoting Javier Martinez Canillas (2015-03-31 01:59:39)
> +Tomeu who I forgot to add to the cc list.
>
> Hello Mike,
>
> Thanks a lot for your feedback.
>
> On 03/31/2015 03:40 AM, Michael Turquette wrote:
> >>
> >> I don't performance is a b
Quoting Stephen Boyd (2015-03-27 00:17:59)
> On 03/25, Paul Walmsley wrote:
> >
> > Most Linux clock framework discussions take place on the
> > linux-kernel@vger.kernel.org or linux-arm-ker...@lists.infradead.org
> > mailing lists. The volume of unrelated messages on these lists makes
> > it dif
Quoting Sergej Sawazki (2015-03-25 12:19:42)
> Am 22.03.2015 um 18:10 schrieb Michael Turquette:
> > Quoting Sergej Sawazki (2015-03-19 14:50:50)
> >> Hi Mike,
> >>
> >> I came across your "[PATCH v2 0/5] clk: dt: bindings for mux, divider &
>
Quoting Jassi Brar (2015-03-02 02:28:44)
> On 2 March 2015 at 15:48, Lee Jones wrote:
> > On Mon, 02 Mar 2015, Jassi Brar wrote:
> >
> >> On Mon, Mar 2, 2015 at 2:06 PM, Lee Jones wrote:
> >> > On Sat, 28 Feb 2015, Jassi Brar wrote:
> >> >
> >> >> On 28 February 2015 at 02:44, Lee Jones wrote:
>
Quoting Krzysztof Kozlowski (2015-04-01 02:16:08)
> 2015-04-01 6:03 GMT+02:00 Kevin Hilman :
> > Abhilash Kesavan writes:
> >
> >> On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman wrote:
> >>> Javier Martinez Canillas writes:
> >>>
> >>> [...]
> >>>
> Unfortunately I don't fully understand why
Quoting Peter Zijlstra (2015-03-26 03:41:50)
> On Thu, Mar 26, 2015 at 10:21:24AM +, Juri Lelli wrote:
> > - what about other sched classes? I know that this is very premature,
> >but I can help but thinking that we'll need to do some sort of
> >aggregation of requests, and if we put t
Quoting Robert Jarzmik (2015-02-23 11:42:53)
> Robert Jarzmik writes:
>
> > The pxa3xx scheduler relies on the pxa-timer, which requires a clock for
> > its rate. As the clock handling will be taken over by the clock
> > framework, add this missing clock.
> >
> > The miss was discovered by attemp
Quoting Mikko Perttunen (2015-03-01 04:44:33)
> This patch moves the initialization of PLL_X to be slightly before
> that of CCLK_G. This ensures that at boot, CCLK_G will immediately
> have a parent and the common clock framework can determine its
> clock rate correctly.
>
> Without this patch, c
Quoting Tomeu Vizoso (2015-03-12 07:47:53)
> From: Mikko Perttunen
>
> This clock has never been able to do anything.
>
> Signed-off-by: Mikko Perttunen
> Signed-off-by: Tomeu Vizoso
Looks good to me.
Regards,
Mike
>
> ---
>
> v2: * Don't remove emc_mux as it's being used by the MC cl
Quoting Philipp Zabel (2015-03-12 03:04:17)
> Am Freitag, den 13.02.2015, 20:18 +0100 schrieb Philipp Zabel:
> > Some board designers, when running out of clock output pads, decide to
> > (mis)use PWM output pads to provide a clock to external components.
> > This driver supports this practice by p
Quoting Ray Jui (2015-03-17 22:45:17)
> Document the device tree binding for Broadcom iProc architecture based
> clock controller
>
> Signed-off-by: Ray Jui
> Reviewed-by: Scott Branden
> ---
> .../bindings/clock/brcm,iproc-clocks.txt | 171
>
> 1 file changed,
Quoting Jyri Sarha (2015-03-18 07:52:14)
> On 03/18/15 15:53, Martin Fuzzey wrote:
> > The active low flag in the DT cell is currently ignored.
> >
> > This occurs because of_get_named_gpio_flags() does not apply the flags
> > to the underlying struct gpio_desc so the test in clk_register_gpio_gate
Quoting Thierry Reding (2015-04-10 07:15:19)
> Mike, Stephen,
>
> The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
>
> Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/li
me dependency).
> This patch also depends on the EMC frequency scaling patches (that Mike
> Acked) that I have in a separate branch. Alternatively I can provide a
> stable branch with my current stash of patches that you can pull into
> the clk tree.
Patch looks fine to me. Please add:
Ack
Quoting Lee Jones (2015-04-29 09:07:13)
> On Wed, 29 Apr 2015, Sascha Hauer wrote:
>
> > On Wed, Apr 29, 2015 at 03:17:51PM +0100, Lee Jones wrote:
> > > On Wed, 22 Apr 2015, Maxime Ripard wrote:
> > >
> > > > On Wed, Apr 08, 2015 at 06:23:44PM +0100, Lee Jones wrote:
> > > > > On Wed, 08 Apr 201
Quoting Russell King - ARM Linux (2015-04-17 03:18:33)
> On Fri, Apr 17, 2015 at 11:12:03AM +0200, Sebastian Hesselbarth wrote:
> > On 17.04.2015 04:00, Michael Welling wrote:
> > >On Fri, Apr 17, 2015 at 01:23:50AM +0200, Sebastian Hesselbarth wrote:
> > >>On 17.04.2015 00:09, Michael Welling wrot
lk: cdce706: Constify struct regmap_config
Martin Fuzzey (1):
clk: clk-gpio-gate: Fix active low
Michael Turquette (6):
clk: introduce clk_is_match
Merge tag 'v3.20-exynos5433-clk' of git://linuxtv.org/snawrocki/samsung
into clk-next
Merge tag 'mvebu-clk-4
Quoting Ben Dooks (2015-03-26 06:07:29)
> Change to using endian agnostic _relaxed IO accessors instead of __raw
>
> Signed-off-by: Ben Dooks
Applied.
Regards,
Mike
> --
> CC: Andrew Victor
> CC: Nicolas Ferre
> CC: Jean-Christophe Plagniol-Villard
> CC: Mike Turquette (maintainer:COMMON C
Quoting Boris Brezillon (2015-03-26 16:40:54)
> Hello,
>
> I recently had a problem with the at91 clk implementation: the
> programmable clock driver is not forwarding set_rate() requests to its
> parent, meaning that, if the PLLB is set to 0, it will choose another
> parent which might be inappro
Quoting Krzysztof Kozlowski (2015-03-28 09:37:05)
> 2015-03-27 17:27 GMT+01:00 Bartlomiej Zolnierkiewicz
> :
> > Commit 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK
> > down feature") enabled ARMCLK down feature on all Exynos4
> > SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature
>
Quoting Boris Brezillon (2015-03-28 18:53:43)
> The PLL impose a certain input range to work correctly, but it appears that
> this input range does not apply on the input clock (or parent clock) but
> on the input clock after it has passed the PLL divisor.
> Fix the implementation accordingly.
>
>
+Sylwester
Quoting Chanwoo Choi (2015-04-01 23:40:36)
> This patch shows the current clock rate instead of return value
> when clk_set_rate() return fail because log message means the clock rate.
>
> Cc: Mike Turquette
> Cc: Stephen Boyd
> Signed-off-by: Chanwoo Choi
> ---
> drivers/clk/clk-c
Quoting Brian Norris (2015-04-12 21:24:22)
> Hi,
>
> I've recently been looking at using the common clock framework to
> handle my CPU clocks for use by the cpufreq-dt driver, and I ran
> across a few problems with integer overflow. On a 32-bit system,
> 'unsigned long' (the type used in clk_set_r
Quoting Ray Jui (2015-04-12 21:08:32)
>
>
> On 4/10/2015 5:12 PM, Michael Turquette wrote:
> > Quoting Ray Jui (2015-03-17 22:45:17)
> >> Document the device tree binding for Broadcom iProc architecture based
> >> clock controller
> >>
> >> Sign
Quoting Rhyland Klein (2015-02-17 08:58:29)
> On 2/15/2015 7:33 AM, Mans Rullgard wrote:
> > If a mux clock is initialised (by hardware or firmware) with an
> > invalid parent, its ->get_parent() can return an out of range
> > index. For example, the generic mux clock attempts to return
> > -EINVA
Quoting Tomeu Vizoso (2015-04-13 05:17:01)
> On 11 April 2015 at 13:00, Mikko Perttunen wrote:
> > On 04/11/2015 12:08 AM, Michael Turquette wrote:
> >>
> >> Quoting Mikko Perttunen (2015-03-01 04:44:33)
> >>>
> >>> This patch moves the initiali
Quoting York Sun (2015-05-26 17:32:13)
> Michael,
>
> Can you give me some guidance here?
>
>
> On 05/26/2015 05:20 PM, York Sun wrote:
> >
> >
> > On 05/26/2015 03:38 PM, Guenter Roeck wrote:
> >> On Tue, May 26, 2015 at 12:12:11PM -0700, York Sun wrote:
> >>> Linux experts,
> >>>
> >>> I hav
Quoting Dong Aisheng (2015-05-14 06:28:59)
> __clk_set_parent_after() actually used the second argument then we
> could put this duplicate logic in there and call it with a different
> order of arguments in the success vs. error paths in this function.
>
> Cc: Mike Turquette
> Cc: Stephen Boyd
>
Quoting Bintian Wang (2015-05-23 21:11:11)
> Add clock drivers for hi6220 SoC, this driver controls the SoC
> registers to supply different clocks to different IPs in the SoC.
>
> We add one divider clock for hi6220 because the divider in hi6220
> also has a mask bit but it doesnot obey the rule d
Quoting andrey (2015-05-27 17:29:00)
>
>
> On Wed, 27 May 2015 17:10:06 -0700 Guenter Roeck
> wrote
> > On 05/27/2015 04:58 PM, andrey wrote:
> > >
> > >
> > > On Wed, 27 May 2015 16:08:12 -0700 Guenter
> Roeck wrote
> > >
> > > > On 05/27/2015 12:44 PM, andrey
Quoting Tomeu Vizoso (2015-05-25 07:53:21)
> When looking up a clk through its DT node, ensure that the corresponding
> device has been registered.
>
> Signed-off-by: Tomeu Vizoso
Ack.
Regards,
Mike
> ---
> drivers/clk/clk.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers
Quoting Kevin Hilman (2015-05-28 10:32:05)
> Bintian writes:
>
> > Hello Mike,
> >
> > On 2015/5/28 13:26, Michael Turquette wrote:
> >> Quoting Bintian Wang (2015-05-23 21:11:11)
> >>> Add clock drivers for hi6220 SoC, this driver controls the SoC
Signed-off-by: Michael Turquette
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d8afd29..15b6d71 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2642,7 +2642,7 @@ F:Documentation/devicetree/bindings/media/coda.txt
F
Quoting Kukjin Kim (2015-06-21 18:46:26)
> Krzysztof Kozlowski wrote:
> >
> > On 22.06.2015 10:38, Kukjin Kim wrote:
> > > Krzysztof Kozlowski wrote:
> > >> 2015-05-08 9:18 GMT+09:00 Krzysztof Kozlowski :
> > >>> 2015-04-04 1:43 GMT+09:00 Bartlomiej Zolnierkiewicz
> > >>> :
> > From: Thomas
Quoting Geert Uytterhoeven (2015-05-28 11:53:38)
> Currently the CPG Clock Domain code looks for MSTP clocks to power
> manage a device.
>
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plai
Quoting Geert Uytterhoeven (2015-06-15 09:15:04)
> On Thu, May 28, 2015 at 8:53 PM, Geert Uytterhoeven
> wrote:
> > Hi all,
> >
> > This patch series adds Clock Domain support to the Clock Pulse Generator
> > (CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain, to
> > be use
Quoting Bintian Wang (2015-05-28 19:08:34)
> Document DT files bindings for Hisilicon hi6220 clock.
>
> Signed-off-by: Bintian Wang
> Acked-by: Haojian Zhuang
> Suggested-by: Arnd Bergmann
> Acked-by: Stephen Boyd
Acked-by: Michael Turquette
> ---
> .../devicetr
Quoting Mike Looijmans (2015-06-02 22:25:19)
> This driver supports the TI CDCE925 programmable clock synthesizer.
> The chip contains two PLLs with spread-spectrum clocking support and
> five output dividers. The driver only supports the following setup,
> and uses a fixed setting for the output m
Quoting Bintian Wang (2015-05-28 19:08:38)
> Add clock drivers for hi6220 SoC, this driver controls the SoC
> registers to supply different clocks to different IPs in the SoC.
>
> We add one divider clock for hi6220 because the divider in hi6220
> also has a mask bit but it doesnot obey the rule d
t; Cc: Mike Turquette
> Cc: Ralf Baechle
> Cc: Stephen Boyd
> Cc: linux-...@vger.kernel.org
> Cc: linux-m...@linux-mips.org
For patches 24-30:
Acked-by: Michael Turquette
Are you wanting to take this all through the same tree, or are you happy
for the clock patches to get pic
Quoting Sylwester Nawrocki (2015-05-13 07:13:13)
> On 03/04/15 18:43, Bartlomiej Zolnierkiewicz wrote:
> > This flag is needed to fix the issue with wrong dividers being setup
> > by Common Clock Framework when using the new Exynos cpu clock support.
> >
> > The issue happens because clk_core_set_
Quoting Murali Karicheri (2015-05-29 09:04:12)
> Main PLL controller has post divider bits in a separate register in
> pll controller. Use the value from this register instead of fixed
> divider when available.
>
> Signed-off-by: Murali Karicheri
Applied to clk-next.
Regards,
Mike
> ---
> ...
Quoting Vignesh R (2015-06-03 04:51:23)
> tbclk is needed by ehrpwm to generate pwm waveforms. Hence, register
> the required clock information.
>
> Signed-off-by: Vignesh R
Looks good to me. Please feel free to add:
Acked-by: Michael Turquette
Regards,
Mike
> ---
>
Quoting Loc Ho (2015-06-17 23:28:56)
> Hi,
>
> On Wed, Jun 17, 2015 at 2:28 PM, Matthias Brugger
> wrote:
>
> X-Gene clocks implement it's name in the clock private struct.
> This is a duplication of the name field. We can delete the field
> and rely on the common implementation to r
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