From: Tuomas Tynkkynen
Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so
enable it to get the Tegra driver to build by default.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Tuomas Tynkkynen
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
.../bindings/cpufreq/tegra124-cpufreq.txt | 44
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu
-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/clk-tegra124.c | 47
drivers/clk/tegra/clk.h | 3 +++
2 files changed, 50 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index
in the device tree.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
.../bindings/clock/nvidia,tegra124-dfll.txt| 69 ++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock
of the work.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/Makefile | 2 +
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 165 +
2 files changed, 167 insertions(+)
create
From: Tuomas Tynkkynen ttynkky...@nvidia.com
Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so
enable it to get the Tegra driver to build by default.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm/configs
...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/clk-tegra124.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 623b77f..9354c42 100644
--- a/drivers/clk/tegra/clk
Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts
-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/clk-dfll.c | 666 ++-
1 file changed, 663 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/clk
...@linaro.org
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/cpufreq/Kconfig.arm| 7 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra124-cpufreq.c | 217 +
3 files changed, 225 insertions(+)
create mode 100644
devices, which rely on this
code.
Signed-off-by: Paul Walmsley pwalms...@nvidia.com
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/Makefile |1 +
drivers/clk/tegra/clk-dfll.c | 1090
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
to be calculated
on an per-chip basis.
Add utility functions to parse the Tegra-specific tables and export the
voltage-frequency pairs to the generic OPP framework for other drivers
to use.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm/boot/dts/tegra124.dtsi | 9
this to
the Venice2 should be simple, though do note that it does not have
active cooling.
Thanks,
Tuomas
Mikko Perttunen (1):
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
Paul Walmsley (1):
clk: tegra: Add DFLL DVCO reset control for Tegra124
Tuomas Tynkkynen (14):
clk: tegra: Add
On 01/06/2015 05:14 PM, Thierry Reding wrote:
On Tue, Jan 06, 2015 at 12:52:58PM +0200, Mikko Perttunen wrote:
From: Mikko Perttunen
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124
From: Mikko Perttunen
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
---
.../bindings/arm/tegra/nvidia,tegra20
From: Mikko Perttunen
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver is also
required
integer field instead of phandle for thermtrip i2c controller id
- Rearrange pmc.c using a forward declaration to prevent huge patch
Mikko Perttunen (3):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM
From: Mikko Perttunen mperttu...@nvidia.com
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver
integer field instead of phandle for thermtrip i2c controller id
- Rearrange pmc.c using a forward declaration to prevent huge patch
Mikko Perttunen (3):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM
On 01/06/2015 05:14 PM, Thierry Reding wrote:
On Tue, Jan 06, 2015 at 12:52:58PM +0200, Mikko Perttunen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30
On 11/19/2014 05:41 PM, Mikko Perttunen wrote:
On 11/18/2014 04:39 PM, Eduardo Valentin wrote:
Different drivers request API extensions in of-thermal. For this reason,
additional callbacks are required to fit the new drivers needs.
The current API implementation expects the registering sensor
of thermal zones described in device
* tree and look for the zone that refer to the sensor device pointed by
With that minor one fixed,
Tested-by: Mikko Perttunen
Reviewed-by: Mikko Perttunen
Cheers,
Mikko
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To unsubscribe from this list: send the line "unsubscribe linux-kernel" i
pointed by
With that minor one fixed,
Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi
Reviewed-by: Mikko Perttunen mikko.perttu...@kapsi.fi
Cheers,
Mikko
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the body of a message to majord...@vger.kernel.org
More majordomo
On 11/19/2014 05:41 PM, Mikko Perttunen wrote:
On 11/18/2014 04:39 PM, Eduardo Valentin wrote:
Different drivers request API extensions in of-thermal. For this reason,
additional callbacks are required to fit the new drivers needs.
The current API implementation expects the registering sensor
On 11/18/2014 12:44 AM, Eduardo Valentin wrote:
Different drivers request API extensions in of-thermal. For this reason,
additional callbacks are required to fit the new drivers needs.
The current API implementation expects the registering sensor driver
to provide a get_temp and get_trend
On 11/17/2014 03:08 PM, Thierry Reding wrote:
On Mon, Nov 17, 2014 at 02:51:24PM +0200, Mikko Perttunen wrote:
On 11/17/2014 01:43 PM, Thierry Reding wrote:
On Fri, Nov 14, 2014 at 12:47:33PM +0200, Mikko Perttunen wrote:
Tested-by: Mikko Perttunen
One potential issue I can see
On 11/17/2014 01:43 PM, Thierry Reding wrote:
On Fri, Nov 14, 2014 at 12:47:33PM +0200, Mikko Perttunen wrote:
Tested-by: Mikko Perttunen
One potential issue I can see is that if the cpufreq driver fails to probe
then you'll never get the thermal driver either. For example, Tegra124
currently
On 11/17/2014 01:43 PM, Thierry Reding wrote:
On Fri, Nov 14, 2014 at 12:47:33PM +0200, Mikko Perttunen wrote:
Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi
One potential issue I can see is that if the cpufreq driver fails to probe
then you'll never get the thermal driver either
On 11/17/2014 03:08 PM, Thierry Reding wrote:
On Mon, Nov 17, 2014 at 02:51:24PM +0200, Mikko Perttunen wrote:
On 11/17/2014 01:43 PM, Thierry Reding wrote:
On Fri, Nov 14, 2014 at 12:47:33PM +0200, Mikko Perttunen wrote:
Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi
One potential
On 11/18/2014 12:44 AM, Eduardo Valentin wrote:
Different drivers request API extensions in of-thermal. For this reason,
additional callbacks are required to fit the new drivers needs.
The current API implementation expects the registering sensor driver
to provide a get_temp and get_trend
integer field instead of phandle for thermtrip i2c controller id
- Rearrange pmc.c using a forward declaration to prevent huge patch
Mikko Perttunen (3):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
---
.../bindings/arm/tegra/nvidia,tegra20
From: Mikko Perttunen
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver is also
required
From: Mikko Perttunen
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko
Tested-by: Mikko Perttunen
One potential issue I can see is that if the cpufreq driver fails to
probe then you'll never get the thermal driver either. For example,
Tegra124 currently has no cpufreq driver, so if CONFIG_CPU_THERMAL was
enabled, then the soctherm driver would never be able
Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi
One potential issue I can see is that if the cpufreq driver fails to
probe then you'll never get the thermal driver either. For example,
Tegra124 currently has no cpufreq driver, so if CONFIG_CPU_THERMAL was
enabled, then the soctherm driver
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver
From: Mikko Perttunen mperttu...@nvidia.com
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
integer field instead of phandle for thermtrip i2c controller id
- Rearrange pmc.c using a forward declaration to prevent huge patch
Mikko Perttunen (3):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM
On 11/12/2014 05:45 PM, Thierry Reding wrote:
On Wed, Nov 12, 2014 at 08:56:33AM +0100, Tomeu Vizoso wrote:
[...]
diff --git a/drivers/memory/tegra/tegra124-emc.c
b/drivers/memory/tegra/tegra124-emc.c
[...]
+static int t124_emc_burst_regs[] = {
The t124 prefix seems rather redundant in a
On 11/12/2014 02:29 PM, Thierry Reding wrote:
On Wed, Nov 12, 2014 at 02:07:51PM +0200, Mikko Perttunen wrote:
On 11/11/2014 08:37 AM, Alexandre Courbot wrote:
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
On 11/11/2014 08:37 AM, Alexandre Courbot wrote:
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties
On 11/11/2014 08:37 AM, Alexandre Courbot wrote:
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant
On 11/12/2014 02:29 PM, Thierry Reding wrote:
On Wed, Nov 12, 2014 at 02:07:51PM +0200, Mikko Perttunen wrote:
On 11/11/2014 08:37 AM, Alexandre Courbot wrote:
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires
On 11/12/2014 05:45 PM, Thierry Reding wrote:
On Wed, Nov 12, 2014 at 08:56:33AM +0100, Tomeu Vizoso wrote:
[...]
diff --git a/drivers/memory/tegra/tegra124-emc.c
b/drivers/memory/tegra/tegra124-emc.c
[...]
+static int t124_emc_burst_regs[] = {
The t124 prefix seems rather redundant in a
From: Mikko Perttunen
Sometimes, hardware blocks want to issue requests to devices
connected to I2C buses by itself. In such case, the bus the
target device resides on must be configured into a register.
For this purpose, each I2C controller has a defined ID known
by the hardware. Add a property
From: Mikko Perttunen
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver is also
required
with this. Note that there are no compile time dependencies
between the two series; it's just that this series is no-op without the
soctherm driver being present.
Mikko Perttunen (5):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
of: Add nvidia,controller-id property to Tegra I2C
From: Mikko Perttunen
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko
From: Mikko Perttunen
I2C controller ids are required when programming hardware blocks
that send messages to devices connected to an I2C bus, such as
when the PMC sends a poweroff message to the PMIC. Add ids
to all I2C controllers in Tegra124.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei Ni
Tested-by: Wei Ni
From: Tuomas Tynkkynen
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
Sorry, I was not aware of those options.
drivers/cpufreq/Kconfig.arm
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
From: Mikko Perttunen mperttu...@nvidia.com
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed
From: Mikko Perttunen mperttu...@nvidia.com
I2C controller ids are required when programming hardware blocks
that send messages to devices connected to an I2C bus, such as
when the PMC sends a poweroff message to the PMIC. Add ids
to all I2C controllers in Tegra124.
Signed-off-by: Mikko
with this. Note that there are no compile time dependencies
between the two series; it's just that this series is no-op without the
soctherm driver being present.
Mikko Perttunen (5):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
of: Add nvidia,controller-id property to Tegra I2C
From: Mikko Perttunen mperttu...@nvidia.com
Sometimes, hardware blocks want to issue requests to devices
connected to I2C buses by itself. In such case, the bus the
target device resides on must be configured into a register.
For this purpose, each I2C controller has a defined ID known
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver
On 11/07/2014 05:54 PM, Eduardo Valentin wrote:
Terve Mikko,
On Wed, Oct 15, 2014 at 01:05:19PM +0300, Mikko Perttunen wrote:
Eduardo: ping
I had no objections with the driver at this point. Neither with the DT
part. I decided to include it in my -linus queue, which means
To better facilitate discussion, here's an outline of how the driver works:
emc_set_rate (CAR) gets called
The current timing (= rate,parent pair) is checked along with the
target timing.
If the target timing has the same clock source (~parent, see
emc_parent_clk_sources in the clk
To better facilitate discussion, here's an outline of how the driver works:
emc_set_rate (CAR) gets called
The current timing (= rate,parent pair) is checked along with the
target timing.
If the target timing has the same clock source (~parent, see
emc_parent_clk_sources in the clk
On 11/07/2014 05:54 PM, Eduardo Valentin wrote:
Terve Mikko,
On Wed, Oct 15, 2014 at 01:05:19PM +0300, Mikko Perttunen wrote:
Eduardo: ping
I had no objections with the driver at this point. Neither with the DT
part. I decided to include it in my -linus queue, which means
On 11/06/2014 10:04 AM, Alexandre Courbot wrote:
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
From: Mikko Perttunen
The driver is currently only tested on Tegra124 Jetson TK1, but should
work with other Tegra124 boards, provided that correct EMC tables are
provided through the device tree
On 11/06/2014 09:56 AM, Alexandre Courbot wrote:
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
From: Mikko Perttunen
Implements functionality needed to change the rate of the memory bus
clock.
Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
---
v2:* Use subsys_initcall(), so
On 11/06/2014 09:56 AM, Alexandre Courbot wrote:
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Implements functionality needed to change the rate of the memory bus
clock.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Signed-off-by: Tomeu Vizoso
On 11/06/2014 10:04 AM, Alexandre Courbot wrote:
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
From: Mikko Perttunen mperttu...@nvidia.com
The driver is currently only tested on Tegra124 Jetson TK1, but should
work with other Tegra124 boards, provided that correct EMC tables are
provided through
Signed-off-by: Mikko Perttunen
---
v6:
- return unrounded rates from clk_round_rate and clk_recalc_rate. The rounded
rate doesn't make much sense for a voltage controlled oscillator and cpufreq
freaks out if any rounding happens to the CPU clock rate.
drivers/clk/tegra/clk-dfll.c | 666
-off-by: Paul Walmsley
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v6:
- disable clks if resume fails
- cosmetic fix in error handling
drivers/clk/tegra/Makefile |1 +
drivers/clk/tegra/clk-dfll.c | 1090 ++
drivers/clk/tegra
devices, which rely on this
code.
Signed-off-by: Paul Walmsley pwalms...@nvidia.com
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
v6:
- disable clks if resume fails
- cosmetic fix in error handling
drivers/clk/tegra/Makefile |1
-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
v6:
- return unrounded rates from clk_round_rate and clk_recalc_rate. The rounded
rate doesn't make much sense for a voltage controlled oscillator and cpufreq
freaks out if any rounding
On 10/24/2014 06:08 PM, Vladimir Zapolskiy wrote:
Hello Mikko,
Hello Vladimir!
On 24.10.2014 17:39, Mikko Perttunen wrote:
From: Tuomas Tynkkynen
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL
On 10/24/2014 06:08 PM, Vladimir Zapolskiy wrote:
Hello Mikko,
Hello Vladimir!
On 24.10.2014 17:39, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-dfll.c | 657 ++-
1 file changed, 654 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 358c5d4..e71f4fb 100644
--- a/drivers/clk/tegra/clk
-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/Makefile | 2 +
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 165 +
2 files changed, 167 insertions(+)
create mode 100644 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
diff
-off-by: Paul Walmsley
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
- Style fixes
- Removed incorrect and unused DFLL_I2C_CFG_SLAVE_ADDR_MASK define
- Documented that dfll_register_clk can return -ENOMEM
- Harmonized clock operation order
- Check !soc before allocating
on an per-chip basis.
Add utility functions to parse the Tegra-specific tables and export the
voltage-frequency pairs to the generic OPP framework for other drivers
to use.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/mach-tegra/Kconfig | 1 +
drivers/clk/tegra/cvb.c
block will complete.
Thanks to Aleksandr Frid for identifying this and
saving hours of debugging time.
Signed-off-by: Paul Walmsley
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 47
From: Tuomas Tynkkynen
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 22 ++
1 file changed
From: Tuomas Tynkkynen
Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
From: Tuomas Tynkkynen
Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124-jetson-tk1
From: Tuomas Tynkkynen
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++-
1 file changed, 3 insertions(+), 1
From: Tuomas Tynkkynen
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
.../bindings/cpufreq/tegra124-cpufreq.txt | 44
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v5:
- Don't name cpu@0 'cpu0'. Instead, we will reference by path.
arch/arm/boot/dts/tegra124.dtsi | 9
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so
enable it to get the Tegra driver to build by default.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
.../bindings/clock/nvidia,tegra124-dfll.txt| 69 ++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
diff --git a/Documentation/devicetree
driver
for all the cpufreq operations.
This driver also relies on the DFLL driver to fill the OPP table for the
CPU0 device, so that the cpufreq-dt driver knows what frequencies to
use.
Signed-off-by: Tuomas Tynkkynen
Acked-by: Viresh Kumar
Signed-off-by: Mikko Perttunen
---
v5:
- Use
, though do note that it does not have
active cooling.
Thanks,
Tuomas
Mikko Perttunen (1):
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
Paul Walmsley (1):
clk: tegra: Add DFLL DVCO reset control for Tegra124
Tuomas Tynkkynen (14):
clk: tegra: Add binding for the Tegra124 DFLL
Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v5:
- Duplicate the cpus/cpu@0 structure here instead of referring to a named
'cpu0' node. This fits in better with the style used by Tegra device trees.
arch/arm
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