On 11/17/2014 03:08 PM, Thierry Reding wrote:
On Mon, Nov 17, 2014 at 02:51:24PM +0200, Mikko Perttunen wrote:
On 11/17/2014 01:43 PM, Thierry Reding wrote:
On Fri, Nov 14, 2014 at 12:47:33PM +0200, Mikko Perttunen wrote:
Tested-by: Mikko Perttunen
One potential issue I can see
On 11/18/2014 12:44 AM, Eduardo Valentin wrote:
Different drivers request API extensions in of-thermal. For this reason,
additional callbacks are required to fit the new drivers needs.
The current API implementation expects the registering sensor driver
to provide a get_temp and get_trend
of thermal zones described in device
* tree and look for the zone that refer to the sensor device pointed by
With that minor one fixed,
Tested-by: Mikko Perttunen
Reviewed-by: Mikko Perttunen
Cheers,
Mikko
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On 11/19/2014 05:41 PM, Mikko Perttunen wrote:
On 11/18/2014 04:39 PM, Eduardo Valentin wrote:
Different drivers request API extensions in of-thermal. For this reason,
additional callbacks are required to fit the new drivers needs.
The current API implementation expects the registering sensor
On 11/11/2014 08:37 AM, Alexandre Courbot wrote:
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties
On 11/12/2014 02:29 PM, Thierry Reding wrote:
On Wed, Nov 12, 2014 at 02:07:51PM +0200, Mikko Perttunen wrote:
On 11/11/2014 08:37 AM, Alexandre Courbot wrote:
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
On 11/12/2014 05:45 PM, Thierry Reding wrote:
On Wed, Nov 12, 2014 at 08:56:33AM +0100, Tomeu Vizoso wrote:
[...]
diff --git a/drivers/memory/tegra/tegra124-emc.c
b/drivers/memory/tegra/tegra124-emc.c
[...]
+static int t124_emc_burst_regs[] = {
The t124 prefix seems rather redundant in a
On 09/26/2014 02:45 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:13PM +0300, Mikko Perttunen wrote:
From: Mikko Perttunen
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature
On 09/29/2014 11:29 AM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 11:28:31PM +0300, Mikko Perttunen wrote:
On 09/26/2014 02:45 PM, Thierry Reding wrote:
[...]
I think a more idiomatic way to write this would be:
static int
calculate_tsensor_calibration(const struct tegra_tsensor *sensor
On 09/27/2014 03:06 PM, Juha-Matti Tilli wrote:
On Fri, Sep 26, 2014 at 11:28:31PM +0300, Mikko Perttunen wrote:
I think a more idiomatic way to write this would be:
static int
calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
struct
From: Mikko Perttunen
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Signed-off-by: Mikko Perttunen
---
v7: bunch of style fixes
drivers/thermal
On 09/17/2014 01:40 AM, Stephen Warren wrote:
That's a huge time-sink, unless I work out NFS root,
which probably isn't properly or easily supported by any distro.
FWIW, this is how I've been working, and it hasn't been /that/ difficult
to get working. The Tegra side is trivial, just append
From: Mikko Perttunen
Currently the i2c-tegra bus driver prepares, enables
and set_rates its clocks separately for each transfer.
This causes locking problems when doing I2C transfers
from clock notifiers; see
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/268653.html
2014 08:54 PM, Stephen Warren wrote:
On 08/21/2014 10:53 AM, Thierry Reding wrote:
On Thu, Aug 21, 2014 at 09:38:29AM -0600, Stephen Warren wrote:
On 08/21/2014 12:58 AM, Thierry Reding wrote:
On Wed, Aug 20, 2014 at 02:16:49PM -0600, Stephen Warren wrote:
On 08/13/2014 06:41 AM, Mikko Pertt
wrote:
On 26 August 2014 09:42, Mikko Perttunen wrote:
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory controller) clock
in the Tegra124 system-on-chip. The series has been tested
FWIW, please fix the authorship information for next version.
Cheers,
Mikko
On 25/08/14 09:29, Wei Ni wrote:
From: lightning314
Split set temp codes as common functions, so we can use it
directly when implement linux thermal framework.
And handle error return value for the
On 25/08/14 20:23, Stephen Warren wrote:
On 07/16/2014 02:54 AM, Mikko Perttunen wrote:
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
I have applied patches 2 and 3 to Tegra's for-3.18/dt branch. I fixed
the DT
On 25/08/14 22:22, Stephen Warren wrote:
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory controller) clock
in the Tegra124 system-on-chip. The series has been tested on Jetson TK1.
The first two patches remove the old "em
On 26/08/14 10:47, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Aug 26, 2014 at 10:42:21AM +0300, Mikko Perttunen wrote:
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory
-by: Mikko Perttunen
---
v2: reordered and separated includes
drivers/ata/ahci_tegra.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index f1fef74..0329044 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata
This enables AHCI_TEGRA by default. This driver is required
for Serial ATA support on Tegra124-based boards.
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs
Moi Eduardo,
can you ack this series or is there still something to do?
Thanks,
Mikko
On 21/08/14 19:01, Eduardo Valentin wrote:
Hello Juha-Matti,
On Thu, Aug 21, 2014 at 03:20:11PM +0300, Juha-Matti Tilli wrote:
On Thu, Aug 21, 2014 at 01:17:18PM +0300, Mikko Perttunen wrote:
this series
On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
Hello Mikko,
On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees
On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
Hello Mikko,
On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
This adds critical trip points to the Jetson TK1
On 09/24/2014 09:48 PM, Eduardo Valentin wrote:
Hello Mikko,
On Wed, Sep 24, 2014 at 09:43:55PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:32 PM, Eduardo Valentin wrote
On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
Mikko,
On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
...
+
+static int enable_tsensor(struct tegra_soctherm *tegra,
+ const struct tegra_tsensor *sensor,
+ struct
On 09/25/2014 08:59 AM, Thierry Reding wrote:
On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
Mikko,
On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
...
+
+static int enable_tsensor(struct tegra_soctherm
Hi,
this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC.
The branch is also available in my github repo,
git://github.com/cyndis/linux.git soctherm-v6
Thanks,
Mikko
Mikko Perttunen (4):
of: Add bindings for nvidia,tegra124-soctherm
ARM
From: Mikko Perttunen
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
Signed-off-by: Mikko Perttunen
---
v6: added comments to cooling map nodes
arch/arm/boot/dts
From: Mikko Perttunen
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Signed-off-by: Mikko Perttunen
---
v6: fixed sparse warning for wrong order
From: Mikko Perttunen
This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.
Signed-off-by: Mikko Perttunen
Acked-by: Stephen Warren
Acked-by: Eduardo Valentin
---
.../devicetree/bindings/thermal/tegra-soctherm.txt | 53 ++
include/dt
From: Mikko Perttunen
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 47
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:09PM +0300, Mikko Perttunen wrote:
Hi,
this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC.
The branch is also available in my github repo,
git://github.com/cyndis
On 09/26/2014 02:48 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 01:22:52PM +0300, Mikko Perttunen wrote:
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:09PM +0300, Mikko Perttunen wrote:
Hi,
this series adds support for the thermal monitoring features
On 09/26/2014 03:05 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 03:00:11PM +0300, Mikko Perttunen wrote:
On 09/26/2014 02:48 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 01:22:52PM +0300, Mikko Perttunen wrote:
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014
From: Mikko Perttunen
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver is also
required
From: Mikko Perttunen
Sometimes, hardware blocks want to issue requests to devices
connected to I2C buses by itself. In such case, the bus the
target device resides on must be configured into a register.
For this purpose, each I2C controller has a defined ID known
by the hardware. Add a property
From: Mikko Perttunen
I2C controller ids are required when programming hardware blocks
that send messages to devices connected to an I2C bus, such as
when the PMC sends a poweroff message to the PMIC. Add ids
to all I2C controllers in Tegra124.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei
the sensors.
Git repo at
git://github.com/cyndis/linux.git pmc-thermtrip-v3
Mikko Perttunen (5):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
of: Add nvidia,controller-id property to Tegra I2C bindings
ARM: tegra124: Add I2C controller ids to device tree
ARM: tegra: Add
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei Ni
Tested-by: Wei Ni
---
v3
From: Mikko Perttunen
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko
From: Mikko Perttunen
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen
Reviewed-by: Wei Ni
Tested-by: Wei Ni
---
v4
Before this patch, the driver included ,
which was effectively renamed to at about the same
time the ahci_tegra series landed. Fix the include path so that the
driver compiles.
Signed-off-by: Mikko Perttunen
---
This would be for 3.17.
drivers/ata/ahci_tegra.c | 2 +-
1 file changed, 1
-by: Mikko Perttunen
---
drivers/ata/ahci_tegra.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index f1fef74..ad99e0f5 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -26,6 +26,7 @@
#include
r_get"), because it changed the order in which the controllers
were probed.
The fix for this issue was suggested by Mikko Perttunen.
Signed-off-by: Tomeu Vizoso
Cc: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/ar
Reviewed-by: Mikko Perttunen
On 04/02/2015 06:00 PM, Tomeu Vizoso wrote:
It should be the first controller, not the second.
This broke USB after 6261b06 ("regulator: Defer lookup of supply to
regulator_get"), because it changed the order in which the controllers
were probed
On 04/02/2015 06:20 PM, Mikko Perttunen wrote:
Reviewed-by: Mikko Perttunen
Scratch that;
as Tuomas noted on IRC, the reset numbers here are still wrong.
phy1 should have 22 and phy2 58.
On 04/02/2015 06:00 PM, Tomeu Vizoso wrote:
It should be the first controller, not the second
s") being misapplied by git
due to the patch context being insufficient.
This broke USB after 6261b06 ("regulator: Defer lookup of supply to
regulator_get"), because it changed the order in which the controllers
were probed.
The fix for this issue was suggested by Mikko Perttunen and Tuoma
On 04/11/2015 12:08 AM, Michael Turquette wrote:
Quoting Mikko Perttunen (2015-03-01 04:44:33)
This patch moves the initialization of PLL_X to be slightly before
that of CCLK_G. This ensures that at boot, CCLK_G will immediately
have a parent and the common clock framework can determine its
-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Cc: devicet...@vger.kernel.org
---
v8:
- Changed dfll@ -> clock@
- Changed compatibility string to "nvidia,tegra124-dfll"
- Clarified how the vdd-cpu-supply property is used
- Marked nvidia,cg-scale as optional since it is a boo
-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v8:
- Removed non-standard dvco reset handlers
drivers/clk/tegra/Makefile | 2 +
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 163 +
2 files changed, 165 insertions(+)
create mode 100644
rate to zero, hanging the system.
Signed-off-by: Mikko Perttunen
---
v8:
- Added
drivers/clk/tegra/clk-tegra-super-gen4.c | 46 ++--
1 file changed, 26 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c
b/drivers/clk/tegra/clk-tegra
set should not be used, as some functions interpret these as negative error
codes.
Each SoC with these special resets should specify the defined reset control
numbers in a device tree header file.
Signed-off-by: Mikko Perttunen
---
v8:
- Added
drivers/clk/tegra/clk.c |
CPU
voltage scaling.
This series has been tested on the Jetson TK1 (Rev C). Porting this to
the Venice2 should be simple, though do note that it does not have
active cooling.
Thanks,
Tuomas
Mikko Perttunen (3):
clk: tegra: Introduce ability for SoC-specific reset control callbacks
clk: tegr
From: Tuomas Tynkkynen
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Cc: devicet...@vger.kernel.org
---
.../bindings/cpufreq
-off-by: Paul Walmsley
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Peter De Schrijver
---
v8:
- Use DVCO reset control instead of non-standard handlers
drivers/clk/tegra/Makefile |1 +
drivers/clk/tegra/clk-dfll.c | 1095
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts
driver
for all the cpufreq operations.
This driver also relies on the DFLL driver to fill the OPP table for the
CPU0 device, so that the cpufreq-dt driver knows what frequencies to
use.
Signed-off-by: Tuomas Tynkkynen
Acked-by: Viresh Kumar
Signed-off-by: Mikko Perttunen
---
drivers/cpufreq
From: Tuomas Tynkkynen
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++-
1 file changed, 3 insertions(+), 1
Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts
From: Tuomas Tynkkynen
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v8:
- Changed dfll@ -> clock@
- Added dvco reset control
arch/arm/boot/
From: Tuomas Tynkkynen
Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
v8:
- Changed dfll@ -> clock@
a
on an per-chip basis.
Add utility functions to parse the Tegra-specific tables and export the
voltage-frequency pairs to the generic OPP framework for other drivers
to use.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Peter De Schrijver
---
arch/arm/mach-tegra/Kconfig
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so
enable it to get the Tegra driver to build by default.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Tuomas Tynkkynen
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/cpufreq/Kconfig.arm| 6
From: Tuomas Tynkkynen
Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Signed-off-by: Mikko Perttunen
Acked-by: Peter De Schrijver
---
drivers/clk/tegra/clk-dfll.c | 666 ++-
1 file changed, 663 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index fb138bf..6ec64577
block will complete.
Thanks to Aleksandr Frid for identifying this and
saving hours of debugging time.
Signed-off-by: Paul Walmsley
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen
[mikko.perttunen: ported to special reset callback]
Signed-off-by: Mikko Perttunen
On 03/02/2015 10:47 AM, Alexandre Courbot wrote:
On Thu, Feb 12, 2015 at 11:06 PM, Tomeu Vizoso
wrote:
From: Mikko Perttunen
Add binding documentation for the nvidia,tegra124-emc device tree node.
Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
---
v5: * Add a short
On 03/02/2015 10:46 AM, Alexandre Courbot wrote:
On Thu, Feb 12, 2015 at 11:06 PM, Tomeu Vizoso
wrote:
From: Mikko Perttunen
Needed for the EMC and MC drivers to know what timings from the DT to use.
Signed-off-by: Mikko Perttunen
Signed-off-by: Tomeu Vizoso
---
v4: Replace magic number
of the *hardware_vsel* regulator APIs.
Signed-off-by: Mikko Perttunen
---
This was just compile-tested as I don't have a board with this regulator.
drivers/regulator/max8973-regulator.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/regulator/max8973-regulator.c
b/drivers/regulator/max8973
ile.
Signed-off-by: Mikko Perttunen
Acked-by: Michael Turquette
---
drivers/clk/tegra/clk.c | 39 +++
drivers/clk/tegra/clk.h | 3 +++
2 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 41cd
On 05/13/15 11:52, Sascha Hauer wrote:
The thermal code uses int, long and unsigned long for temperatures
in different places. Using an unsigned type limits the thermal framework
to positive temperatures without need. 'long' is 64bit on several
architectures which is not needed. Consistently use
; crit_temp)
*temp = tz->emul_temperature;
}
Reviewed-by: Mikko Perttunen
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fore but aren't now. But I don't know why that would matter.
Reviewed-by: Mikko Perttunen
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Please read the FAQ at http://www.tux.org/lkml/
On 05/20/15 11:34, Sascha Hauer wrote:
On Wed, May 20, 2015 at 10:12:44AM +0300, Mikko Perttunen wrote:
On 05/13/15 11:52, Sascha Hauer wrote:
The thermal code uses int, long and unsigned long for temperatures
in different places. Using an unsigned type limits the thermal framework
to positive
Hi, very good patch!
Here are a few small comments. Aside those, you should also add a
section to
Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt in a
separate patch.
Thanks,
Mikko.
On 05/21/2015 04:20 PM, Arto Merilainen wrote:
> This patch adds support for Video Image
On 05/21/2015 06:10 PM, Arto Merilainen wrote:
...
+
+vic->rst = devm_reset_control_get(dev, "vic03");
I might prefer just "vic" as the clock/reset name. The name is often
used as a sort of "role" for the clock/reset for the device, not
necessarily the raw name of the "correct"
-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Michael Turquette
---
.../bindings/clock/nvidia,tegra124-dfll.txt| 79 ++
1 file changed, 79 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
diff --git
From: Tuomas Tynkkynen
Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
on an per-chip basis.
Add utility functions to parse the Tegra-specific tables and export the
voltage-frequency pairs to the generic OPP framework for other drivers
to use.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Peter De Schrijver
Acked-by: Michael Turquette
From: Tuomas Tynkkynen
Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Michael Turquette
---
arch/arm
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts
-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Michael Turquette
---
drivers/clk/tegra/Makefile | 2 +
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 161 +
2 files changed, 163 insertions(+)
create mode 100644 drivers/clk/tegra/clk
From: Tuomas Tynkkynen
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
.../bindings/cpufreq/tegra124-cpufreq.txt | 44
Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts
From: Tuomas Tynkkynen
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
drivers/cpufreq/Kconfig.arm| 6
From: Tuomas Tynkkynen
The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so
enable it to get the Tegra driver to build by default.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
just renames a
driver),
so hopefully we can get this merged.
Mikko Perttunen (2):
clk: tegra: Introduce ability for SoC-specific reset control callbacks
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
Paul Walmsley (1):
clk: tegra: Add DFLL DVCO reset control for Tegra124
Tuomas
set should not be used, as some functions interpret these as negative error
codes.
Each SoC with these special resets should specify the defined reset control
numbers in a device tree header file.
Signed-off-by: Mikko Perttunen
Acked-by: Michael Turquette
---
drivers/clk/tegra/clk.c |
Signed-off-by: Mikko Perttunen
Acked-by: Peter De Schrijver
Acked-by: Michael Turquette
---
drivers/clk/tegra/clk-dfll.c | 666 ++-
1 file changed, 663 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk
driver
for all the cpufreq operations.
This driver also relies on the DFLL driver to fill the OPP table for the
CPU0 device, so that the cpufreq-dt driver knows what frequencies to
use.
Signed-off-by: Tuomas Tynkkynen
Acked-by: Viresh Kumar
Signed-off-by: Mikko Perttunen
---
drivers/cpufreq
From: Tuomas Tynkkynen
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Michael Turquette
---
arch/arm/boot/dts/tegra124.dtsi | 25
From: Tuomas Tynkkynen
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Michael Turquette
---
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++-
1 file
-off-by: Paul Walmsley
Signed-off-by: Tuomas Tynkkynen
Signed-off-by: Mikko Perttunen
Acked-by: Peter De Schrijver
Acked-by: Michael Turquette
---
drivers/clk/tegra/Makefile |1 +
drivers/clk/tegra/clk-dfll.c | 1095 ++
drivers/clk/tegra/clk-dfll.h
block will complete.
Thanks to Aleksandr Frid for identifying this and
saving hours of debugging time.
Signed-off-by: Paul Walmsley
[ttynkkynen: ported to tegra124 from tegra114]
Signed-off-by: Tuomas Tynkkynen
[mikko.perttunen: ported to special reset callback]
Signed-off-by: Mikko Perttunen
The series
Tested-by: Mikko Perttunen
on Jetson-TK1.
I rebased my cpufreq series on top of this and everything's working well
now. :)
Thanks,
Mikko.
On 04/17/2015 10:29 AM, Boris Brezillon wrote:
...
--
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On 05/14/2015 01:47 AM, Rafael J. Wysocki wrote:
> ...
If I'm supposed to apply this, I need ACKs from the appropriate people on
all the patches where they are still missing. Thanks!
I believe Thierry Reding will apply the series; your ACK as cpufreq
maintainer for patch 13, and maybe
On 05/15/2015 05:09 AM, Viresh Kumar wrote:
On 15 May 2015 at 01:45, Rafael J. Wysocki wrote:
You need ACKs from Viresh for those two, then. He's officially responsible
for ARM cpufreq drivers.
I thought an Ack for 14th is enough :)
For: 12/13/14.
Acked-by: Viresh Kumar
Thanks! :)
It
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