Re: [PATCH v2 3/3] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186

On 04.04.2017 16:43, Mikko Perttunen wrote: The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - Only one regs entry arch/arm64/boot/dts/nvidia/tegra186.dt

Re: [PATCH] gpu: host1x: select IOMMU_IOVA

Ah, had to forget something :) Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 19.04.2017 21:24, Arnd Bergmann wrote: When IOMMU_IOVA is not built-in but host1x is, we get a link error: drivers/gpu/host1x/dev.o: In function `host1x_remove': dev.c:(.text.host1x_remove+0x50): und

Re: [PATCH] [RFC] gpu: host1x: shut up warning about DMA API misuse

On 19.04.2017 21:24, Arnd Bergmann wrote: When dma_addr_t and phys_addr_t are not the same size, we get a warning from the dma_alloc_wc function: drivers/gpu/host1x/cdma.c: In function 'host1x_pushbuffer_init': drivers/gpu/host1x/cdma.c:94:48: error: passing argument 3 of 'dma_alloc_wc' from

Re: [PATCH] irqchip/gic: Don't write to GICD_ICFGR0

On 06.04.2017 12:26, Marc Zyngier wrote: On 06/04/17 09:17, Mikko Perttunen wrote: From: Matt Craighead <mcraigh...@nvidia.com> According to the GICv2 specification, the GICD_ICFGR0, or GIC_DIST_CONFIG[0] register is read-only. Therefore avoid writing to it. Have you verified that thi

Re: [PATCH] gpu: host1x: Free the IOMMU domain when there is no device to attach

On 07/11/2017 05:44 PM, Paul Kocialkowski wrote: On Tue, 2017-07-11 at 14:37 +, Marcel Ziswiler wrote: On Tue, 2017-07-11 at 11:49 +0300, Paul Kocialkowski wrote: On Mon, 2017-07-10 at 21:33 +0200, Paul Kocialkowski wrote: When there is no device to attach to the IOMMU domain, as may be

Re: [PATCH 4/4] thermal: Add Tegra BPMP thermal sensor driver

On 01.07.2017 05:53, Eduardo Valentin wrote: Hey Mikko, Sorry for the late answer, Likewise, On Fri, Jun 16, 2017 at 02:28:25PM +0300, Mikko Perttunen wrote: On Tegra186, the BPMP (Boot and Power Management Processor) exposes an interface to thermal sensors on the system-on-chip

Re: [PATCH 1/4] arm64: tegra: Add BPMP thermal sensor to Tegra186

On 01.07.2017 02:56, Eduardo Valentin wrote: On Fri, Jun 16, 2017 at 02:28:22PM +0300, Mikko Perttunen wrote: This adds the thermal sensor device provided by the BPMP, and the relevant thermal sensors to the Tegra186 device tree. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> ---

Re: [PATCH] gpu: host1x: Free the IOMMU domain when there is no device to attach

Thanks for the patch, didn't consider this case. I really need to get together some system to automatically test on multiple platforms.. :) Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> On 10.07.2017 22:33, Paul Kocialkowski wrote: When there is no device to attach to the IOMMU

[PATCH v2 5/5] thermal: Add Tegra BPMP thermal sensor driver

-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - don't allocate space for disabled zones - allow compilation with COMPILE_TEST drivers/thermal/Makefile | 2 +- drivers/thermal/tegra/Kconfig| 7 + drivers/thermal/tegra/Makefile | 3 +- drivers/thermal/tegr

[PATCH v2 2/5] dt-bindings: Add bindings for nvidia,tegra186-bpmp-thermal

In Tegra186, the BPMP (Boot and Power Management Processor) implements an interface that is used to read system temperatures, including CPU cluster and GPU temperatures. This binding describes the thermal sensor that is exposed by BPMP. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>

[PATCH v2 4/5] firmware: tegra: Add stubs when BPMP not enabled

Add static inline stubs to bpmp.h when CONFIG_BPMP is not enabled. This allows building BPMP-related drivers with COMPILE_TEST. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - added patch include/soc/tegra/bpmp.h | 42 +++--- 1 file c

[PATCH v2 1/5] arm64: tegra: Add BPMP thermal sensor to Tegra186

This adds the thermal sensor device provided by the BPMP, and the relevant thermal sensors to the Tegra186 device tree. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - added trips and cooling-maps nodes arch/arm64/boot/dts/nvidia/tegra186.dtsi

[PATCH v2 3/5] firmware: tegra: Expose tegra_bpmp_mrq_return

Expose and export the tegra_bpmp_mrq_return function for use of drivers outside the core BPMP driver. This function is used to reply to messages originating from the BPMP, which is required in the thermal driver. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/firmware

Re: [PATCH v2 1/5] arm64: tegra: Add BPMP thermal sensor to Tegra186

to help improve the system] url: https://github.com/0day-ci/linux/commits/Mikko-Perttunen/arm64-tegra-Add-BPMP-thermal-sensor-to-Tegra186/20170726-055759 base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next config: arm64-allnoconfig (attached as .config) compiler: aarch64

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 08/19/2017 01:36 AM, Dmitry Osipenko wrote: On 18.08.2017 19:15, Mikko Perttunen wrote: Since Tegra186 the Host1x hardware allows syncpoints to be assigned to specific channels, preventing any other channels from incrementing them. Enable this feature where available and assign syncpoints

Re: [PATCH 4/4] drm/tegra: Use u64_to_user_ptr helper

On 08/19/2017 01:05 AM, Dmitry Osipenko wrote: On 18.08.2017 19:15, Mikko Perttunen wrote: Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values to user pointers instead of writing out the cast manually. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drive

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 08/19/2017 01:09 PM, Dmitry Osipenko wrote: On 19.08.2017 11:10, Mikko Perttunen wrote: [snip] +host1x_hw_syncpt_set_protection(host, true); Is it really okay to force the protection? Maybe protection should be enabled with a respect to CONFIG_TEGRA_HOST1X_FIREWALL? In that case we

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 08/19/2017 02:11 PM, Dmitry Osipenko wrote: On 19.08.2017 13:35, Mikko Perttunen wrote: On 08/19/2017 01:09 PM, Dmitry Osipenko wrote: On 19.08.2017 11:10, Mikko Perttunen wrote: [snip] +host1x_hw_syncpt_set_protection(host, true); Is it really okay to force the protection? Maybe

Re: [PATCH 2/4] gpu: host1x: Enable gather filter

On 08/19/2017 01:42 PM, Dmitry Osipenko wrote: On 18.08.2017 19:15, Mikko Perttunen wrote: The gather filter is a feature present on Tegra124 and newer where the hardware prevents GATHERed command buffers from executing commands normally reserved for the CDMA pushbuffer which is maintained

[PATCH 6/6] drm/tegra: Add Tegra186 support for VIC

Add Tegra186 support for VIC - no changes are required except for new firmware and compatibility string. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 1 + drivers/gpu/drm/tegra/vic.c | 10 ++ 2 files changed, 11 insertions(+) diff

[PATCH 1/6] arm64: tegra: Add #power-domain-cells for BPMP

Add #power-domain-cells for the BPMP node on Tegra186 so that the power domain provider may be used. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.d

[PATCH 4/6] dt-bindings: host1x: Fix and add Tegra186 information

Add note that address/size-cells should be 2 on 64-bit systems, and add Tegra186-specific register range properties. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 9 +++-- 1 file changed, 7 insertions

[PATCH 0/6] Host1x and VIC support for Tegra186

code. The series has been tested on the Jetson TX1 (T210) and TX2 (T186) using the host1x_test test suite available at http://github.com/cyndis/host1x_test The series itself is available at http://github.com/cyndis/linux, branch host1x-t186-1 Cheers, Mikko Mikko Perttunen (6): arm64: tegra

[PATCH 2/6] arm64: tegra: Add host1x on Tegra186

Add the node for Host1x on the Tegra186, without any subdevices for now. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 ++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi

[PATCH 5/6] gpu: host1x: Add Tegra186 support

with this commit. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/Makefile| 3 +- drivers/gpu/host1x/dev.c | 60 ++- drivers/gpu/host1x/dev.h | 4 + drivers/gpu/host1x/hw/cdm

[PATCH 3/6] arm64: tegra: Add VIC on Tegra186

Add a node for the Video Image Compositor on the Tegra186. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/

Re: [PATCH v2 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

On 08.06.2017 01:11, Rob Herring wrote: On Thu, Jun 01, 2017 at 11:04:04AM +0300, Mikko Perttunen wrote: The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. What the block is should also go in the binding doc. With that, I don't

[PATCH] PM / Domains: Call driver's noirq callbacks

Currently genpd installs its own suspend_noirq and resume_noirq callbacks, but never calls down to the driver's corresponding callbacks. Add these calls. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/base/power/domain.c | 8 1 file changed, 8 insertions(+)

Re: [PATCH v2] PM / Domains: Call driver's noirq callbacks

On 20.06.2017 17:18, Ulf Hansson wrote: On 20 June 2017 at 15:38, Mikko Perttunen <mperttu...@nvidia.com> wrote: Currently genpd installs its own suspend_noirq, resume_noirq, and poweroff_noirq callbacks, but never calls down to the driver's corresponding callbacks. Add these calls. Sign

Re: [PATCH] PM / Domains: Call driver's noirq callbacks

On 20.06.2017 15:47, Ulf Hansson wrote: On 20 June 2017 at 14:05, Mikko Perttunen <mperttu...@nvidia.com> wrote: Currently genpd installs its own suspend_noirq and resume_noirq callbacks, but never calls down to the driver's corresponding callbacks. Add these calls. Signed-off-by:

[PATCH v2] PM / Domains: Call driver's noirq callbacks

Currently genpd installs its own suspend_noirq, resume_noirq, and poweroff_noirq callbacks, but never calls down to the driver's corresponding callbacks. Add these calls. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - Moved pm_generic_suspend_noirq to

[PATCH v3] PM / Domains: Call driver's noirq callbacks

Currently genpd installs its own noirq callbacks, but never calls down to the driver's corresponding callbacks. Add these calls. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v3: - Factored out common code in pm_genpd_{suspend,poweroff}_noirq - Added pm_generic_* calls t

[PATCH v2 2/2] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186

The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/bo

[PATCH v2 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt| 17 + 1 file changed, 17 insertions(+)

[PATCH v2 0/2] Device tree changes for Tegra186 cpufreq

Hi, these are the device tree and bindings changes for the Tegra186 cpufreq driver that was recently merged. The patches are the same as those that were originally posted with the driver. Mikko Perttunen (2): dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster arm64: tegra: Add

Re: [PATCH v3 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

On 13.06.2017 15:42, Thierry Reding wrote: On Mon, Jun 12, 2017 at 01:23:04PM +0300, Mikko Perttunen wrote: The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> Acked-b

Re: [PATCH v3 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

On 13.06.2017 15:46, Mikko Perttunen wrote: On 13.06.2017 15:42, Thierry Reding wrote: On Mon, Jun 12, 2017 at 01:23:04PM +0300, Mikko Perttunen wrote: The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko

Re: [PATCH v2 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

On 09.06.2017 23:54, Rob Herring wrote: On Thu, Jun 8, 2017 at 2:32 AM, Mikko Perttunen <cyn...@kapsi.fi> wrote: On 08.06.2017 01:11, Rob Herring wrote: On Thu, Jun 01, 2017 at 11:04:04AM +0300, Mikko Perttunen wrote: The Tegra186 CCPLEX_CLUSTER area contains memory-mapped reg

[PATCH 2/4] dt-bindings: Add bindings for nvidia,tegra186-bpmp-thermal

In Tegra186, the BPMP (Boot and Power Management Processor) implements an interface that is used to read system temperatures, including CPU cluster and GPU temperatures. This binding describes the thermal sensor that is exposed by BPMP. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.

[PATCH 1/4] arm64: tegra: Add BPMP thermal sensor to Tegra186

This adds the thermal sensor device provided by the BPMP, and the relevant thermal sensors to the Tegra186 device tree. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 48 1 file changed, 48 inse

[PATCH 4/4] thermal: Add Tegra BPMP thermal sensor driver

-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/thermal/Makefile | 2 +- drivers/thermal/tegra/Kconfig| 7 + drivers/thermal/tegra/Makefile | 3 +- drivers/thermal/tegra/bpmp-thermal.c | 253 +++ 4 files changed, 263 insertions

[PATCH 3/4] firmware: tegra: Expose tegra_bpmp_mrq_return

Expose and export the tegra_bpmp_mrq_return function for use of drivers outside the core BPMP driver. This function is used to reply to messages originating from the BPMP, which is required in the thermal driver. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/firmware

[PATCH v3 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster

The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> Acked-by: Rob Herring <r...@kernel.org> --- .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 20 +++

Re: [PATCH v2 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

On 09/05/2017 04:33 PM, Dmitry Osipenko wrote: On 05.09.2017 11:10, Mikko Perttunen wrote: ... >> diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c index 8447a56c41ca..0161da331702 100644 --- a/drivers/gpu/host1x/hw/channel_hw.c +++ b/drivers/gpu/hos

Re: [PATCH] arm64: tegra: Add SMMU node for Tegra186

Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> Tested-by: Mikko Perttunen <mperttu...@nvidia.com> Tested to work with Host1x :) I noticed a slight difference with downstream where downstream has global interrupts 170 and 171 - but looks like the latter is for secure fau

[PATCH v2 0/6] Miscellaneous improvements to Host1x and TegraDRM

was tested on TX1 and TX2 and should be applied on the previously posted Tegra186 support series. Cheers, Mikko Mikko Perttunen (6): gpu: host1x: Enable Tegra186 syncpoint protection gpu: host1x: Enable gather filter gpu: host1x: Improve debug disassembly formatting gpu: host1x: Disassemble more

[PATCH v2 3/6] gpu: host1x: Improve debug disassembly formatting

y newlines and by fixing other small issues. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> Reviewed-by: Dmitry Osipenko <dig...@gmail.com> Tested-by: Dmitry Osipenko <dig...@gmail.com> --- This uses pr_cont, which there are currently talks of being replaced with something

[PATCH v2 4/6] gpu: host1x: Disassemble more instructions

The disassembler for debug dumps was missing some newer host1x opcodes. Add disassembly support for these. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/hw/debug_hw.c | 57 --- drivers/gpu/host1x/hw/debug_hw_1x01.

[PATCH v2 5/6] gpu: host1x: Fix incorrect comment for channel_request

This function actually doesn't sleep in the version that was merged. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/channel.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu/host1x/channel.c

[PATCH v2 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

since that would require extra work and is unnecessary with the current channel allocation model. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- Notes: v2: - Changed from set_protection(bool) to enable_protection - Added some comments - Added missing check for hv_regs

[PATCH v2 2/6] gpu: host1x: Enable gather filter

-off-by: Mikko Perttunen <mperttu...@nvidia.com> Reviewed-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/host1x/hw/channel_hw.c | 22 ++ drivers/gpu/host1x/hw/hw_host1x04_channel.h | 12 drivers/gpu/host1x/hw/hw_host1x05_channel.h | 12 +++

[PATCH v2 5/6] gpu: host1x: Add Tegra186 support

with this commit. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> Reviewed-by: Dmitry Osipenko <dig...@gmail.com> Tested-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/host1x/Makefile| 3 +- drivers/gpu/host1x/dev.c | 60 +++

[PATCH v2 4/6] dt-bindings: host1x: Add Tegra186 information

Add the Tegra186-specific hypervisor-related register range properties. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - Dropped incorrect note about cells properties. .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 1 file changed, 4 inse

[PATCH v2 1/6] arm64: tegra: Add #power-domain-cells for BPMP

Add #power-domain-cells for the BPMP node on Tegra186 so that the power domain provider may be used. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.d

[PATCH v2 2/6] arm64: tegra: Add host1x on Tegra186

Add the node for Host1x on the Tegra186, without any subdevices for now. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - Changed address-cells and size-cells to 1 and fixed the ranges property correspondingly. arch/arm64/boot/dts/nvidia/tegra186.dts

[PATCH v2 6/6] drm/tegra: Add Tegra186 support for VIC

Add Tegra186 support for VIC - no changes are required except for new firmware and compatibility string. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 1 + drivers/gpu/drm/tegra/vic.c | 10 ++ 2 files changed, 11 insertions(+) diff

[PATCH v2 3/6] arm64: tegra: Add VIC on Tegra186

Add a node for the Video Image Compositor on the Tegra186. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- v2: - Fixed reg property in accordance with changed parent cells. arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12 1 file changed, 12 insertions(+) diff --git

[PATCH v2 0/6] Host1x and VIC support for Tegra186

. The series has been tested on the Jetson TX1 (T210) and TX2 (T186) using the host1x_test test suite available at http://github.com/cyndis/host1x_test The series itself is available at http://github.com/cyndis/linux, branch host1x-t186-1 Cheers, Mikko Mikko Perttunen (6): arm64: tegra: Add

[PATCH v2 6/6] drm/tegra: Use u64_to_user_ptr helper

Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values to user pointers instead of writing out the cast manually. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-)

Re: [PATCH v3 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

On 09/30/2017 05:41 AM, Dmitry Osipenko wrote: On 28.09.2017 15:50, Mikko Perttunen wrote: .. diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c index 8447a56c41ca..b929d7f1e291 100644 --- a/drivers/gpu/host1x/hw/channel_hw.c +++ b/drivers/gpu/host1x/hw

[PATCH v3 3/6] gpu: host1x: Improve debug disassembly formatting

y newlines and by fixing other small issues. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> Reviewed-by: Dmitry Osipenko <dig...@gmail.com> Tested-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/host1x/debug.c| 14 ++- drivers/gpu/ho

[PATCH v3 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

since that would require extra work and is unnecessary with the current channel allocation model. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/dev.h | 15 + drivers/gpu/host1x/hw/channel_hw.c | 3 +++ drivers/gpu/host1x/hw/syncpt_hw.c

[PATCH v3 2/6] gpu: host1x: Enable gather filter

-off-by: Mikko Perttunen <mperttu...@nvidia.com> Reviewed-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/host1x/hw/channel_hw.c | 22 ++ drivers/gpu/host1x/hw/hw_host1x04_channel.h | 12 drivers/gpu/host1x/hw/hw_host1x05_channel.h | 12 +++

[PATCH v3 5/6] gpu: host1x: Fix incorrect comment for channel_request

This function actually doesn't sleep in the version that was merged. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> Reviewed-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/host1x/channel.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/driver

[PATCH v3 0/6] Miscellaneous improvements to Host1x and TegraDRM

in case of job timeouts. They are now actually readable by humans without use of additional scripts. Patch 4 is a simple aesthetical fix to the TegraDRM submit path. Everything was tested on TX1 and TX2 and should be applied on the previously posted Tegra186 support series. Cheers, Mikko Mikko

[PATCH v3 6/6] drm/tegra: Use u64_to_user_ptr helper

Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values to user pointers instead of writing out the cast manually. Also do some other cleanup with user pointers to make them stand out more and look cleaner. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/g

[PATCH v3 4/6] gpu: host1x: Disassemble more instructions

The disassembler for debug dumps was missing some newer host1x opcodes. Add disassembly support for these. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/hw/debug_hw.c | 59 --- drivers/gpu/host1x/hw/debug_hw_1x01.

Re: [PATCH 2/4] gpu: host1x: Enable gather filter

On 08/21/2017 08:27 PM, Mikko Perttunen wrote: On 08/20/2017 07:59 PM, Dmitry Osipenko wrote: On 20.08.2017 19:44, Dmitry Osipenko wrote: On 20.08.2017 19:24, Dmitry Osipenko wrote: On 18.08.2017 19:15, Mikko Perttunen wrote: The gather filter is a feature present on Tegra124 and newer

Re: [PATCH 2/4] gpu: host1x: Enable gather filter

On 08/20/2017 07:59 PM, Dmitry Osipenko wrote: On 20.08.2017 19:44, Dmitry Osipenko wrote: On 20.08.2017 19:24, Dmitry Osipenko wrote: On 18.08.2017 19:15, Mikko Perttunen wrote: The gather filter is a feature present on Tegra124 and newer where the hardware prevents GATHERed command

[PATCH 3/4] gpu: host1x: Improve debug disassembly formatting

y newlines and by fixing other small issues. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/debug.c| 14 ++- drivers/gpu/host1x/debug.h| 14 --- drivers/gpu/host1x/hw/debug_hw.c | 46 ++--

[PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

since that would require extra work and is unnecessary with the current channel allocation model. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/dev.h | 16 drivers/gpu/host1x/hw/channel_hw.c | 3 +++ drivers/gpu/host1x/hw/syncpt_hw.c

[PATCH 0/4] Miscellaneous improvements to Host1x and TegraDRM

to the TegraDRM submit path. Everything was tested on TX1 and TX2 and should be applied on the previously posted Tegra186 support series. Cheers, Mikko *** BLURB HERE *** Mikko Perttunen (4): gpu: host1x: Enable Tegra186 syncpoint protection gpu: host1x: Enable gather filter gpu: host1x

[PATCH 4/4] drm/tegra: Use u64_to_user_ptr helper

Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values to user pointers instead of writing out the cast manually. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff

[PATCH 2/4] gpu: host1x: Enable gather filter

-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/hw/channel_hw.c | 22 ++ drivers/gpu/host1x/hw/hw_host1x04_channel.h | 12 drivers/gpu/host1x/hw/hw_host1x05_channel.h | 12 3 files changed, 46 insertions(+) diff

Re: [PATCH v2 0/6] Host1x and VIC support for Tegra186

On 05.09.2017 14:10, Daniel Vetter wrote: Since this is new hw support, is there also open source userspace using all this? The VIC HW in Tegra186 is backwards compatible with the one in Tegra210, which has open userspace (https://github.com/cyndis/vaapi-tegra-driver), so that userspace

Re: [tegra186]: emmc resume failing after booting from snapshot image

The upstream kernel currently has no core rail suspend support (LP0/SC7) on Tegras - in general the downstream kernel (used e.g. in L4T) is the reference that has the most functionality on Tegra. IIRC the MMC subsystem and Tegra MMC driver between upstream and downstream are currently quite

Re: [PATCH 06/10] drm/tegra: Deliver job completion callback to client

On 16.11.2017 18:40, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: To allow client drivers to free resources when jobs have completed, deliver job completion callbacks to them. This requires adding reference counting to context objects, as job completion can happen after

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 12.11.2017 13:23, Dmitry Osipenko wrote: On 11.11.2017 00:15, Dmitry Osipenko wrote: On 07.11.2017 18:29, Dmitry Osipenko wrote: On 07.11.2017 16:11, Mikko Perttunen wrote: On 05.11.2017 19:14, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: Add an option

Re: [PATCH] drm/tegra: gem: Use PTR_ERR_OR_ZERO()

On 29.11.2017 00:18, Vasyl Gomonovych wrote: Fix ptr_ret.cocci warnings: drivers/gpu/drm/tegra/gem.c:420:1-3: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Signed-off-by: Vasyl Gomonovych

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 29.11.2017 14:18, Dmitry Osipenko wrote: On 29.11.2017 12:10, Mikko Perttunen wrote: On 12.11.2017 13:23, Dmitry Osipenko wrote: On 11.11.2017 00:15, Dmitry Osipenko wrote: On 07.11.2017 18:29, Dmitry Osipenko wrote: On 07.11.2017 16:11, Mikko Perttunen wrote: On 05.11.2017 19:14, Dmitry

Re: [PATCH] staging: nvec: Fix usleep_range is preferred over udelay

On 11/29/2017 06:00 PM, Joshua Abraham wrote: Signed-off-by: Joshua Abraham This patch fixes the issue: CHECK: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt --- drivers/staging/nvec/nvec.c | 2 +- 1 file changed, 1 insertion(+),

[PATCH 1/2] arm64: defconfig: Enable CONFIG_ARM_TEGRA186_CPUFREQ

Enable Tegra186 CPU frequency scaling support by default. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6356c6da34ea..427110

[PATCH 2/2] arm64: defconfig: Enable CONFIG_TEGRA_BPMP_THERMAL

Enable Tegra BPMP thermal sensor support by default, built as a module. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 427110

Re: [PATCH] soc/tegra: pmc: fix child-node lookup

as of_find_node_by_name() drops a reference to its first argument. Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC") Cc: stable <sta...@vger.kernel.org> # 4.0 Cc: Mikko Perttunen <mperttu...@nvidia.com> Signed-off-by: Johan Hovold <jo...@kernel.org>

[PATCH 06/10] drm/tegra: Deliver job completion callback to client

for contexts. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 27 --- drivers/gpu/drm/tegra/drm.h | 4 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra

[PATCH 01/10] gpu: host1x: Parameterize channel aperture size

The size of a single channel's aperture is different on Tegra186 vs. previous chips. Parameterize the value using a new define in the register definition headers. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/hw/channel_hw.c | 3 +-- drivers/gpu/hos

[PATCH 04/10] gpu: host1x: Lock classes during job submission

. This patch implements locking on all platforms from Tegra20 to Tegra186. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/cdma.c | 1 + drivers/gpu/host1x/cdma.h | 1 + drivers/gpu/host1x/hw/cdma_hw.c

[PATCH 05/10] gpu: host1x: Add job done callback

Allow job submitters to set a callback to be called when the job has completed. The jobs are stored and the callbacks called outside the CDMA lock area to allow the callbacks to do CDMA-requiring operations like freeing channels. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- d

[PATCH 09/10] drm/tegra: Boot VIC in runtime resume

This ensures that there are no concurrency issues when multiple users are trying to use VIC concurrently, and also simplifies the code slightly. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/vic.c | 47 +++--

[PATCH 08/10] drm/tegra: Implement dynamic channel allocation model

, this patch only adapts VIC to the new model. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 46 ++ drivers/gpu/drm/tegra/drm.h | 7 +++- drivers/gpu/drm/tegra/vic.c | 79 +++-- 3 files chang

[PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

Add an option to host1x_channel_request to interruptibly wait for a free channel. This allows IOCTLs that acquire a channel to block the userspace. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm/tegra/drm.c | 9 + drivers/gpu/drm/tegra/gr2d.

[PATCH 03/10] gpu: host1x: Add lock around channel allocation

With the new channel allocation model, multiple threads can be allocating channels simultaneously. Therefore we need to add a lock around the code. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/channel.c | 7 +++ drivers/gpu/host1x/channel.h | 2 ++ 2

[PATCH 00/10] Dynamic Host1x channel allocation

sted using the host1x_test test suite, and also by running the performance test of host1x_test in parallel. Thanks, Mikko Mikko Perttunen (10): gpu: host1x: Parameterize channel aperture size gpu: host1x: Print MLOCK state in debug dumps on T186 gpu: host1x: Add lock around channel allocation g

[PATCH 07/10] drm/tegra: Make syncpoints be per-context

As a preparation for each context potentially being able to have a separate hardware channel, and thus requiring a separate syncpoint, move syncpoints to be stored inside each context instead of global client data. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/drm

[PATCH 02/10] gpu: host1x: Print MLOCK state in debug dumps on T186

Add support for dumping current MLOCK state in debug dumps also on T186, now that MLOCKs are used by the driver. Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> --- drivers/gpu/host1x/hw/debug_hw_1x06.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff

Re: [PATCH 04/10] gpu: host1x: Lock classes during job submission

On 05.11.2017 18:46, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: >> ... +static int mlock_id_for_class(unsigned int class) +{ +#if HOST1X_HW >= 6 + switch (class) + { + case HOST1X_CLASS_HOST1X: + return 0; + case HOST1X_

Re: [PATCH 08/10] drm/tegra: Implement dynamic channel allocation model

On 05.11.2017 19:43, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: In the traditional channel allocation model, a single hardware channel was allocated for each client. This is simple from an implementation perspective but prevents use of hardware scheduling. This patch

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 05.11.2017 19:14, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: Add an option to host1x_channel_request to interruptibly wait for a free channel. This allows IOCTLs that acquire a channel to block the userspace. Wouldn't it be more optimal to request channel and block

Re: [PATCH 04/10] gpu: host1x: Lock classes during job submission

On 07.11.2017 23:23, Dmitry Osipenko wrote: On 07.11.2017 15:28, Mikko Perttunen wrote: On 05.11.2017 18:46, Dmitry Osipenko wrote: On 05.11.2017 14:01, Mikko Perttunen wrote: ... +static int mlock_id_for_class(unsigned int class) +{ +#if HOST1X_HW >= 6 +switch (class) +{ +c

Re: [PATCH 6/8] serial: Add Tegra Combined UART driver

On 14.05.2018 01:20, Andy Shevchenko wrote: On Sun, May 13, 2018 at 9:04 PM, Mikko Perttunen <cyn...@kapsi.fi> wrote: On 05/13/2018 05:16 PM, Andy Shevchenko wrote: On Tue, May 8, 2018 at 2:44 PM, Mikko Perttunen <mperttu...@nvidia.com> wrote: The Tegra Combined UART (TCU)

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