> -Original Message-
> From: arndbergm...@gmail.com [mailto:arndbergm...@gmail.com] On
> Behalf Of Arnd Bergmann
> Sent: Tuesday, August 15, 2017 2:16 PM
> To: Oleksandr Shamray
> Cc: gregkh ; Linux Kernel Mailing List ker...@vger.kernel.org>; Linux ARM ;
> de
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
V3->v4
Comments pointed by Rob Herring
- delete unnecessary "status" and "reg-shif
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
---
v3->v4
Comments pointed by Arnd Bergmann
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
v2->v3
v1->v2
Comments pointed by Greg KH
- change license type from GPLv2/BSD to GPLv2
Comments p
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
> -Original Message-
> From: Greg KH [mailto:gre...@linuxfoundation.org]
> Sent: Friday, October 20, 2017 5:54 PM
> To: Oleksandr Shamray
> Cc: a...@arndb.de; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; devicet...@vger.kernel.org;
> open..
> -Original Message-
> From: Chip Bilbrey [mailto:c...@bilbrey.org]
> Sent: Monday, November 6, 2017 12:33 AM
> To: Oleksandr Shamray
> Cc: gre...@linuxfoundation.org; a...@arndb.de; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@
the hardware specific driver.
Oleksandr Shamray (4):
drivers: jtag: Add JTAG core driver
drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master
driver
Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx
families JTAG master driver
Documentation: jtag: Add ABI docu
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v11->v12
v10->v11
v9->v10
v8->v9
v7->v8
Comments pointed by pointed by Joel St
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
---
v11->v12
Comments pointed by Chip Bilbrey
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
v10->v11
v9->v10
V8->v9
Comments pointed by Arnd Bergmann
- add *data
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v11->v12
Tobias Klauser
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/interfase/interface
v10->v11
v9->v10
Fixes added by Oleksandr:
- chan
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v10->v11
v9->v10
Fixes added by Oleksandr:
- change jtag-cdev to jtag-dev in documentation
- update Kernel Version and Date in jtag-dev documentation;
v8->v9
v7-&
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
---
v10->v11
v9->v10
V8->v9
Comments pointed by Arnd Bergmann
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Joel Stanley
- aspeed_jtag_init replace goto to return;
- change input variabl
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v10->v11
v9->v10
v8->v9
v7->v8
Comments pointed by pointed by Joel Stanley
- Change compa
Hi,
Thanks for review>
> -Original Message-
> From: Chip Bilbrey [mailto:c...@bilbrey.org]
> Sent: Monday, November 6, 2017 12:33 AM
> To: Oleksandr Shamray
> Cc: gre...@linuxfoundation.org; a...@arndb.de; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.inf
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v9->v10
- change jtag-cdev to jtag-dev in documentation
- update Kernel Version and Date in jtag-dev documentation;
v8->v9
v7->v8
v6->v7
Comments pointed by
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v9->v10
v8->v9
v7->v8
Comments pointed by pointed by Joel Stanley
- Change compatible
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
---
v9->v10
V8->v9
Comments pointed by Arnd Bergmann
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Joel Stanley
- aspeed_jtag_init replace goto to return;
- change input variables type from
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
> -Original Message-
> From: Florian Fainelli [mailto:f.faine...@gmail.com]
> Sent: 26 декабря 2017 г. 1:09
> To: Oleksandr Shamray ;
> gre...@linuxfoundation.org; a...@arndb.de
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@
From: Linus Torvalds
---
Makefile |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/Makefile b/Makefile
index 92b74bc..eb1f597 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
VERSION = 4
PATCHLEVEL = 15
SUBLEVEL = 0
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
NAME
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v15->v16
Comments pointed by Joel Stanley
- change clocks = <&clk_apb> to proper cloc
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v15->v16
Comments pointed by Joel Stanley
- Add reset_control on Jtag init/deinit
v14->v15
Comments pointed by Joel Stanley
- Add ARCH_ASPEED || COMPILE_TEST to K
dware specific driver.
Linus Torvalds (1):
Linux 4.15-rc6
Oleksandr Shamray (3):
drivers: jtag: Add JTAG core driver
drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master
driver
Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx
families JTAG master driver
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
do not pay attention about this.
Best Regards,
Oleksandr Shamray
> -Original Message-
> From: Oleksandr Shamray [mailto:oleksan...@mellanox.com]
> Sent: 12 января 2018 г. 18:55
> To: gre...@linuxfoundation.org; a...@arndb.de
> Cc: linux-kernel@vger.kernel.org
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v15->v16
v14->v15
v13->v14
v12->v13
v11->v12
Tobias Klauser
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/interfase/interface
v10-
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v15->v16
Comments pointed by Joel Stanley
- change clocks = <&clk_apb> to proper cloc
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v15->v16
Comments pointed by Joel Stanley
- Add reset_control on Jtag init/deinit
v14->v15
Comments pointed by Joel Stanley
- Add ARCH_ASPEED || COMPILE_TEST to K
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v17->v18
v16->v17
v15->v16
v14->v15
v13->v14
v12->v13
v11->v12
Tobias Klauser
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/inte
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley
- change clocks = <&cl
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley
- Add reset_control on Jtag init/deinit
v14->v15
Comments pointed by Joel Stanley
- Add
Hi Julia
> -Original Message-
> From: Julia Cartwright [mailto:jul...@eso.teric.us]
> Sent: 15 января 2018 г. 22:52
> To: Oleksandr Shamray
> Cc: gre...@linuxfoundation.org; a...@arndb.de; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devic
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v16->v17
v15->v16
Comments pointed by Joel Stanley
- Add reset_control on Jtag init/deinit
v14->v15
Comments pointed by Joel Stanley
- Add ARCH_ASPEED || COMPIL
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v16->v17
v15->v16
Comments pointed by Joel Stanley
- change clocks = <&clk_apb>
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v16->v17
v15->v16
v14->v15
v13->v14
v12->v13
v11->v12
Tobias Klauser
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/interfase/inter
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v19->v20
Comments pointed by Randy Dunlap
- Fix JTAG doccumentation
v18->v19
Pavel Machek
- Added JTAG doccumentation to Documentation/jtag
v17->v18
v16->v17
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v19->v20
v18->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley
EEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v19->v20
Notifications from kbuild test robot
- add static declaration to 'aspeed_jtag_init' and
'aspeed_jtag_deinit' functions
v18->v19
EEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v21->v22
v20->v21
v19->v20
v18->v19
v17->v18
v16->v17
v15->v16
Comments po
Hi Andy.
Thanks for review.
Please read my answers inline.
> -Original Message-
> From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
> Sent: 16 мая 2018 г. 0:22
> To: Oleksandr Shamray
> Cc: Greg Kroah-Hartman ; Arnd Bergmann
> ; Linux Kernel Mailing List
>
Hi Andy.
Thanks for review.
Please read my answers inline.
> -Original Message-
> From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
> Sent: 16 мая 2018 г. 0:00
> To: Oleksandr Shamray
> Cc: Greg Kroah-Hartman ; Arnd Bergmann
> ; Linux Kernel Mailing List
>
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v21->v22
Comments pointed by Randy Dunlap
- fix spell in ABI doccumentation
v20->v21
Comments pointed by Randy Dunlap
- Fix JTAG dirver help in Kconfig
v19->v20
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v21->v22
v20->v21
v19->v20
v18->v19
v17->v18
v16->v17
v15->v16
Comments po
EEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v21->v22
Comments pointed by Andy Shevchenko
- rearrange ASPEED register defines
- simplified JTAG divider calculation formula
- change delay function in bit-b
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v21->v22
Comments pointed by Randy Dunlap
- fix spell in ABI doccumentation
v20->v21
Comments pointed by Randy Dunlap
- Fix JTAG dirver help in Kconfig
v19->v20
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
EEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v21->v22
Comments pointed by Andy Shevchenko
- rearrange ASPEED register defines
- simplified JTAG divider calculation formula
- change delay function in bit-b
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v21->v22
v20->v21
v19->v20
v18->v19
v17->v18
v16->v17
v15->v16
Comments po
Hi Greg.
Thanks for your review.
Please see my comments inline.
Best Regards,
Oleksandr Shamray
> -Original Message-
> From: Greg KH [mailto:gre...@linuxfoundation.org]
> Sent: 28 мая 2018 г. 15:35
> To: Oleksandr Shamray
> Cc: a...@arndb.de; linux-kernel@vger.kernel
EEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
EEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v19->v20
v18->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v19->v20
Comments pointed by Randy Dunlap
- Fix JTAG doccumentation
v18->v19
Pavel Machek
- Added JTAG doccumentation to Documentation/jtag
v17->v18
v16->v17
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v19->v20
Notifications from kbuild test robot
- add static declaration to 'aspeed_jtag_init' and
'aspeed_jtag_deinit' functions
v18->v19
st_idle {
__u8 reset;
__u8 endstate;
__u8 tck;
};
You can see usage example on
https://github.com/mellanoxbmc/mellanox-bmc-tools/tree/master/mlnx_cpldprog
Best Regards,
Oleksandr Shamray
> -Original Message-
> From: Florian Fa
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v18-v19
Pavel Machek
- Added JTAG doccumentation to Documentation/jtag
v17->v18
v16->v17
v15->v16
v14->v15
v13->v14
v12->v13
v11->v12
Tob
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
Acked-by: Joel Stanley
---
v18->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley
- Add reset_control on Jtag init/deinit
v14->v15
Comments pointed by Joel Stanley
-
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v17->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley
- change clocks = &
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v13->v14
v12->v13
v11->v12
v10->v11
v9->v10
v8->v9
v7->v8
Comments pointed by po
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v13->v14
v12->v13
v11->v12
Tobias Klauser
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/interfase/interface
v10->v11
v9->v10
Fixes
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
---
v13->v14
Comments pointed by Philippe Ombredanne
- Change style of head block comment from /**/ to //
v12->v13
Comments pointed by Philippe Ombredanne
- Change jtag-aspeed.c licence type to
SPDX-License-Identifier: G
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardware
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v14->v15
v13->v14
v12->v13
v11->v12
v10->v11
v9->v10
v8->v9
v7->v8
Comments po
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v14->v15
v13->v14
v12->v13
v11->v12
Tobias Klauser
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/interfase/interface
v10->v11
v9-&
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
Acked-by: Philippe Ombredanne
---
v14->v15
Comments pointed by Joel Stanley
- Add ARCH_ASPEED || COMPILE_TEST to Kconfig
- remove unused offset variable
- remove "aspeed_jtag" from dev_err and dev_dbg mess
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
---
v5->v6
Comments pointed by Tobias Klauser
- Small nit: s/doccumentation/Documentation/
v4->
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
---
v5->v6
v4->v5
Comments pointed by Arnd Bergmann
- Added HAS_IOMEM dependence in Kconfig to avoid
"undefined reference to `devm_ioremap_resource'" error,
because in some arch this not supported
v3->v4
Comments pointed by
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray
Acked-by: Arnd Bergmann
---
v7->v8
v6->v7
Comments pointed by Pavel Machek
- Added jtag-cdev documentation to Documentation/ABI/testing folder
---
Documentation/ABI/testing/jatg-cdev
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Rob Herring
Acked-by: Arnd Bergmann
---
v7->v8
Comments pointed by Arnd Bergmann
- Change compatible string
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
Acked-by: Arnd Bergmann
---
v7->v8
Comments pointed by Arnd Bergmann
- aspeed_jtag_init replace goto to return;
- change input variables type from __u32 to u32
in functios freq_get, freq_set, status_get
- change sm_ variables type from char to u8
-
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
9.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardwar
: Oleksandr Shamray
Signed-off-by: Jiri Pirko
---
v6->v7
Notifications from kbuild test robot
- Add include to jtag-asapeed.c
v5->v6
v4->v5
Comments pointed by Arnd Bergmann
- Added HAS_IOMEM dependence in Kconfig to avoid
"undefined reference to `devm_ioremap_resource'"
frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray
Signed-off-by: Jiri
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