On Sat, 18 Aug 2018 11:15:18 PDT (-0700), Linus Torvalds wrote:
On Fri, Aug 17, 2018 at 1:28 PM Palmer Dabbelt wrote:
I remember having sent this on Wednesday, but for some reason I don't see it in
your tree or my outbox so I might be crazy.
You might indeed have been having hallucina
On Sat, 18 Aug 2018 06:37:59 PDT (-0700), li...@roeck-us.net wrote:
Hi Palmer,
On Fri, Aug 17, 2018 at 01:28:11PM -0700, Palmer Dabbelt wrote:
[ ... ]
This tag boots a Fedora root filesystem on QEMU's master branch for me,
and before this morning's rebase (from 4.18-rc8 to 4.18) it
On Mon, 20 Aug 2018 19:47:28 PDT (-0700), alan...@andestech.com wrote:
On Mon, Aug 20, 2018 at 03:22:55PM -0700, Palmer Dabbelt wrote:
On Tue, 07 Aug 2018 20:24:43 PDT (-0700), alan...@andestech.com wrote:
>Just a side note: (Assume that atomic and compressed is on)
>
>Before t
urce()")
first patched then removed pcibios_align_resource() from the microblaze
architecture code but failed to remove the comment that was added to
it.
Remove it since it has now become stale and it is quite confusing.
Signed-off-by: Lorenzo Pieralisi
Cc: Palmer Dabbelt
Cc: Bjorn Helgaas
Cc:
On Tue, 21 Aug 2018 12:45:50 PDT (-0700), mer...@debian.org wrote:
On Tue, Aug 21, 2018 at 11:31:48AM -0700, Palmer Dabbelt wrote:
On Sat, 18 Aug 2018 06:37:59 PDT (-0700), li...@roeck-us.net wrote:
[...]
> Do you have vmlinux embedded in bbl ?
>
> With separate bbl and vmlinux
On Tue, 21 Aug 2018 23:03:53 PDT (-0700), Christoph Hellwig wrote:
On Tue, Aug 21, 2018 at 10:34:38PM +0530, Anup Patel wrote:
The cpu_operations is certainly required because SOC vendors will add
vendor-specific mechanism to selectively bringing-up CPUs/HARTs instead
of all CPUs entering Linux
-- I'd noticed this when we were messing around in here recently and
assumed there was some reason for the non-orthogonality. As far as the RISC-V
stuff goes, feel free to add a
Reviewed-by: Palmer Dabbelt
I can deal with the inevitable merge conflicts on our end, as they'll be
trivial :).
for the paramater type. Here it is with a commit message,
although still untested because I haven't got round to setting up a riscv
toolchain yet.
FWIW, Arnd built them last time he updated the cross tools so you should be
able to get GCC 8.1.0 for RISC-V from there. I use this make.cross
2017 04:01:12 PDT (-0700), mark.rutl...@arm.com wrote:
> On Tue, Sep 26, 2017 at 06:56:30PM -0700, Palmer Dabbelt wrote:
>> +/*
>> + * This is particularly ugly: it appears we can't actually get the
>> definition
>> + * of task_struct here, but we need access to the C
On Tue, 26 Jun 2018 21:22:26 PDT (-0700), alan...@andestech.com wrote:
This patch adds an option, CONFIG_FPU, to enable/disable floating
procedures. Also, some style issues are fixed.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Zong Li
---
arch/riscv/Kconfig | 9
arch
On Wed, 20 Jun 2018 18:40:07 PDT (-0700), z...@andestech.com wrote:
The stvec's value must be 4 byte alignment by specification definition.
This directive avoids to stvec be set the non-alignment value by the
following code in head.S
/* Point stvec to virtual address of intruction after satp wr
On Wed, 25 Jul 2018 02:36:43 PDT (-0700), Christoph Hellwig wrote:
The RISC-V ISA mandantes the presence of a simple, per-hart (hardware
thread) interrupt controller availiable to supervisor mode. In addition
the RISC-V specification contains the definition of a programmable
interrupt controller
return IRQ_HANDLED;
}
static void
Acked-by: Palmer Dabbelt
I think it's probably easier to have the whole patch set go through the IRQ
tree, so I won't put these in the RISC-V tree unless someone says something.
INTERRUPT_CAUSE_TIMER 5
-#define INTERRUPT_CAUSE_EXTERNAL9
-
void riscv_timer_interrupt(void);
#include
Acked-by: Palmer Dabbelt
/arm
to kernel/irq/handle.c.
Signed-off-by: Palmer Dabbelt
---
arch/arm/Kconfig | 5 -
arch/arm/include/asm/irq.h | 5 -
arch/arm/kernel/entry-armv.S | 6 --
arch/arm/kernel/irq.c| 10 --
include/linux/irq.h | 18 ++
kernel/irq
This is the second version of a patch set titled "Use arm64's scheme for
registering first-level IRQ handlers on RISC-V". That patch set's cover letter
is still the best way to describe what's going on, so I'm just copying it here:
This patch set has been sitting around for a while, but it go
It appears that openrisc copied arm64's MULTI_IRQ_HANDLER code (which
came from arm). I wanted to make this generic so I could use it in the
RISC-V port. This patch converts the openrisc code to use the generic
version.
Signed-off-by: Palmer Dabbelt
---
arch/openrisc/Kconfig | 1 +
additional
load to the interrupt latency, but there's a lot of tuning left to be
done there on RISC-V so I think it's OK for now.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/Kbuild | 1 +
arch/riscv/kernel/entry.S | 5 +++--
On Thu, 18 Jan 2018 07:45:13 PST (-0800), Christoph Hellwig wrote:
I think this should not be asm-generic and lib, but kernel/irq/handle.c
and include/linux/irq.h, under the CONFIG_MULTI_IRQ_HANDLER symbol
already used by arm.
Also for completeness of the series please convert arm, arm64 and
ope
NDLER instead.
Signed-off-by: Palmer Dabbelt
---
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/irq.h | 2 --
arch/arm64/kernel/irq.c | 10 --
3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index c9a7e9e1414f..effb04a
On Thu, 25 Jan 2018 00:31:53 PST (-0800), sho...@gmail.com wrote:
On Wed, Jan 24, 2018 at 07:07:56PM -0800, Palmer Dabbelt wrote:
The old mechanism for handling IRQs on RISC-V was pretty ugly: the arch
code looked at the Kconfig entry for our first-level irqchip driver and
called into it
ork on our port is
coordinated.
This patch changes the RISC-V maintainers entry to reflect these new
bits of infrastructure.
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index e3581413420c..a3
") makes it possible
> to share generic GCC library routines by several
> architectures.
>
> This commit removes several generic GCC library
> routines from arch/mips/lib/ in favour of similar
> routines from lib/.
>
> Signed-off-by: Antony Pavlov
> Cc: Palmer
by several
architectures.
This commit removes several generic GCC library
routines from arch/mips/lib/ in favour of similar
routines from lib/.
Signed-off-by: Antony Pavlov
Cc: Palmer Dabbelt
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
arch/mips/Kconfig
From: Palmer Dabbelt
I've copied this from arm64, but it appears to be the same code that's
in arm and openrisc. I wanted to use it for RISC-V's interrupt handler
as well, so despite this only being a handful of lines of code it seems
worth having a generic version -- if it
an additional
load to the interrupt latency, but there's a lot of tuning left to be
done there on RISC-V so I think it's OK for now.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/Kbuild | 1 +
arch/riscv/kernel/entry.S | 5 +++--
This patch set has been sitting around for a while, but it got a bit lost in
the shuffle. In RISC-V land we currently couple do_IRQ (the C entry point for
interrupt handling) to our first-level interrupt controller. While this isn't
completely crazy (as the first-level interrupt controller is spe
On Wed, 17 Jan 2018 10:08:27 PST (-0800), sudeep.ho...@arm.com wrote:
(Sorry, somehow I missed this email until I saw Jeremy's reply today)
On 15/01/18 16:07, Palmer Dabbelt wrote:
On Mon, 15 Jan 2018 04:33:38 PST (-0800), sudeep.ho...@arm.com wrote:
On Fri, Jan 12, 2018 at 06:59:10PM
From: Palmer Dabbelt
We were hoping to avoid making this visible to userspace, but it looks
like we're going to have to because QEMU's user-mode emulation doesn't
want to emulate a vDSO. Having vDSO-only system calls was a bit
unothodox anyway, so I think in this case it's
;
Before this patch:
[0.00] Kernel command line: root=/dev/vda ro root=/dev/vda ro
After this patch:
[0.00] Kernel command line: root=/dev/vda ro
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/setup.c | 16
1 file changed, 1
This is just some cruft left over from before the port converted to
device tree. The right way to handle memory regions is to specify them
in the device tree, which BBL (our simplest bootloader) is already
capable of doing. This patch simply removes the cruft.
Signed-off-by: Palmer Dabbelt
: Signature made Fri 26 Jan 2018 08:02:15 AM PST
gpg:using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
gpg:issuer "pal...@dabbelt.com"
gpg: Good signature from "Palmer Dabbelt " [ultimate]
gpg: aka "Palmer Dabbelt " [ultimate
On Fri, 26 Jan 2018 15:13:19 PST (-0800), Linus Torvalds wrote:
On Fri, Jan 26, 2018 at 2:39 PM, Palmer Dabbelt wrote:
I can understand if it's too late to get this into 4.15, but given that
it's not a code change I was hoping it'd still be OK.
No problem. Something li
it removes several generic GCC library
routines from arch/mips/lib/ in favour of similar
routines from lib/.
Signed-off-by: Antony Pavlov
Cc: Palmer Dabbelt
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
arch/mips/Kconfig | 5 +
arch/mips/lib/Make
to go.
CC: Adhemerval Zanella
Signed-off-by: Palmer Dabbelt
---
arch/riscv/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 2c6adf12713a..02076f3a2883 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -10,7 +10,6 @@ conf
On Tue, 09 Jan 2018 00:11:45 PST (-0800), h...@lst.de wrote:
On Mon, Jan 08, 2018 at 05:27:56PM -0800, Palmer Dabbelt wrote:
During the glibc upstreaming it was suggested that CLONE_BACKWARDS was a
deprecated ABI decision. I think we just copied it from ARM, but I
don't see any reason to
rs are nice to
haves, but they seem sane for 4.15 to me.
Christoph Hellwig (2):
riscv: remove CONFIG_MMU ifdefs
riscv: rename SR_* constants to match the spec
Karsten Merker (1):
RISC-V: Add a basic defconfig
Palmer
properties. That change
helps to clarify its one remaining use (matching
cacheinfo nodes that represent shared caches) which
will be used by the ACPI/PPTT code in the following patches.
Cc: Palmer Dabbelt
Cc: Albert Ou
Signed-off-by: Jeremy Linton
---
arch/riscv/kernel/cacheinfo.c | 1 +
drivers/base
On Fri, 09 Mar 2018 10:36:44 PST (-0800), parri.and...@gmail.com wrote:
On Fri, Mar 09, 2018 at 09:56:21AM -0800, Palmer Dabbelt wrote:
On Fri, 09 Mar 2018 04:13:40 PST (-0800), parri.and...@gmail.com wrote:
>Atomics present the same issue with locking: release and acquire
>variants need
On Fri, 09 Mar 2018 13:30:08 PST (-0800), parri.and...@gmail.com wrote:
On Fri, Mar 09, 2018 at 10:54:27AM -0800, Palmer Dabbelt wrote:
On Fri, 09 Mar 2018 10:36:44 PST (-0800), parri.and...@gmail.com wrote:
[...]
>This belongs to the "few style fixes" (in the specific, 8
It appears that openrisc copied arm64's GENERIC_IRQ_MULTI_HANDLER code
(which came from arm). I wanted to make this generic so I could use it
in the RISC-V port. This patch converts the openrisc code to use the
generic version.
Acked-by: Stafford Horne
Signed-off-by: Palmer Dabbelt
---
On Fri, 09 Mar 2018 15:00:56 PST (-0800), t...@linutronix.de wrote:
On Fri, 9 Mar 2018, Palmer Dabbelt wrote:
On Fri, 09 Mar 2018 02:20:12 PST (-0800), t...@linutronix.de wrote:
> This looks sensible. We have two options for getting this merged:
>
> 1) I'll take the whole lot t
;
spin_unlock(s);
spin_lock(s);
r1 = READ_ONCE(*x);
}
exists (1:r0=1 /\ 1:r1=0)
[1] https://marc.info/?l=linux-kernel&m=151930201102853&w=2
https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkAXM
https://marc.info/?l=linux-kernel&
On Wed, 07 Mar 2018 02:52:42 PST (-0800), parri.and...@gmail.com wrote:
On Tue, Mar 06, 2018 at 06:02:28PM -0800, Palmer Dabbelt wrote:
On Mon, 05 Mar 2018 10:24:09 PST (-0800), parri.and...@gmail.com wrote:
>Current implementations map locking operations using .rl and .aq
>annot
/* CONFIG_BLK_DEV_INITRD */
I haven't looked through the rest of the patch set, but this is a pretty
trivial change so feel free to add a
Reviewed-By: Palmer Dabbelt
if you'd like. If you'd like it merged through my tree then just say
something!
On Mon, 26 Mar 2018 01:07:54 PDT (-0700), Arnd Bergmann wrote:
On Tue, Mar 20, 2018 at 6:52 PM, Palmer Dabbelt wrote:
On Tue, 20 Mar 2018 00:53:21 PDT (-0700), t...@linutronix.de wrote:
On Tue, 20 Mar 2018, kbuild test robot wrote:
Hi Palmer,
FYI, the error/warning still remains
On Mon, 26 Mar 2018 22:27:36 PDT (-0700), t...@linutronix.de wrote:
On Mon, 26 Mar 2018, Palmer Dabbelt wrote:
On Mon, 26 Mar 2018 01:07:54 PDT (-0700), Arnd Bergmann wrote:
> On Tue, Mar 20, 2018 at 6:52 PM, Palmer Dabbelt wrote:
> > On Tue, 20 Mar 2018 00:53:21 PDT (
On Thu, 15 Mar 2018 01:50:40 PDT (-0700), z...@andestech.com wrote:
These patches resolve the some issues of loadable module.
- symbol out of ranges
- unknown relocation types
The reference of external variable and function symbols
cannot exceed 32-bit offset ranges in kernel module.
The mod
On Thu, 15 Mar 2018 03:42:25 PDT (-0700), Arnd Bergmann wrote:
On Thu, Mar 15, 2018 at 10:59 AM, Hannes Reinecke wrote:
On 03/15/2018 10:42 AM, David Howells wrote:
Do we have anything left that still implements NOMMU?
RISC-V ?
(evil grin :-)
Is anyone producing a chip that includes enough
On Tue, 20 Mar 2018 00:53:21 PDT (-0700), t...@linutronix.de wrote:
On Tue, 20 Mar 2018, kbuild test robot wrote:
Hi Palmer,
FYI, the error/warning still remains.
Zapped the commit as well...
Sorry, I got the flu at ELC and have been offline for a bit. It looks like
you've kept the IRQ an
On Sun, 18 Mar 2018 05:51:50 PDT (-0700), r...@kernel.org wrote:
On Wed, Mar 14, 2018 at 09:31:05AM -0700, Palmer Dabbelt wrote:
Systems that boot without a chosen node in the device tree should still
respect the command lines that are built into the kernel. This patch
avoids bailing out of
On Mon, 09 Apr 2018 00:07:11 PDT (-0700), alan...@andestech.com wrote:
On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote:
On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alan...@andestech.com wrote:
>This patch provide a basic PMU, riscv_base_pmu, which supports two
>general ha
On Tue, 10 Apr 2018 09:09:32 PDT (-0700), wi...@infradead.org wrote:
On Tue, Apr 10, 2018 at 05:25:50PM +0200, Laurent Dufour wrote:
arch/powerpc/include/asm/pte-common.h | 3 ---
arch/riscv/Kconfig | 1 +
arch/s390/Kconfig
tting MULTI_IRQ_HANDLER instead.
Reviewed-by: Christoph Hellwig
Signed-off-by: Palmer Dabbelt
---
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/irq.h | 2 --
arch/arm64/kernel/irq.c | 10 --
3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/
s not marked as __ro_after_init.
Signed-off-by: Palmer Dabbelt
---
arch/arm/Kconfig | 19 +++
arch/arm/include/asm/irq.h | 5 -
arch/arm/include/asm/mach/arch.h | 2 +-
arch/arm/kernel/entry-armv.S | 10 ++
arch/arm/kernel/irq.c
It appears that openrisc copied arm64's GENERIC_IRQ_MULTI_HANDLER code
(which came from arm). I wanted to make this generic so I could use it
in the RISC-V port. This patch converts the openrisc code to use the
generic version.
Acked-by: Stafford Horne
Signed-off-by: Palmer Dabbelt
---
additional
load to the interrupt latency, but there's a lot of tuning left to be
done there on RISC-V so I think it's OK for now.
Reviewed-by: Christoph Hellwig
Acked-by: Stafford Horne
Signed-off-by: Palmer Dabbelt
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/K
This is my third version of this patch set, but the original cover
letter is still the most relevant description I can come up with.
This patch set has been sitting around for a while, but it got a bit lost
in the shuffle. In RISC-V land we currently couple do_IRQ (the C entry
point f
kernel/irq under CONFIG_GENERIC_MULTI_IRQ_HANDLER. This patch is
currently all dead code, but it will be enabled in the various other
architectures in subsequent patches.
Signed-off-by: Palmer Dabbelt
---
include/linux/irq.h | 18 ++
kernel/irq/Kconfig | 5 +
kernel/irq
On Thu, 08 Mar 2018 07:55:33 PST (-0800), Arnd Bergmann wrote:
- riscv32 is not yet supported by Linux or glibc, but that seems
very likely to come in the future, maybe one or two years from
now.
I'm hoping it'll be a lot less than a year away :).
On Thu, 08 Mar 2018 11:14:52 PST (-0800), s...@shealevy.com wrote:
Hi Palmer,
Palmer Dabbelt writes:
On Tue, 20 Feb 2018 05:50:43 PST (-0800), s...@shealevy.com wrote:
Signed-off-by: Shea Levy
---
arch/riscv/mm/init.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/mm
On Thu, 08 Mar 2018 11:47:08 PST (-0800), s...@shealevy.com wrote:
Palmer Dabbelt writes:
On Thu, 08 Mar 2018 11:14:52 PST (-0800), s...@shealevy.com wrote:
Hi Palmer,
Palmer Dabbelt writes:
On Tue, 20 Feb 2018 05:50:43 PST (-0800), s...@shealevy.com wrote:
Signed-off-by: Shea Levy
On Thu, 08 Mar 2018 13:03:03 PST (-0800), parri.and...@gmail.com wrote:
On Wed, Mar 07, 2018 at 10:33:49AM -0800, Palmer Dabbelt wrote:
[...]
I'm going to go produce a new set of spinlocks, I think it'll be a bit more
coherent then.
I'm keeping your other patch in my qu
On Fri, 09 Mar 2018 02:20:12 PST (-0800), t...@linutronix.de wrote:
On Wed, 7 Mar 2018, Palmer Dabbelt wrote:
This is my third version of this patch set, but the original cover
letter is still the most relevant description I can come up with.
This patch set has been sitting around for a
s (u=1 /\ v=1 /\ 0:r1=0 /\ 1:r1=0)
[1] https://marc.info/?l=linux-kernel&m=151930201102853&w=2
https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkAXM
https://marc.info/?l=linux-kernel&m=151633436614259&w=2
Suggested-by: Daniel Lustig
Signed-off-by:
On Fri, 09 Mar 2018 04:16:43 PST (-0800), parri.and...@gmail.com wrote:
On Thu, Mar 08, 2018 at 02:11:12PM -0800, Palmer Dabbelt wrote:
On Thu, 08 Mar 2018 13:03:03 PST (-0800), parri.and...@gmail.com wrote:
>On Wed, Mar 07, 2018 at 10:33:49AM -0800, Palmer Dabbelt wrote:
>
>[...]
>
On Tue, 13 Mar 2018 01:35:05 PDT (-0700), z...@andestech.com wrote:
These patches resolve the some issues of loadable module.
- symbol out of ranges
- unknown relocation types
The reference of external variable and function symbols
cannot exceed 32-bit offset ranges in kernel module.
The mod
On Tue, 13 Mar 2018 18:34:19 PDT (-0700), zong...@gmail.com wrote:
2018-03-14 5:30 GMT+08:00 Shea Levy :
Hi Palmer,
Palmer Dabbelt writes:
On Tue, 13 Mar 2018 01:35:05 PDT (-0700), z...@andestech.com wrote:
These patches resolve the some issues of loadable module.
- symbol out of ranges
On Tue, 13 Mar 2018 14:30:53 PDT (-0700), s...@shealevy.com wrote:
Hi Palmer,
Palmer Dabbelt writes:
On Tue, 13 Mar 2018 01:35:05 PDT (-0700), z...@andestech.com wrote:
These patches resolve the some issues of loadable module.
- symbol out of ranges
- unknown relocation types
The
ction with a patch to move
from COMMANDLINE_OVERRIDE to COMMANDLINE_FORCE), still works on systems
with and without the chosen node, and builds on ARM64.
CC: Michael J Clark
CC: Trung Tran
CC: Moritz Fischer
Signed-off-by: Palmer Dabbelt
---
drivers/of/fdt.c | 14 --
1 file c
x27;t even work any more.
Thanks to Mortiz and Trung for finding the original bug, and for Michael
for suggeting a better fix.
CC: Trung Tran
CC: Moritz Fischer
CC: Michael J Clark
Signed-off-by: Palmer Dabbelt
---
arch/riscv/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
di
On Wed, 14 Mar 2018 05:07:09 PDT (-0700), s...@shealevy.com wrote:
Palmer Dabbelt writes:
On Tue, 13 Mar 2018 14:30:53 PDT (-0700), s...@shealevy.com wrote:
Hi Palmer,
Palmer Dabbelt writes:
On Tue, 13 Mar 2018 01:35:05 PDT (-0700), z...@andestech.com wrote:
These patches resolve the
On Wed, 14 Mar 2018 04:54:14 PDT (-0700), s...@shealevy.com wrote:
Palmer Dabbelt writes:
On Tue, 13 Mar 2018 18:34:19 PDT (-0700), zong...@gmail.com wrote:
2018-03-14 5:30 GMT+08:00 Shea Levy :
Hi Palmer,
Palmer Dabbelt writes:
On Tue, 13 Mar 2018 01:35:05 PDT (-0700), z
On Wed, 14 Mar 2018 10:07:35 PDT (-0700), t...@linutronix.de wrote:
On Wed, 7 Mar 2018, Palmer Dabbelt wrote:
This converts the ARM port to use the recently added
GENERIC_IRQ_MULTI_HANDLER, which is essentially just a copy of ARM's
existhing MULTI_IRQ_HANDLER. The only change
On Wed, 14 Mar 2018 10:11:49 PDT (-0700), s...@shealevy.com wrote:
Palmer Dabbelt writes:
On Wed, 14 Mar 2018 05:07:09 PDT (-0700), s...@shealevy.com wrote:
Palmer Dabbelt writes:
On Tue, 13 Mar 2018 14:30:53 PDT (-0700), s...@shealevy.com wrote:
Hi Palmer,
Palmer Dabbelt writes:
On
On Tue, 25 Sep 2018 22:54:48 PDT (-0700), a...@brainfault.org wrote:
On Mon, Sep 17, 2018 at 7:58 PM Anup Patel wrote:
On Mon, Sep 17, 2018 at 7:44 PM Christoph Hellwig wrote:
>
> On Mon, Sep 10, 2018 at 10:08:58PM +0530, Anup Patel wrote:
> > > They could in theory IFF someone actually get t
The following changes since commit 6bf4ca7fbc85d80446ac01c0d1d77db4d91a6d84:
Linux 4.19-rc5 (2018-09-23 19:15:18 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git
tags/riscv-for-linus-4.19-rc6
for you to fetch changes up to
On Wed, 26 Sep 2018 01:31:09 PDT (-0700), zong...@gmail.com wrote:
This patches contain the modificaion as follows:
1. Fix up the building fail on RV32.
2. Add umoddi3 and udivmoddi4 functions for RV32.
3. Fix ioremap problem on RV32.
Changes in v2:
- Retain the copyright notices from libgcc in
d of direct access
RISC-V: Add logical CPU indexing for RISC-V
RISC-V: Use Linux logical CPU number instead of hartid
Palmer Dabbelt (7):
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
RISC-V: Filter ISA and MMU values in cpuinfo
RISC-V: Comment on the TLB flush in
On Mon, 17 Sep 2018 07:23:08 PDT (-0700), Christoph Hellwig wrote:
On Fri, Sep 14, 2018 at 02:54:55PM -0700, Atish Patra wrote:
Follow the updated DT specs and read the timebase-frequency
from the boot cpu. Keep the old DT reading as well for backward
compatibility. This patch is rework of old p
On Fri, 07 Sep 2018 13:29:03 PDT (-0700), robh...@kernel.org wrote:
On Fri, Sep 7, 2018 at 1:55 PM Paul Burton wrote:
The CONFIG_CMDLINE-related logic in early_init_dt_scan_chosen() falls
back to copying CONFIG_CMDLINE into boot_command_line/data if the DT has
a /chosen node but that node has
On Mon, 10 Sep 2018 06:46:59 PDT (-0700), Christoph Hellwig wrote:
On Fri, Sep 07, 2018 at 06:14:29PM +0530, Anup Patel wrote:
This patch provides arch_show_interrupts() implementation to
show IPI stats via /proc/interrupts.
Now the contents of /proc/interrupts" will look like below:
On Mon, 10 Sep 2018 06:34:18 PDT (-0700), Christoph Hellwig wrote:
On Thu, Sep 06, 2018 at 04:15:14PM +0530, Anup Patel wrote:
This patch is doing two things:
1. Allow IRQCHIP driver to provide IPI trigger mechanism
And the big questions is why do we want that? The last thing we
want is for p
On Wed, 12 Sep 2018 07:38:22 PDT (-0700), a...@brainfault.org wrote:
Currently, /proc/cpuinfo show logical CPU ID as Hart ID which
is in-correct. This patch shows CPU ID and Hart ID separately
in /proc/cpuinfo using cpuid_to_hardid_map().
With this patch, contents of /proc/cpuinfo looks as follo
dependent prepare_ftrace_return().
Have riscv use the new code, and remove the shadow stack management as well as
having to set up the trace structure.
This is needed to prepare for a fix of a design bug on how the curr_ret_stack
is used.
Cc: Greentime Hu
Cc: Alan Kao
Cc: Palmer Dabbel
Herring .
Cc: Rob Herring
Cc: Palmer Dabbelt
Cc: Megan Wachs
Cc: Wesley Terpstra
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: linux-ri...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Paul Walmsley
Signed-off-by: Paul Walmsley
---
Hi Rob, please let me know if
On Wed, 21 Nov 2018 17:06:56 PST (-0800), Paul Walmsley wrote:
For IP blocks that are generated from the public, open-source
sifive-blocks repository, describe the version numbering policy
that its maintainers intend to use, upon request from Rob
Herring .
Cc: Rob Herring
Cc: Palmer Dabbelt
On Fri, 16 Nov 2018 19:09:36 PST (-0800), Olof Johansson wrote:
On Thu, Nov 8, 2018 at 11:32 AM Palmer Dabbelt wrote:
On Thu, 08 Nov 2018 11:07:00 PST (-0800), david.abdurachma...@gmail.com wrote:
> Fixes warning: 'struct module' declared inside parameter list will not be
> vi
On Fri, 16 Nov 2018 19:32:04 PST (-0800), a...@brainfault.org wrote:
On Sat, Nov 17, 2018 at 2:43 AM Palmer Dabbelt wrote:
On Sun, 11 Nov 2018 21:55:15 PST (-0800), a...@brainfault.org wrote:
> This patch extends Linux RISC-V build system to build and install:
> Image - Flat uncomp
On Tue, 20 Nov 2018 06:11:02 PST (-0800), tiny.win...@gmail.com wrote:
use of_node_put() to release the refcount.
Signed-off-by: Yangtao Li
---
arch/riscv/kernel/time.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
index 1911c8f6b8a6..4
On Tue, 20 Nov 2018 21:06:18 PST (-0800), bmeng...@gmail.com wrote:
On Mon, Nov 12, 2018 at 1:55 PM Anup Patel wrote:
This patch extends Linux RISC-V build system to build and install:
Image - Flat uncompressed kernel image
Image.gz - Flat and GZip compressed kernel image
Quiet a few bootload
On Wed, 21 Nov 2018 01:53:50 PST (-0800), pet...@infradead.org wrote:
On Wed, Nov 21, 2018 at 09:19:36AM +0100, Peter Zijlstra wrote:
On Wed, Nov 21, 2018 at 09:39:00AM +0800, Li, Aubrey wrote:
> > Also; you were going to shop around with the other architectures to see
> > what they want/need fo
The following changes since commit ccda4af0f4b92f7b4c308d3acc262f4a7e3affad:
Linux 4.20-rc2 (2018-11-11 17:12:31 -0600)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git
tags/riscv-for-linus-4.20-rc2
for you to fetch changes up to
On Wed, 14 Nov 2018 16:27:55 PST (-0800), Olof Johansson wrote:
Sparse highlighted it, and appears to be a pure bug (from vs to).
./arch/riscv/include/asm/uaccess.h:403:35: warning: incorrect type in argument
1 (different address spaces)
./arch/riscv/include/asm/uaccess.h:403:39: warning: incor
On Fri, 09 Nov 2018 13:42:16 PST (-0800), m...@packi.ch wrote:
Removes the warning about an unsupported ISA when reading /proc/cpuinfo
on QEMU. The "S" extension is not being returned as it is not accessible
from userspace.
Signed-off-by: Patrick Stählin
---
arch/riscv/kernel/cpu.c | 9 ++-
On Sun, 11 Nov 2018 21:55:15 PST (-0800), a...@brainfault.org wrote:
This patch extends Linux RISC-V build system to build and install:
Image - Flat uncompressed kernel image
Image.gz - Flat and GZip compressed kernel image
Quiet a few bootloaders (such as Uboot, UEFI, etc) are capable of
bootin
On Fri, 16 Nov 2018 18:39:45 PST (-0800), Olof Johansson wrote:
On Thu, Nov 8, 2018 at 11:02 AM David Abdurachmanov
wrote:
Marcin Juszkiewicz reported issues while generating syscall table for riscv
using 4.20-rc1. The patch refactors our unistd.h files to match some other
architectures.
- Ad
On Sun, 11 Nov 2018 22:19:02 PST (-0800), david.abdurachma...@gmail.com wrote:
On Mon, Nov 12, 2018 at 5:10 AM Zong Li wrote:
The stat64 family that is used on 32-bit architectures to replace
newstat.
Since commit 67314ec7b0250290cc85eaa7a2f88a8ddb9e8547 ("RISC-V: Request
newstat syscalls"),
On Mon, 29 Oct 2018 05:15:16 PDT (-0700), david.abdurachma...@gmail.com wrote:
Depends on:
http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html
Why we don't have HAVE_SYSCALL_TRACEPOINTS in arch/riscv/Kconfig?
Signed-off-by: David Abdurachmanov
---
arch/riscv/kernel/ptrac
On Mon, 29 Oct 2018 03:48:53 PDT (-0700), david.abdurachma...@gmail.com wrote:
On RISC-V (riscv) audit is supported through generic lib/audit.c.
The patch adds required arch specific definitions.
Signed-off-by: David Abdurachmanov
---
arch/riscv/Kconfig | 1 +
arch/riscv/inc
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