This patch contains code to manage the RISC-V MMU, including definitions
of the page tables and the page walking code.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu_context.h | 69 ++
arch/riscv/include/asm/page.h | 134 +++
arch/riscv/include/asm/pgalloc.h
This patch contains the code that interfaces with ELF objects on RISC-V
systems, the vast majority of which is present to load kernel modules.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/compat.h | 29 ++
arch/riscv/include/asm/elf.h| 84
This patch contains code that is more specific to the RISC-V ISA than it
is to Linux. It contains string and math operations, C wrappers for
various assembly instructions, stack walking code, and uaccess.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm.h| 76
This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm-offsets.h | 1 +
arch/riscv/include/asm/current.h | 45
arch/riscv/include/asm/kprobes.h | 22 ++
arch/riscv
This patch contains code that interfaces with devices that are mandated
by the RISC-V supervisor specification and that don't have explicit
drivers anywhere else in the tree. This includes the staticly defined
interrupts, the CSR-mapped timer, and virtualized SBI devices.
Signed-off-by: Palmer
the hardware from the clocksource driver by taking a pair of
function pointers to issue the actual RISC-V specific instructions.
Signed-off-by: Palmer Dabbelt
---
drivers/clocksource/Kconfig | 8 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/riscv_timer.c | 64
This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system. When a file was
init-related this patch contains the entire file.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/bug.h | 88 ++
arch/riscv/include
This patch adds a driver for the Platform Level Interrupt Controller
(PLIC) specified as part of the RISC-V supervisor level ISA manual.
The PLIC connocts global interrupt sources to the local interrupt
controller on each hart. A PLIC is present on all RISC-V systems.
Signed-off-by: Palmer
controller). Per-hart local interrupt
controllers are found on all RISC-V systems.
Signed-off-by: Palmer Dabbelt
---
drivers/irqchip/Kconfig | 14 +++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-riscv-intc.c | 213 +++
3 files changed, 228
are
functionally identical to the various other copies. These are
availiable via Kconfig as CONFIG_GENERIC_$ROUTINE, which currently isn't
used anywhere.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Palmer Dabbelt
---
include/lib/libgcc.h | 44
Sorry, I missed this before submitting our v7. I'll respond properly in a
bit...
On Mon, 31 Jul 2017 04:00:26 PDT (-0700), daniel.lezc...@linaro.org wrote:
> On 11/07/2017 03:39, Palmer Dabbelt wrote:
>> The RISC-V ISA defines a per-hart real-time clock and timer, which is
>>
On Tue, 26 Sep 2017 23:08:02 PDT (-0700), Arnd Bergmann wrote:
> On Tue, Sep 26, 2017 at 6:56 PM, Palmer Dabbelt wrote:
>> As per suggestions on our v8 patch set, I've split the core architecture code
>> out from our drivers and would like to submit this patch set to be include
Signed-off-by: Palmer Dabbelt
---
arch/riscv/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 2c6adf12713a..02076f3a2883 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -10,7 +10,6 @@ config RISCV
select OF_IRQ
On Tue, 09 Jan 2018 00:11:45 PST (-0800), h...@lst.de wrote:
On Mon, Jan 08, 2018 at 05:27:56PM -0800, Palmer Dabbelt wrote:
During the glibc upstreaming it was suggested that CLONE_BACKWARDS was a
deprecated ABI decision. I think we just copied it from ARM, but I
don't see any reason to favor
.
Christoph Hellwig (2):
riscv: remove CONFIG_MMU ifdefs
riscv: rename SR_* constants to match the spec
Karsten Merker (1):
RISC-V: Add a basic defconfig
Palmer Dabbelt (1):
RISC-V: Make __NR_riscv_flush_icache
On Thu, 23 Nov 2017 00:03:18 PST (-0800), h...@lst.de wrote:
On Wed, Nov 22, 2017 at 08:50:25AM -0800, Palmer Dabbelt wrote:
On Wed, 22 Nov 2017 02:47:28 PST (-0800), h...@lst.de wrote:
Introducing a new include/lib directory just for this file totally
messes up tab completion for include
From: Palmer Dabbelt
We were hoping to avoid making this visible to userspace, but it looks
like we're going to have to because QEMU's user-mode emulation doesn't
want to emulate a vDSO. Having vDSO-only system calls was a bit
unothodox anyway, so I think in this case it's OK to just make
;
Before this patch:
[0.00] Kernel command line: root=/dev/vda ro root=/dev/vda ro
After this patch:
[0.00] Kernel command line: root=/dev/vda ro
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/setup.c | 16
1 file changed, 1
This is just some cruft left over from before the port converted to
device tree. The right way to handle memory regions is to specify them
in the device tree, which BBL (our simplest bootloader) is already
capable of doing. This patch simply removes the cruft.
Signed-off-by: Palmer Dabbelt
On Thu, 14 Dec 2017 10:21:16 PST (-0800), dhowe...@redhat.com wrote:
Stephen Rothwell wrote:
I'd be much happier if these patches had any Reviewd-by or Tested-by tags ...
They've now got:
Tested-by: Tony Luck
Tested-by: Will Deacon (arm64)
attached. I've also added
On Fri, 15 Dec 2017 00:36:37 PST (-0800), dhowe...@redhat.com wrote:
Palmer Dabbelt wrote:
Thanks! It works for me.
Excellent, thanks! Can I put you down as a Tested-by for riscv?
Sure.
Tested-by: Palmer Dabbelt
cleaner to use a 'u32 *' instead of
'void *' here, something more like this (which I haven't even compiled)
commit 2424a65ce079ecbe16fbedc704b88b6f04f8b97a
Author: Palmer Dabbelt
Date: Wed Dec 20 19:31:41 2017 -0800
void* -> u32* in PLIC
diff --git a/drivers/irqchip/irq-riscv-plic.c b/drive
On Mon, 18 Dec 2017 01:52:48 PST (-0800), noner...@gmail.com wrote:
This patch contains basic ftrace support for RV64I platform.
Specifically, function tracer (HAVE_FUNCTION_TRACER), function graph
tracer (HAVE_FUNCTION_GRAPH_TRACER), and a frame pointer test
(HAVE_FUNCTION_GRAPH_FP_TEST) are
On Wed, 20 Dec 2017 01:14:31 PST (-0800), zong...@gmail.com wrote:
Build the dtb into the kernel image.
If the DTB is given via bootloader, the external DTB is adopted first.
Signed-off-by: Zong Li
---
arch/riscv/Kconfig | 4
arch/riscv/Makefile | 9 +
On Thu, 21 Dec 2017 12:43:20 PST (-0800), Arnd Bergmann wrote:
On Thu, Dec 21, 2017 at 9:32 PM, Palmer Dabbelt wrote:
On Wed, 20 Dec 2017 01:14:31 PST (-0800), zong...@gmail.com wrote:
I've added Arnd and Olof, in case they have a bit more perspective here. If
I'm reading this correctly
I'd like to request that you add the following tree to linux-next
git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git for-linux-next
It contains the RISC-V port, which has been through 9 rounds of review on
various public Linux mailing lists. While the port isn't perfect, I've
is was necessary because thread_info is no longer on
the stack.
* A few shared routines have been added that we use instead of creating
another arch copy.
Jonathan Neuschäfer (1):
MAINTAINERS: Add RISC-V
Palmer Dabbelt
On Tue, 14 Nov 2017 01:04:42 PST (-0800), Arnd Bergmann wrote:
> On Mon, Nov 13, 2017 at 10:56 PM, Palmer Dabbelt wrote:
>> The following changes since commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4:
>>
>> Linux 4.14 (2017-11-12 10:46:13 -0800)
>>
>> ar
On Tue, 14 Nov 2017 11:23:08 PST (-0800), will.dea...@arm.com wrote:
Hi Palmer,
On Mon, Nov 13, 2017 at 01:56:22PM -0800, Palmer Dabbelt wrote:
The following changes since commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4:
Linux 4.14 (2017-11-12 10:46:13 -0800)
are available in the git
lose the message again
the code contained here has been minimally tested. All the commits live on a
branch now, so hopefully I won't lose it this time :).
On Tue, Sep 26, 2017 at 06:56:31PM -0700, Palmer Dabbelt wrote:
This contains all the code that directly interfaces with the RISC-V
memory
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/spinlock.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/arch/riscv/include/asm/spinlock.h
b/arch/riscv/include/asm/spinlock.h
index b3b394ffaf7e..7e06eee8f256 100644
--- a/arch/riscv/include/asm/spinlock.h
+++ b/arch/riscv/include/asm/
On Wed, 08 Nov 2017 21:53:52 PST (-0800), luc.vanoostenr...@gmail.com wrote:
> The goal of these two patches is to ass endianness and machine
> size info to sparse so that sparse can emit correct diagnostics
> even when the endianness and machine size doesn't correspond to
> sparse's defaults.
>
>
On Thu, 09 Nov 2017 13:46:50 PST (-0800), luc.vanoostenr...@gmail.com wrote:
> On Thu, Nov 9, 2017 at 10:36 PM, Palmer Dabbelt wrote:
>> On Wed, 08 Nov 2017 21:53:52 PST (-0800), luc.vanoostenr...@gmail.com wrote:
>>> The goal of these two patches is to ass endianness and mac
These were left over from an earlier version of the port.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/vdso/vdso.lds.S | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/riscv/kernel/vdso/vdso.lds.S
b/arch/riscv/kernel/vdso/vdso.lds.S
index 8c9dce95c11d..3ac08eebd11d 100644
will be taken before anything
runs on it.
Signed-off-by: Andrew Waterman
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/cacheflush.h | 24 ---
arch/riscv/include/asm/mmu.h | 4 +++
arch/riscv/include/asm/mmu_context.h | 44 +++
arch/riscv
off-by: Andrew Waterman
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/cacheflush.h| 6 ++
arch/riscv/include/asm/vdso-syscalls.h | 28
arch/riscv/include/asm/vdso.h | 4
arch/riscv/kernel/sys_riscv.c |
-by: Palmer Dabbelt
---
arch/riscv/kernel/vdso/Makefile| 6 +-
arch/riscv/kernel/vdso/clock_getres.S | 26 ++
arch/riscv/kernel/vdso/clock_gettime.S | 26 ++
arch/riscv/kernel/vdso/getcpu.S| 26 ++
arch/riscv
This patch set contains all the user-visible ABI changes that we currently know
about. There might be a few more as we get through the glibc upstreaming
process, though. Most of the changes are pretty minor:
* Some VDSO symbols that weren't defined were versioned, which doesn't make any
On Sun, 19 Nov 2017 23:35:28 PST (-0800), j.neuschae...@gmx.net wrote:
Hi Palmer,
On Thu, Oct 05, 2017 at 11:16:33AM +0100, Mark Rutland wrote:
[...]
I would *strongly* recommend that from day one, you determine the SMP
bringup mechanism via an enable-method property, and document the
contract
The RISC-V privileged ISA mandates the presence of an SBI, but there's
no reason not to put it in the device tree. This would allow us to
possibly remove the SBI later.
CC: Jonathan Neuschäfer
Signed-off-by: Palmer Dabbelt
---
.../devicetree/bindings/firmware/riscv.sbi.txt | 20
y only has the value "none". This allows us to change the
enable method in the future.
CC: Mark Rutland
Signed-off-by: Palmer Dabbelt
---
Documentation/devicetree/bindings/riscv/cpus.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindin
On Mon, 20 Nov 2017 12:28:56 PST (-0800), j.neuschae...@gmx.net wrote:
On Mon, Nov 20, 2017 at 11:50:00AM -0800, Palmer Dabbelt wrote:
The RISC-V privileged ISA mandates the presence of an SBI, but there's
no reason not to put it in the device tree. This would allow us to
possibly remove
On Tue, 01 Aug 2017 06:06:20 PDT (-0700), andriy.shevche...@linux.intel.com
wrote:
> On Mon, 2017-07-31 at 17:59 -0700, Palmer Dabbelt wrote:
>> Many ports (m32r, microblaze, mips, parisc, score, and sparc) use
>> functionally identical copies of various GCC library routine files
On Wed, 13 Sep 2017 09:15:39 PDT (-0700), Arnd Bergmann wrote:
> On Tue, Sep 12, 2017 at 11:56 PM, Palmer Dabbelt wrote:
>> I know it may not be the ideal time to submit a patch set right now, as it's
>> the middle of the merge window, but things have calmed down quite a bit in
On Wed, 13 Sep 2017 09:06:03 PDT (-0700), Arnd Bergmann wrote:
> On Tue, Sep 12, 2017 at 11:57 PM, Palmer Dabbelt wrote:
>> This patch contains all the build infrastructure that actually enables
>> the RISC-V port. This includes Makefiles, linker scripts, and Kconfig
>> fil
On Fri, 15 Sep 2017 07:34:33 PDT (-0700), r...@kernel.org wrote:
> On Tue, Sep 12, 2017 at 4:57 PM, Palmer Dabbelt wrote:
>> This patch adds documentation for the platform-level interrupt
>> controller (PLIC) found in all RISC-V systems. This interrupt
>> controller route
On Tue, 03 Apr 2018 05:56:18 PDT (-0700), Arnd Bergmann wrote:
On Tue, Apr 3, 2018 at 2:44 PM, Sinan Kaya wrote:
On 4/3/2018 7:13 AM, Arnd Bergmann wrote:
On Tue, Apr 3, 2018 at 12:49 PM, Mark Rutland wrote:
Hi,
On Fri, Mar 30, 2018 at 11:58:13AM -0400, Sinan Kaya wrote:
The default
-by: Matt Redfearn
Reviewed-by: Palmer Dabbelt
---
Changes in v5: None
Changes in v4:
Rename Kconfig symbols GENERIC_* -> GENERIC_LIB_*
Changes in v3: None
Changes in v2: None
arch/riscv/Kconfig | 6 +++---
lib/Kconfig| 12 ++--
lib/Makefile | 12 ++--
3 fi
On Tue, 03 Apr 2018 05:03:56 PDT (-0700), t...@linutronix.de wrote:
Palmer Dabbelt (2):
genirq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER
RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler
Oh, sorry, I must have screwed something up here. I attempted to send out a v4
On Tue, 03 Apr 2018 06:51:06 PDT (-0700), matt.redfe...@mips.com wrote:
Hi Palmer,
On 29/03/18 22:59, Palmer Dabbelt wrote:
On Thu, 29 Mar 2018 03:41:21 PDT (-0700), matt.redfe...@mips.com wrote:
From: Palmer Dabbelt
As part of the MIPS conversion to use the generic GCC library routines
On Tue, 03 Apr 2018 07:45:45 PDT (-0700), jho...@kernel.org wrote:
On Tue, Apr 03, 2018 at 02:51:06PM +0100, Matt Redfearn wrote:
On 29/03/18 22:59, Palmer Dabbelt wrote:
> Ah, thanks, I think I must have forgotten about this. I assume these
> three are going through your tree?
Yeah I
On Tue, 03 Apr 2018 17:27:41 PDT (-0700), Linus Torvalds wrote:
On Tue, Apr 3, 2018 at 3:39 PM, Palmer Dabbelt wrote:
I assume it's too late to swap this out for that? If so that's OK, I can
just send a follow-on.
Sorry for breaking things!
Thomas,
I'll delay pulling your trees until
arm has an optional MULTI_IRQ_HANDLER, which arm64 copied but didn't
make optional. I'm converting this to generic code, but in order to aid
the porting effort I want to define this on arm64 for a bit. This will
go away at the end of this patch set.
Signed-off-by: Palmer Dabbelt
---
arch
On Tue, 03 Apr 2018 19:03:28 PDT (-0700), Linus Torvalds wrote:
> On Tue, Apr 3, 2018 at 6:51 PM, Palmer Dabbelt wrote:
>>
>> Thanks! The linked patch set should be fully bisectable, while this one
>> will fail on some ARM randconfigs.
>
> If it's only some (not ver
arm has an optional MULTI_IRQ_HANDLER, which arm64 copied but didn't
make optional. I'm converting this to generic code, but in order to aid
the porting effort I want to define this on arm64 for a bit. This will
go away at the end of this patch set.
Signed-off-by: Palmer Dabbelt
---
arch
.
This will go away when every port is converted over to
GENERIC_IRQ_MULTI_HANDLER.
Signed-off-by: Palmer Dabbelt
---
kernel/irq/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig
index 5f3e2baefca9..c6766f326072 100644
--- a/kernel/irq/Kconfig
+++ b
On Wed, 04 Apr 2018 03:19:54 PDT (-0700), t...@linutronix.de wrote:
On Tue, 3 Apr 2018, Linus Torvalds wrote:
On Tue, Apr 3, 2018 at 6:51 PM, Palmer Dabbelt wrote:
>
> Thanks! The linked patch set should be fully bisectable, while this one
> will fail on some ARM randconfigs.
If
):
riscv/barrier: Define __smp_{store_release,load_acquire}
riscv/spinlock: Strengthen implementations with fences
riscv/atomic: Strengthen implementations with fences
Palmer Dabbelt (4):
RISC-V: Add dynamic ftrace support for RISC-V platforms
RISC-V: Assorted memory model
On Wed, 04 Apr 2018 15:02:58 PDT (-0700), jho...@kernel.org wrote:
On Tue, Apr 03, 2018 at 03:39:34PM -0700, Palmer Dabbelt wrote:
Sorry, I'm not sure if this is the right patch -- someone suggested acking
this, but it's already Review-By me and if I understand correctly it's going
through
On Wed, 04 Apr 2018 22:02:29 PDT (-0700), alan...@andestech.com wrote:
On Tue, Apr 03, 2018 at 03:45:17PM -0700, Palmer Dabbelt wrote:
On Tue, 03 Apr 2018 07:29:02 PDT (-0700), alan...@andestech.com wrote:
>On Mon, Apr 02, 2018 at 08:15:44PM -0700, Palmer Dabbelt wrote:
>>On Mon, 02 Ap
On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alan...@andestech.com wrote:
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
On Wed, 18 Apr 2018 04:10:16 PDT (-0700), s...@shealevy.com wrote:
Hi all,
Shea Levy writes:
This function is effectively identical across 14 architectures, and
the generic implementation is small enough to be negligible in the
architectures that do override it. Many of the remaining
On Mon, 09 Apr 2018 00:07:11 PDT (-0700), alan...@andestech.com wrote:
On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote:
On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alan...@andestech.com wrote:
>This patch provide a basic PMU, riscv_base_pmu, which supports two
>general ha
On Tue, 10 Apr 2018 09:09:32 PDT (-0700), wi...@infradead.org wrote:
On Tue, Apr 10, 2018 at 05:25:50PM +0200, Laurent Dufour wrote:
arch/powerpc/include/asm/pte-common.h | 3 ---
arch/riscv/Kconfig | 1 +
arch/s390/Kconfig
the calling function clearer.
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc: linux-ri...@lists.infradead.org
Signed-off-by: "Eric W. Biederman"
---
arch/riscv/kernel/traps.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kern
On Sun, 22 Apr 2018 05:53:56 PDT (-0700), s...@shealevy.com wrote:
Hi Palmer,
Shea Levy writes:
Signed-off-by: Shea Levy
---
Note that this patch worked in my old modules patchset and seems to be
working now, but my kernel boot locks up on top of
riscv-for-linus-4.17-mw0 and I don't know
shim does not initialize PCI bus */
#define pcibios_assign_all_busses() 1
-/* We do not have an IOMMU */
-#define PCI_DMA_BUS_IS_PHYS 1
-
extern int isa_dma_bridge_buggy;
#ifdef CONFIG_PCI
Thanks!
Acked-by: Palmer Dabbelt (For the RISC-V change)
On Tue, 24 Apr 2018 12:27:26 PDT (-0700), atish.pa...@wdc.com wrote:
On 4/24/18 11:07 AM, Atish Patra wrote:
On 4/19/18 4:28 PM, Alan Kao wrote:
This implements the baseline PMU for RISC-V platforms.
To ease future PMU portings, a guide is also written, containing
perf concepts, arch porting
On Tue, 24 Apr 2018 15:16:16 PDT (-0700), atish.pa...@wdc.com wrote:
On 4/24/18 12:44 PM, Palmer Dabbelt wrote:
On Tue, 24 Apr 2018 12:27:26 PDT (-0700), atish.pa...@wdc.com wrote:
On 4/24/18 11:07 AM, Atish Patra wrote:
On 4/19/18 4:28 PM, Alan Kao wrote:
However, I got an rcu-stall
On Mon, 02 Apr 2018 00:17:30 PDT (-0700), Arnd Bergmann wrote:
- openrisc, risc-v and nds32 are still in the process of finishing their
support or getting it added to mainline gcc in the first place.
They all have patched gcc-7.3 ports that work to some degree, but
complete upstream
On Mon, 02 Apr 2018 05:31:22 PDT (-0700), alan...@andestech.com wrote:
This implements the baseline PMU for RISC-V platforms.
To ease future PMU portings, a guide is also written, containing
perf concepts, arch porting practices and some hints.
Changes in v2:
- Fix the bug reported by Alex,
spin_lock(s);
r1 = READ_ONCE(*x);
}
exists (1:r0=1 /\ 1:r1=0)
[1] https://marc.info/?l=linux-kernel=151930201102853=2
https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkAXM
https://marc.info/?l=linux-kernel=151633436614259=2
Signed-off-by: Andrea
On Wed, 07 Mar 2018 02:52:42 PST (-0800), parri.and...@gmail.com wrote:
On Tue, Mar 06, 2018 at 06:02:28PM -0800, Palmer Dabbelt wrote:
On Mon, 05 Mar 2018 10:24:09 PST (-0800), parri.and...@gmail.com wrote:
>Current implementations map locking operations using .rl and .aq
>annot
MULTI_IRQ_HANDLER instead.
Reviewed-by: Christoph Hellwig
Signed-off-by: Palmer Dabbelt
---
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/irq.h | 2 --
arch/arm64/kernel/irq.c | 10 --
3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64
is not marked as __ro_after_init.
Signed-off-by: Palmer Dabbelt
---
arch/arm/Kconfig | 19 +++
arch/arm/include/asm/irq.h | 5 -
arch/arm/include/asm/mach/arch.h | 2 +-
arch/arm/kernel/entry-armv.S | 10 ++
arch/arm/kernel/irq.c| 10
It appears that openrisc copied arm64's GENERIC_IRQ_MULTI_HANDLER code
(which came from arm). I wanted to make this generic so I could use it
in the RISC-V port. This patch converts the openrisc code to use the
generic version.
Acked-by: Stafford Horne
Signed-off-by: Palmer Dabbelt
---
arch
an additional
load to the interrupt latency, but there's a lot of tuning left to be
done there on RISC-V so I think it's OK for now.
Reviewed-by: Christoph Hellwig
Acked-by: Stafford Horne
Signed-off-by: Palmer Dabbelt
---
arch/riscv/Kconfig| 1 +
arch/riscv/include/asm/Kbuild | 1
This is my third version of this patch set, but the original cover
letter is still the most relevant description I can come up with.
This patch set has been sitting around for a while, but it got a bit lost
in the shuffle. In RISC-V land we currently couple do_IRQ (the C entry
point
into
kernel/irq under CONFIG_GENERIC_MULTI_IRQ_HANDLER. This patch is
currently all dead code, but it will be enabled in the various other
architectures in subsequent patches.
Signed-off-by: Palmer Dabbelt
---
include/linux/irq.h | 18 ++
kernel/irq/Kconfig | 5 +
kernel/irq
On Tue, 20 Feb 2018 18:45:39 PST (-0800), alan...@andestech.com wrote:
On Tue, Feb 13, 2018 at 01:13:15PM +0800, Alan Quey-Liang Kao(高魁良) wrote:
This patch set includes the building blocks of dynamic ftrace features
for RISC-V machines.
Changes in v4:
- Organize code structure according to
On Mon, 26 Feb 2018 02:35:52 PST (-0800), parri.and...@gmail.com wrote:
On Thu, Feb 22, 2018 at 03:14:52PM -0800, Palmer Dabbelt wrote:
On Tue, 20 Feb 2018 02:17:28 PST (-0800), parri.and...@gmail.com wrote:
>Introduce __smp_{mb,rmb,wmb}, and rely on the generic definitions
>for smp_{mb,r
On Mon, 26 Feb 2018 18:24:11 PST (-0800), parri.and...@gmail.com wrote:
Introduce __smp_{store_release,load_acquire}, and rely on the generic
definitions for smp_{store_release,load_acquire}. This avoids the use
of full ("rw,rw") fences on SMP.
Signed-off-by: Andrea Parri
---
On Thu, 08 Feb 2018 14:54:46 PST (-0800), ulfali...@gmail.com wrote:
The RISCV_IRQ_INTC configuration symbol is undefined, but RISCV selects
it. Quoting Palmer Dabbelt:
It looks like this slipped through, the symbol has been renamed
RISCV_INTC.
No RISCV_INTC configuration
-by: Matt Redfearn
Thanks! Do you want me to take this in my tree?
Reviewed-by: Palmer Dabbelt
---
arch/riscv/Kconfig | 6 +++---
lib/Kconfig| 12 ++--
lib/Makefile | 12 ++--
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/Kconfig
properties. That change
helps to clarify its one remaining use (matching
cacheinfo nodes that represent shared caches) which
will be used by the ACPI/PPTT code in the following patches.
Cc: Palmer Dabbelt
Cc: Albert Ou
Signed-off-by: Jeremy Linton
---
arch/riscv/kernel/cacheinfo.c | 1 +
drivers/base
On Tue, 13 Feb 2018 14:49:37 PST (-0800), jho...@kernel.org wrote:
On Tue, Feb 13, 2018 at 01:48:18PM -0800, Palmer Dabbelt wrote:
On Fri, 09 Feb 2018 05:22:52 PST (-0800), matt.redfe...@mips.com wrote:
> When these are included into arch Kconfig files, maintaining
> alphabetical or
On Wed, 07 Jun 2017 06:17:27 PDT (-0700), pet...@infradead.org wrote:
> On Tue, Jun 06, 2017 at 04:00:03PM -0700, Palmer Dabbelt wrote:
>> diff --git a/arch/riscv/include/asm/spinlock.h
>> b/arch/riscv/include/asm/spinlock.h
>> new file mode 100644
>> index 000
On Wed, 07 Jun 2017 05:58:50 PDT (-0700), pet...@infradead.org wrote:
> On Wed, Jun 07, 2017 at 02:36:27PM +0200, Peter Zijlstra wrote:
>> Which (pending the sub confusion) will generate the entire set of:
>>
>> atomic_add, atomic_add_return{_relaxed,_acquire,_release,}
>>
On Wed, 07 Jun 2017 06:16:11 PDT (-0700), will.dea...@arm.com wrote:
> [sorry, jumping in here because it's the only mail I have relating to
> patch 13]
>
> On Wed, Jun 07, 2017 at 02:58:50PM +0200, Peter Zijlstra wrote:
>> On Wed, Jun 07, 2017 at 02:36:27PM +0200, Peter Zijlstra wrote:
>> >
elp improve the system]
>>
>> url:
>> https://github.com/0day-ci/linux/commits/Palmer-Dabbelt/pci-Add-and-use-PCI_GENERIC_SETUP-Kconfig-entry/20170626-043558
>> config: m68k-allnoconfig (attached as .config)
>> compiler: m68k-linux-gcc (GCC) 4.9.0
>> repro
with the patch applied.
The intention is that this patch doesn't change the behavior of any
build.
Signed-off-by: Palmer Dabbelt
Reviewed-by: James Hogan
Acked-by: Russell King
Acked-by: Richard Henderson
Acked-by: Vineet Gupta[arch/arc]
---
arch/alpha/Kconfig | 1 +
arch/arc/Kconfig
locksource folks
>
> Thanks Geert.
>
>> On Wed, Jun 7, 2017 at 12:59 AM, Palmer Dabbelt wrote:
>> > The RISC-V ISA defines a single RTC as well as an SBI oneshot timer.
>> > This timer is present on all RISC-V systems.
>
> As it is a new driver, please give a d
On Fri, 09 Jun 2017 06:47:48 PDT (-0700), will.dea...@arm.com wrote:
> On Wed, Jun 07, 2017 at 11:52:10AM +0100, Marc Zyngier wrote:
>> On 07/06/17 00:00, Palmer Dabbelt wrote:
>> > +static void plic_disable(struct plic_data *data, int i, int hwirq)
>> > +{
>>
The RISC-V ISA defines a simple console that is availiable via SBI calls
on all systems. This patch adds a driver for this console interface
that can act as both a target for early printk and as the system
console.
Signed-off-by: Palmer Dabbelt
---
drivers/tty/hvc/Kconfig | 11
This patch set contains two interrupt controller drivers for RISC-V systems:
the local interrupt controller is a per-hart controller, and the PLIC is a
per-chip controller.
This patch adds a driver for the Platform Level Interrupt Controller
(PLIC) specified as part of the RISC-V supervisor level ISA manual.
The PLIC connocts global interrupt sources to the local interrupt
controller on each hart. A PLIC is present on all RISC-V systems.
Signed-off-by: Palmer
controller). Per-hart local interrupt
controllers are found on all RISC-V systems.
Signed-off-by: Palmer Dabbelt
---
drivers/irqchip/Kconfig | 14 +++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-riscv-intc.c | 239 +++
3 files changed, 254
As part of submitting the RISC-V Linux port it was suggested that we write some
documentation that describes our device tree bindings. Our port is still in
progress, but it was suggested that we start sending patches to the relevant
parties. There is one outstanding issue to resolve with the
This patch adds documentation on the RISC-V local interrupt controller,
which is a per-hart interrupt controller that manages all interrupts
entering a RISC-V hart. This interrupt controller is present on all
RISC-V systems.
Signed-off-by: Palmer Dabbelt
---
.../interrupt-controller/riscv,cpu
might
want to change how we're specifying holes in the hart list.
Signed-off-by: Palmer Dabbelt
---
.../bindings/interrupt-controller/riscv,plic0.txt | 63 ++
1 file changed, 63 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/riscv
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