On 09/25/2013 08:00 AM, Pavel Machek wrote:
> Hi!
>
The firmware approach is interesting. It might be less flexible
compared with my original code (see link to git below) that this is
>>>
>>> On the other hand... that's the interface world wants, right? To most
>>> users, fpga bitstream
number
of parties that are interested in having reprogrammable logic available in
Linux and that will want to merge their drivers. I'm aware of these other
people that must have some interest (and one person I can't mention here
because of NDA):
Philip Balister (OpenSDR)
Dinh Nguyen (A
On 12/01/2012 08:56 AM, Greg KH wrote:
On Fri, Nov 30, 2012 at 07:19:16PM -0800, Philip Balister wrote:
On 11/30/2012 09:36 AM, Greg KH wrote:
On Fri, Nov 30, 2012 at 05:28:47PM +, Arnd Bergmann wrote:
On Wednesday 28 November 2012, Eli Billauer wrote:
Xillybus is a general-purpose
On 12/01/2012 12:48 PM, Arnd Bergmann wrote:
On Saturday 01 December 2012, Philip Balister wrote:
On 11/30/2012 09:36 AM, Greg KH wrote:
Yes, I know of at least one more device other than the ones listed above
that wants this type of functionality as well, so defining it in a
standard user
On 05/14/2013 12:46 PM, Mike Turquette wrote:
Quoting Sören Brinkmann (2013-05-13 10:58:49)
On Mon, May 13, 2013 at 07:37:23PM +0200, Sebastian Hesselbarth wrote:
On 05/13/13 19:24, Sören Brinkmann wrote:
On Mon, May 13, 2013 at 06:21:13PM +0200, Sebastian Hesselbarth wrote:
Well, that driver
On 05/16/2013 12:28 AM, Saravana Kannan wrote:
> On 05/14/2013 09:46 PM, Mark Brown wrote:
>> On Tue, May 14, 2013 at 02:09:47PM -0400, Philip Balister wrote:
>>
>>> First of all, the driver that loads the bitstream into the fpga
>>> fabric does not know ANYTHING
On 01/16/2014 12:53 PM, Srikanth Thokala wrote:
This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type video target peripherals. The core provides efficient tw
On 06/25/2014 11:43 AM, H. Peter Anvin wrote:
> On 06/25/2014 11:37 AM, Alan Tull wrote:
>>
>> Yes, that's why I've recently felt more love for the firmware
>> interface. Since I need resume, it gives me a straightforward path to
>> be able to reprogram the FPGA without holding ram for the bitfile
from making that happen. So yes, running
> mainline is a usecase that matters to me.
>
> It is one thing to keep bitching about vendor kernels as a community
> continuously, but then if someone goes through the effort and actually
> tries to run mainline, you give them crap l
On 09/26/2017 02:06 PM, Michal Simek wrote:
> On 26.9.2017 19:58, Philip Balister wrote:
>> On 09/26/2017 01:50 PM, Moritz Fischer wrote:
>>> Michal,
>>>
>>> On Tue, Sep 26, 2017 at 02:54:48PM +0200, Michal Simek wrote:
>>>> Hi,
>>>>
&g
On 10/06/2017 04:49 AM, Michal Simek wrote:
> On 26.9.2017 20:15, Philip Balister wrote:
>> On 09/26/2017 02:06 PM, Michal Simek wrote:
>>> On 26.9.2017 19:58, Philip Balister wrote:
>>>> On 09/26/2017 01:50 PM, Moritz Fischer wrote:
>>>>> Michal,
&
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