On 12/18/2015 09:14 PM, Rob Herring wrote:
> On Mon, Dec 14, 2015 at 03:42:05PM -0700, Joshua Henderson wrote:
>> From: Purna Chandra Mandal <purna.man...@microchip.com>
>>
>> Document the devicetree bindings for the clock driver found on Microchip
>> PIC3
y.h...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: linux-m...@linux-mips.org
Cc: Joshua Henderson <digitalp...@digitalpeer.com>
Reported-by: Harvey Hunt <harvey.h...@imgtec.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Reviewed-by: Harve
On 06/02/2016 02:45 PM, Harvey Hunt wrote:
> Hi Purna,
>
> On 02/06/16 06:20, Purna Chandra Mandal wrote:
>> Early clock API pic32_get_pbclk() is defined in early_clk.c and
>> used by time.c and early_console.c. When CONFIG_EARLY_PRINTK isn't
>> set, early_clk.c isn
On 06/02/2016 03:25 AM, Stephen Boyd wrote:
> This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate
> CLK_IS_ROOT", 2016-02-02) so remove it.
>
> Cc: Purna Chandra Mandal <purna.man...@microchip.com>
> Cc: Ralf Baechle <r...@linux-mips.org>
>
On 05/25/2016 09:32 PM, Harvey Hunt wrote:
> Hi Purna,
>
> On 17/05/16 06:05, Purna Chandra Mandal wrote:
>> PIC32 clock driver is now implemented as platform driver instead of
>> as part of of_clk_init(). It meants all the clock modules are available
>> quite late in th
in
alphabetical order.
Cc: Harvey Hunt <harvey.h...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: linux-m...@linux-mips.org
Cc: Joshua Henderson <digitalp...@digitalpeer.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
arch/mips/pic32/pic32mz
Thanks Mark.
On 02/02/2016 04:47 AM, Mark Brown wrote:
> On Mon, Feb 01, 2016 at 03:39:23PM -0700, Joshua Henderson wrote:
>> From: Purna Chandra Mandal <purna.man...@microchip.com>
>> There is a BUG in the way SPI_MASTER_MUST_RX/TX is implemented which can
>> crea
On 02/02/2016 04:41 PM, Sergei Shtylyov wrote:
> Hello.
> On 2/2/2016 1:44 AM, Joshua Henderson wrote:
>> From: Purna Chandra Mandal <purna.man...@microchip.com>
>> Document the devicetree bindings for the SPI peripheral found
>> on Microchip PIC32 class devices.
&
Hi Mark,
On 02/02/2016 05:43 PM, Mark Brown wrote:
> On Mon, Feb 01, 2016 at 03:44:57PM -0700, Joshua Henderson wrote:
>
>> The PIC32 SPI driver is capable of performing SPI transfers either using
>> polling or based on interrupt-trigger. GPIO based CS support (necessary
>> for correct SPI
On 02/05/2016 07:02 PM, Sergei Shtylyov wrote:
> Hello.
> On 2/5/2016 8:08 AM, Purna Chandra Mandal wrote:
>>>> From: Purna Chandra Mandal <purna.man...@microchip.com>
>>>> Document the devicetree bindings for the SPI peripheral found
>>>> o
On 01/30/2016 05:28 AM, Stephen Boyd wrote:
> On 01/13, Joshua Henderson wrote:
>> diff --git a/drivers/clk/clk-pic32.c b/drivers/clk/clk-pic32.c
>> new file mode 100644
>> index 000..9dc5f78
>> --- /dev/null
>> +++ b/drivers/clk/clk-pic32.c
>> @@ -0,0
On 02/20/2016 01:46 AM, Michael Turquette wrote:
> Quoting Joshua Henderson (2016-02-19 08:25:35)
>> +const struct clk_ops pic32_roclk_ops = {
>> + .enable = roclk_enable,
>> + .disable= roclk_disable,
>> + .is_enabled =
On 04/07/2016 06:42 PM, Sergei Shtylyov wrote:
> On 4/7/2016 4:02 PM, Purna Chandra Mandal wrote:
>
>>>> Document devicetree binding for the USB controller
>>>
>>> Device tree.
>>>
>> ack.
>>
>>>> and USB Phy found on Micro
On 04/07/2016 07:04 PM, Sergei Shtylyov wrote:
> On 4/7/2016 3:32 PM, Purna Chandra Mandal wrote:
>
>> Document devicetree binding for the USB controller
>> and USB Phy found on Microchip PIC32 class devices.
>>
>> Signed-off-by: Purna Chandra Mand
On 04/07/2016 06:09 PM, Felipe Balbi wrote:
> Purna Chandra Mandal <purna.man...@microchip.com> writes:
>> From: Cristian Birsan <cristian.bir...@microchip.com>
>>
>> This driver adds support of PIC32 MUSB OTG controller as
>> dual role device. It implem
On 04/07/2016 06:23 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 4/7/2016 2:16 PM, Purna Chandra Mandal wrote:
>
>> Document devicetree binding for the USB controller
>
>Device tree.
>
ack.
>> and USB Phy found on Microchip PIC32 class devices.
>
>
From: Cristian Birsan <cristian.bir...@microchip.com>
This driver adds support of PIC32 MUSB OTG controller as
dual role device. It implements platform specific glue to
reuse musb core.
Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Manda
Document devicetree binding for the USB controller
and USB Phy found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v2: None
.../bindings/usb/microchip,pic32-musb.txt | 67 ++
1 file chang
From: Cristian Birsan <cristian.bir...@microchip.com>
This driver adds support of PIC32 MUSB OTG controller as
dual role device. It implements platform specific glue to
reuse musb core.
Signed-off-by: Cristian Birsan <cristian.bir...@microchip.com>
Signed-off-by: Purna Chandra Manda
Document devicetree binding for the USB controller
and USB Phy found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
.../bindings/usb/microchip,pic32-musb.txt | 67 ++
1 file changed, 67 insertions(+)
Document Device tree bindings for quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Cc: Rob Herring <robh...@kernel.org>
Cc: Mark Brown <broo...@kernel.org>
---
Documentation/devicetree/bindings/spi/
This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA to perform half-duplex
communication on SPI bus for single, dual and quad-lane
SPI transactions.
Signed-off-by: Purna Chandra Mandal <purna.
On 04/11/2016 08:40 PM, Rob Herring wrote:
> On Thu, Apr 07, 2016 at 06:02:59PM +0530, Purna Chandra Mandal wrote:
>> Document devicetree binding for the USB controller
>> and USB Phy found on Microchip PIC32 class devices.
>>
>> Signed-off-by: Purna Chandra Mandal
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v4:
- report error and bailout in case of missing irq(s).
- remove fallback to PIO mode in case of failure in DMA transfer.
- remove polling based PIO completely.
- drop spinlock
- update error message and comments
Document the devicetree bindings for the SPI peripheral found
on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- fix indentation
This clock driver implements PIC32 specific clock-tree. clock-tree
entities can only be configured through device-tree file (OF).
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Note: Please pull this complete series through the MIPS tree.
---
Changes in v10:
.
Purna Chandra Mandal (3):
dt/bindings: Add PIC32 clock binding documentation
clk: microchip: Add PIC32 clock driver
MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding
.../devicetree/bindings/clock/microchip,pic32.txt | 39 +
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Note: Please pull this complete series through the MIPS tree.
---
C
Document the devicetree bindings for the clock driver found on Microchip
PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Michael Turquette <mturque...@baylibre.com>
Note: Please pull th
Hi Michael,
Ping! Need an ack for this or pull it upstream.
DT bindings have long been acked.
Purna
On 02/25/2016 11:37 PM, Joshua Henderson wrote:
> From: Purna Chandra Mandal <purna.man...@microchip.com>
>
> This clock driver implements PIC32 specific clock-tree. clock-tree
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v2:
- fix indentation
- add space after comma
- moved 'cs-gpios' section under 'required' properties.
.../bindings/spi/microchip,spi-pic32.txt | 34 ++
1 file changed, 34 inse
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v2:
- fix indentation
- add space after comma
- moved 'cs-gpios' section under 'required' properties.
.../bindings/spi/microchip,spi-pic32.txt | 34 ++
1 file changed, 34 inse
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v3:
- drop 'owner' field in driver struct.
- fix compilation warning in dma_addr_t print.
Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort include
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v3: None
Changes in v2:
- fix indentation
- add space after comma
- moved 'cs-gpios' section under 'required' properties.
.../bindings/spi/microchip,s
Mark,
On 02/08/2016 09:45 PM, Mark Brown wrote:
> On Fri, Feb 05, 2016 at 10:30:24AM +0530, Purna Chandra Mandal wrote:
>
> Please fix your mail client to word wrap within paragraphs at something
> substantially less than 80 columns. Doing this makes your messages much
>
On 03/05/2016 09:10 AM, Mark Brown wrote:
> On Fri, Mar 04, 2016 at 07:14:42PM +0530, Purna Chandra Mandal wrote:
>> The PIC32 SPI driver is capable of performing SPI transfers
>> using PIO or external DMA engine. GPIO controlled /CS support
> I don't seem to have patch 1 in t
On 04/02/2016 10:05 PM, Mark Brown wrote:
> On Fri, Apr 01, 2016 at 04:48:49PM +0530, Purna Chandra Mandal wrote:
>> Document the devicetree bindings for the SPI peripheral found
>> on Microchip PIC32 class devices.
> Please use subject lines reflecting the style for the subsystem.
ack. Will do.
On 03/29/2016 09:55 PM, Mark Brown wrote:
> On Tue, Mar 29, 2016 at 05:32:41PM +0530, Purna Chandra Mandal wrote:
>
>> It is required for MMC-over-SPI support. Linux MMC_SPI driver sometimes
>> (depending on some logic) want chip-select to be kept enabled (using
>>
Document the devicetree bindings for the SPI peripheral found
on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes i
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Changes in v5:
- report error for unsupported bits_per_word.
- drop custom debugging messages in favor of core provided one.
- use if-else instead of 'goto'
- moved enable/disable of controller to prepare/unprepare_hardware()
On 03/29/2016 12:56 AM, Mark Brown wrote:
> On Wed, Mar 23, 2016 at 07:12:56PM +0530, Purna Chandra Mandal wrote:
>
>> +switch (bits_per_word) {
>> +default:
>> +case 8:
> Are you sure that all bits per word settings other than those explicitly
> supporte
On 03/30/2016 09:18 PM, Mark Brown wrote:
> On Wed, Mar 30, 2016 at 04:19:16PM +0530, Purna Chandra Mandal wrote:
>> On 03/29/2016 09:55 PM, Mark Brown wrote:
>>> On Tue, Mar 29, 2016 at 05:32:41PM +0530, Purna Chandra Mandal wrote:
>>>> MMC_SPI will have to termi
Document Device tree bindings for the quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Cc: Kumar Gala <ga...@codeaurora.org>
Cc: Ian Campbell <ijc+devicet...@hellion.org.uk>
Cc: Rob Herring <robh...@
This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA transfer mode and supports
half-duplex communication for single, dual and quad SPI
transactions.
Signed-off-by: Purna Chandra Mandal <purna.
xtp = rdesc[i + 1].bd_dma;
> bd[PESQI_BD_COUNT - 1].bd_nextp = 0;
>
Reviewed-by: Purna Chandra Mandal <purna.man...@microchip.com>
by adding 'depends on HAS_DMA' in Kconfig.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
drivers/spi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 281ed5d..0f50755 100644
--- a/drivers/spi/Kconfig
+++ b/drive
This clock driver implements PIC32 specific clock-tree. clock-tree
entities can only be configured through device-tree file (OF).
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Note: Please pull this complete series through the MIPS tree.
Changes in v11:
- split
Document the devicetree bindings for the clock driver found on Microchip
PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: Stephen Boyd <sb...@
: Please pull this complete series through the MIPS tree.
Purna Chandra Mandal (3):
dt/bindings/clk: Add PIC32 clock binding documentation.
clk: microchip: Add Microchip PIC32 clock driver.
MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding
.../devicetree/bindings/clock
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Signed-off-by: Joshua Henderson <joshua.hender...@microchip.com>
Cc:
Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-pic32mzda
pbclk_set_rate() is using readl_poll_timeout_atomic() even
though spinlock is released. Fix it by replacing with
readl_poll_timeout().
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/mic
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt | 2 +-
1 file changed, 1 ins
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt | 4 ++--
1 file chan
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt | 2 +-
1 file changed, 1 ins
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt | 4 ++--
1 file chan
early clock functions implemented for early
console support.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Note: Please pull this complete series through the MIPS tree.
---
arch/mips/pic32/pic32mzda/time.c | 13 -
1 file changed, 4 insertions(+), 9 del
From: Joshua Henderson <digitalp...@digitalpeer.com>
The wrong external interrupt bits are being set, offset by 1.
Signed-off-by: Joshua Henderson <digitalp...@digitalpeer.com>
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
drivers/irqchip/irq-pic32-evi
Update binding example based on new clock binding documentation.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 +-
1 file chan
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | 2 +-
1 file chan
Allocated memory for 'sport->irq_fault_name' is freed twice, first
in error check of 'if(!sport->irq_rx_name)' and other in fallback
handler.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
drivers/tty/serial/pic32_uart.c | 1 -
1 file changed, 1 deletion(-)
On 05/07/2016 05:40 AM, Stephen Boyd wrote:
> Mostly nitpicks, although I'm worried about the iomem casting and
> addition stuff. I suppose if those are fixed up at some later
> time then I'm fine with this going through MIPS tree.
>
> On 03/23, Purna Chandra Mandal wrote:
On 04/14/2016 11:25 AM, Mark Brown wrote:
> On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:
>
>> +enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
>> +status = readl(sqi->regs + PESQI_INT_STAT_REG);
>> +if (!status)
&
Document Device tree bindings for the quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal <purna.man...@microchip.com>
Acked-by: Rob Herring <r...@kernel.org>
Cc: Kumar Gala <ga...@codeaurora.org>
Cc: Ian Campbell <ijc+devicet.
This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA transfer mode and supports
half-duplex communication for single, dual and quad SPI
transactions.
Signed-off-by: Purna Chandra Mandal <purna.
-off-by: Purna Chandra Mandal
---
drivers/mtd/spi-nor/cadence-quadspi.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 04cedd3a2bf6..7f78f9409ddd 100644
--- a/drivers/mtd/spi
.
Signed-off-by: Purna Chandra Mandal
---
drivers/mtd/spi-nor/cadence-quadspi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 04cedd3a2bf6..990934387fea 100644
--- a/drivers/mtd/spi-nor
Document the devicetree bindings for the clock driver found on Microchip
PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Cc: Ralf Baechle
Cc: Michael Turquette
Cc: Stephen Boyd
Acked-by: Rob Herring
Acked-by: Michael Turquette
---
Note: Please pull this complete series through
: Please pull this complete series through the MIPS tree.
Purna Chandra Mandal (3):
dt/bindings/clk: Add PIC32 clock binding documentation.
clk: microchip: Add Microchip PIC32 clock driver.
MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding
.../devicetree/bindings/clock
This clock driver implements PIC32 specific clock-tree. clock-tree
entities can only be configured through device-tree file (OF).
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
Changes in v11:
- split clock-init-data from clock-driver
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Signed-off-by: Purna Chandra Mandal
Signed-off-by: Joshua Henderson
Cc: Ralf Baechle
Cc: Michael Turquette
Cc: Stephen Boyd
---
Note: Please
by adding 'depends on HAS_DMA' in Kconfig.
Signed-off-by: Purna Chandra Mandal
---
drivers/spi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 281ed5d..0f50755 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -445,6 +445,7
On 05/07/2016 05:40 AM, Stephen Boyd wrote:
> Mostly nitpicks, although I'm worried about the iomem casting and
> addition stuff. I suppose if those are fixed up at some later
> time then I'm fine with this going through MIPS tree.
>
> On 03/23, Purna Chandra Mandal wrote:
Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-pic32mzda.c | 1 +
1 file changed, 1 insertion
pbclk_set_rate() is using readl_poll_timeout_atomic() even
though spinlock is released. Fix it by replacing with
readl_poll_timeout().
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-core.c | 6 +++---
1 file
early clock functions implemented for early
console support.
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
arch/mips/pic32/pic32mzda/time.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/mips/pic32
From: Joshua Henderson
The wrong external interrupt bits are being set, offset by 1.
Signed-off-by: Joshua Henderson
Signed-off-by: Purna Chandra Mandal
---
drivers/irqchip/irq-pic32-evic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-pic32-evic.c
Update binding example based on new clock binding documentation.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Allocated memory for 'sport->irq_fault_name' is freed twice, first
in error check of 'if(!sport->irq_rx_name)' and other in fallback
handler.
Signed-off-by: Purna Chandra Mandal
---
drivers/tty/serial/pic32_uart.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/tty/
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On 02/05/2016 07:02 PM, Sergei Shtylyov wrote:
> Hello.
> On 2/5/2016 8:08 AM, Purna Chandra Mandal wrote:
>>>> From: Purna Chandra Mandal
>>>> Document the devicetree bindings for the SPI peripheral found
>>>> on Microchip PIC32 class devices
On 04/11/2016 08:40 PM, Rob Herring wrote:
> On Thu, Apr 07, 2016 at 06:02:59PM +0530, Purna Chandra Mandal wrote:
>> Document devicetree binding for the USB controller
>> and USB Phy found on Microchip PIC32 class devices.
>>
>> Signed-off-by: Purna Chandra Mandal
&g
On 04/14/2016 11:25 AM, Mark Brown wrote:
> On Wed, Apr 13, 2016 at 06:52:58PM +0530, Purna Chandra Mandal wrote:
>
>> +enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
>> +status = readl(sqi->regs + PESQI_INT_STAT_REG);
>> +if (!status)
&
Document Device tree bindings for the quad SPI peripheral
found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Acked-by: Rob Herring
Cc: Kumar Gala
Cc: Ian Campbell
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Mark Brown
---
Changes in v3:
- update exmaple
This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA transfer mode and supports
half-duplex communication for single, dual and quad SPI
transactions.
Signed-off-by: Purna Chandra Mandal
Cc: Mark Brown
On 04/02/2016 10:05 PM, Mark Brown wrote:
> On Fri, Apr 01, 2016 at 04:48:49PM +0530, Purna Chandra Mandal wrote:
>> Document the devicetree bindings for the SPI peripheral found
>> on Microchip PIC32 class devices.
> Please use subject lines reflecting the style for the subsystem.
ack. Will do.
On 03/30/2016 09:18 PM, Mark Brown wrote:
> On Wed, Mar 30, 2016 at 04:19:16PM +0530, Purna Chandra Mandal wrote:
>> On 03/29/2016 09:55 PM, Mark Brown wrote:
>>> On Tue, Mar 29, 2016 at 05:32:41PM +0530, Purna Chandra Mandal wrote:
>>>> MMC_SPI will have to termi
Document the devicetree bindings for the SPI peripheral found
on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
Acked-by: Rob Herring
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- fix indentation
- add space after comma
- moved 'cs
Signed-off-by: Purna Chandra Mandal
---
Changes in v5:
- report error for unsupported bits_per_word.
- drop custom debugging messages in favor of core provided one.
- use if-else instead of 'goto'
- moved enable/disable of controller to prepare/unprepare_hardware()
- refactor setup(), just retain cs-dese
From: Cristian Birsan
This driver adds support of PIC32 MUSB OTG controller as
dual role device. It implements platform specific glue to
reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
---
drivers/usb/musb/Kconfig | 9 +-
drivers/usb/musb/Makefile
Document devicetree binding for the USB controller
and USB Phy found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
---
.../bindings/usb/microchip,pic32-musb.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation
Document devicetree binding for the USB controller
and USB Phy found on Microchip PIC32 class devices.
Signed-off-by: Purna Chandra Mandal
---
Changes in v2: None
.../bindings/usb/microchip,pic32-musb.txt | 67 ++
1 file changed, 67 insertions(+)
create mode
From: Cristian Birsan
This driver adds support of PIC32 MUSB OTG controller as
dual role device. It implements platform specific glue to
reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
In-reply-to: 460027775-20729-2-git-send-email-purna.man
On 04/07/2016 06:09 PM, Felipe Balbi wrote:
> Purna Chandra Mandal writes:
>> From: Cristian Birsan
>>
>> This driver adds support of PIC32 MUSB OTG controller as
>> dual role device. It implements platform specific glue to
>> reuse musb core.
>>
>>
On 04/07/2016 06:23 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 4/7/2016 2:16 PM, Purna Chandra Mandal wrote:
>
>> Document devicetree binding for the USB controller
>
>Device tree.
>
ack.
>> and USB Phy found on Microchip PIC32 class devices.
>
>
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