Hi Lee,
On 18/07/2017 11:49, Lee Jones wrote:
> On Tue, 18 Jul 2017, Quentin Schulz wrote:
>
>> Hi Lee,
>>
>> On 18/07/2017 09:19, Lee Jones wrote:
>>> On Mon, 17 Jul 2017, Quentin Schulz wrote:
>>>
>>>> According to their datasheets, the
Hi Maxime,
On 18/07/2017 09:57, Maxime Ripard wrote:
> On Tue, Jul 18, 2017 at 09:36:04AM +0200, Quentin Schulz wrote:
>>>> +
>>>> + error = sysfs_create_group(>dev.kobj,
>>>> + axp20x_pek->attribute_group);
>
Hi Maxime,
On 18/07/2017 09:57, Maxime Ripard wrote:
> On Tue, Jul 18, 2017 at 09:36:04AM +0200, Quentin Schulz wrote:
>>>> +
>>>> + error = sysfs_create_group(>dev.kobj,
>>>> + axp20x_pek->attribute_group);
>
Hi Lee,
On 18/07/2017 09:19, Lee Jones wrote:
> On Mon, 17 Jul 2017, Quentin Schulz wrote:
>
>> According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
>> AXP809 and AXP813 PEK have different values for startup time bits from
>> the AXP20X, let's us
Hi Lee,
On 18/07/2017 09:19, Lee Jones wrote:
> On Mon, 17 Jul 2017, Quentin Schulz wrote:
>
>> According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
>> AXP809 and AXP813 PEK have different values for startup time bits from
>> the AXP20X, let's us
Hi Maxime,
On 17/07/2017 13:29, Maxime Ripard wrote:
> Hi,
>
> On Mon, Jul 17, 2017 at 11:53:06AM +0200, Quentin Schulz wrote:
>> The AXP221 has different values for startup time bits from the AXP20X.
>>
>> This patch introduces a different platform_device_i
Hi Maxime,
On 17/07/2017 13:29, Maxime Ripard wrote:
> Hi,
>
> On Mon, Jul 17, 2017 at 11:53:06AM +0200, Quentin Schulz wrote:
>> The AXP221 has different values for startup time bits from the AXP20X.
>>
>> This patch introduces a different platform_device_i
Hi Lee,
On 18/07/2017 09:18, Lee Jones wrote:
> On Mon, 17 Jul 2017, Quentin Schulz wrote:
>
>> Hi all,
>>
>> On 17/07/2017 11:53, Quentin Schulz wrote:
>>> According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
>>> AXP809 and AXP813 PEK h
Hi Lee,
On 18/07/2017 09:18, Lee Jones wrote:
> On Mon, 17 Jul 2017, Quentin Schulz wrote:
>
>> Hi all,
>>
>> On 17/07/2017 11:53, Quentin Schulz wrote:
>>> According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
>>> AXP809 and AXP813 PEK h
Hi all,
On 17/07/2017 11:53, Quentin Schulz wrote:
> According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
> AXP809 and AXP813 PEK have different values for startup time bits from
> the AXP20X PEK (which are currently used for all the aforementioned PMICs).
>
> Th
Hi all,
On 17/07/2017 11:53, Quentin Schulz wrote:
> According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
> AXP809 and AXP813 PEK have different values for startup time bits from
> the AXP20X PEK (which are currently used for all the aforementioned PMICs).
>
> Th
the board.
Thanks,
Quentin
Quentin Schulz (2):
Input: axp20x-pek: add support for AXP221 PEK
mfd: axp20x: use correct platform device id for many PEK
drivers/input/misc/axp20x-pek.c | 62 ++---
drivers/mfd/axp20x.c| 12
2 files changed
the board.
Thanks,
Quentin
Quentin Schulz (2):
Input: axp20x-pek: add support for AXP221 PEK
mfd: axp20x: use correct platform device id for many PEK
drivers/input/misc/axp20x-pek.c | 62 ++---
drivers/mfd/axp20x.c| 12
2 files changed
The AXP221 has different values for startup time bits from the AXP20X.
This patch introduces a different platform_device_id to the driver and
adds the necessary code to handle the different platform_device_ids.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
drivers
The AXP221 has different values for startup time bits from the AXP20X.
This patch introduces a different platform_device_id to the driver and
adds the necessary code to handle the different platform_device_ids.
Signed-off-by: Quentin Schulz
---
drivers/input/misc/axp20x-pek.c | 62
According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
AXP809 and AXP813 PEK have different values for startup time bits from
the AXP20X, let's use the platform device id with the correct values.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
drive
According to their datasheets, the AXP221, AXP223, AXP288, AXP803,
AXP809 and AXP813 PEK have different values for startup time bits from
the AXP20X, let's use the platform device id with the correct values.
Signed-off-by: Quentin Schulz
---
drivers/mfd/axp20x.c | 12 ++--
1 file
The setting of clocks and presets is currently done in probe only but
once deep PM support is added, it'll be needed in the resume function.
Let's create a function for this setting.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Ludovic Desroches <ludov
The setting of clocks and presets is currently done in probe only but
once deep PM support is added, it'll be needed in the resume function.
Let's create a function for this setting.
Signed-off-by: Quentin Schulz
Acked-by: Ludovic Desroches
Acked-by: Adrian Hunter
---
drivers/mmc/host/sdhci
to be
reconfigured as well.
The other registers and init process are taken care of by the SDHCI
core.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Ludovic Desroches <ludovic.desroc...@microchip.com>
---
v3:
- pm_runtime_force_suspend before setting restore
to be
reconfigured as well.
The other registers and init process are taken care of by the SDHCI
core.
Signed-off-by: Quentin Schulz
Acked-by: Ludovic Desroches
---
v3:
- pm_runtime_force_suspend before setting restore_needed flag,
v2:
- use runtime_resume as system_resume,
- set a flag
The way to find the best_diff and do the appropriate process afterwards
can be re-used.
This patch prepares the driver for an upcoming patch that will allow
clk_generated to determine the rate of the audio_pll.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by:
The way to find the best_diff and do the appropriate process afterwards
can be re-used.
This patch prepares the driver for an upcoming patch that will allow
clk_generated to determine the rate of the audio_pll.
Signed-off-by: Quentin Schulz
Acked-by: Boris Brezillon
---
drivers/clk/at91/clk
From: Cyrille Pitchen <cyrille.pitc...@atmel.com>
This patch adds nodes for the classd device and its generated clock.
Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Quentin Schulz &l
From: Cyrille Pitchen
This patch adds nodes for the classd device and its generated clock.
Signed-off-by: Cyrille Pitchen
Signed-off-by: Nicolas Ferre
Signed-off-by: Quentin Schulz
---
arch/arm/boot/dts/sama5d2.dtsi | 39 ++-
1 file changed, 38 insertions
ed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
v2:
- split DT binding in a different patch,
- removed unused AUDIO_PLL_*FOUT* defines from clk-audio-pll-pmc,
- split classD modifications in a different patch,
arch/arm/mach-at91/Kconfig | 4 +
driv
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.
The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre
Signed-off-by: Quentin Schulz
of the clock.
Since audio IPs are most likely to request the same rate, we enforce
that the only clks able to modify gck rate are those of audio IPs.
To remain consistent, we deny other clocks to be children of audio_pll.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Since gclk (generated-clk) is now able to determine the rate of the
audio_pll, there is no need for classd to have a direct phandle to the
audio_pll while already having a phandle to gclk.
This binding is used by no board in mainline so it is safe to be
modified.
Signed-off-by: Quentin Schulz
of the clock.
Since audio IPs are most likely to request the same rate, we enforce
that the only clks able to modify gck rate are those of audio IPs.
To remain consistent, we deny other clocks to be children of audio_pll.
Signed-off-by: Quentin Schulz
Acked-by: Boris Brezillon
---
v3:
- added
Since gclk (generated-clk) is now able to determine the rate of the
audio_pll, there is no need for classd to have a direct phandle to the
audio_pll while already having a phandle to gclk.
This binding is used by no board in mainline so it is safe to be
modified.
Signed-off-by: Quentin Schulz
From: Cyrille Pitchen <cyrille.pitc...@atmel.com>
This patch adds the pin muxing for classd and enables it.
Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Quentin Schulz <quentin.sch.
-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Mark Brown <broo...@kernel.org>
---
added in v2:
- split from bigger patch with audio PLLs and DT binding,
- updated all variables and macros named ACLK to GCLK,
sound/soc/atmel/atmel-c
From: Cyrille Pitchen
This patch adds the pin muxing for classd and enables it.
Signed-off-by: Cyrille Pitchen
Signed-off-by: Nicolas Ferre
Signed-off-by: Quentin Schulz
---
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 16
1 file changed, 16 insertions(+)
diff --git
-by: Quentin Schulz
Acked-by: Mark Brown
---
added in v2:
- split from bigger patch with audio PLLs and DT binding,
- updated all variables and macros named ACLK to GCLK,
sound/soc/atmel/atmel-classd.c | 47 +-
1 file changed, 14 insertions(+), 33 deletions
://patchwork.kernel.org/patch/9462349/
[4] https://www.spinics.net/lists/arm-kernel/msg436120.html
[5] http://www.spinics.net/lists/linux-clk/msg17927.html
Cyrille Pitchen (2):
ARM: dts: at91: sama5d2: add classd nodes
ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd
Quentin
://patchwork.kernel.org/patch/9462349/
[4] https://www.spinics.net/lists/arm-kernel/msg436120.html
[5] http://www.spinics.net/lists/linux-clk/msg17927.html
Cyrille Pitchen (2):
ARM: dts: at91: sama5d2: add classd nodes
ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd
Quentin
(passed along req argument of the function) and
the parent clock rate, thus we know the closest rounded divisor, we
don't need to iterate over the available divisors to find the best one
for a given clock.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Boris Bre
(passed along req argument of the function) and
the parent clock rate, thus we know the closest rounded divisor, we
don't need to iterate over the available divisors to find the best one
for a given clock.
Signed-off-by: Quentin Schulz
Acked-by: Boris Brezillon
---
drivers/clk/at91/clk-generated.c
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers.
This adds the audio plls (frac, pad and pmc) to the compatible list of
at91 clocks in DT binding.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Rob H
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers.
This adds the audio plls (frac, pad and pmc) to the compatible list of
at91 clocks in DT binding.
Signed-off-by: Quentin Schulz
Acked-by: Rob Herring
---
added in v2:
- split from
The setting of clocks and presets is currently done in probe only but
once deep PM support is added, it'll be needed in the resume function.
Let's create a function for this setting.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Ludovic Desroches <ludov
The setting of clocks and presets is currently done in probe only but
once deep PM support is added, it'll be needed in the resume function.
Let's create a function for this setting.
Signed-off-by: Quentin Schulz
Acked-by: Ludovic Desroches
Acked-by: Adrian Hunter
---
drivers/mmc/host/sdhci
to be
reconfigured as well.
The other registers and init process are taken care of by the SDHCI
core.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Ludovic Desroches <ludovic.desroc...@microchip.com>
---
v2:
- use runtime_resume as system_resume,
- set a
to be
reconfigured as well.
The other registers and init process are taken care of by the SDHCI
core.
Signed-off-by: Quentin Schulz
Acked-by: Ludovic Desroches
---
v2:
- use runtime_resume as system_resume,
- set a flag to tell when restoring presets is needed,
- use a flag to tell
Better with the link.
On 05/07/2017 08:23, Quentin Schulz wrote:
> Hi Adrian and Ludovic,
>
> On 20/06/2017 11:49, Ludovic Desroches wrote:
>> On Tue, Jun 20, 2017 at 10:07:06AM +0200, Quentin Schulz wrote:
>>> Hi Adrian,
>>>
>>> On 20/06/2017 09:39, A
Better with the link.
On 05/07/2017 08:23, Quentin Schulz wrote:
> Hi Adrian and Ludovic,
>
> On 20/06/2017 11:49, Ludovic Desroches wrote:
>> On Tue, Jun 20, 2017 at 10:07:06AM +0200, Quentin Schulz wrote:
>>> Hi Adrian,
>>>
>>> On 20/06/2017 09:39, A
Hi Adrian and Ludovic,
On 20/06/2017 11:49, Ludovic Desroches wrote:
> On Tue, Jun 20, 2017 at 10:07:06AM +0200, Quentin Schulz wrote:
>> Hi Adrian,
>>
>> On 20/06/2017 09:39, Adrian Hunter wrote:
>>> On 16/06/17 10:29, Quentin Schulz wrote:
>>>> This add
Hi Adrian and Ludovic,
On 20/06/2017 11:49, Ludovic Desroches wrote:
> On Tue, Jun 20, 2017 at 10:07:06AM +0200, Quentin Schulz wrote:
>> Hi Adrian,
>>
>> On 20/06/2017 09:39, Adrian Hunter wrote:
>>> On 16/06/17 10:29, Quentin Schulz wrote:
>>>> This add
When phy-sun4i-usb's probing fails, it does not print the reason in
kernel log, forcing the developer to edit this driver to add info logs.
This commit makes the kernel print the reason of phy-sun4i-usb's probing
failure or a success message.
Signed-off-by: Quentin Schulz <quentin.sch...@f
When phy-sun4i-usb's probing fails, it does not print the reason in
kernel log, forcing the developer to edit this driver to add info logs.
This commit makes the kernel print the reason of phy-sun4i-usb's probing
failure or a success message.
Signed-off-by: Quentin Schulz
---
Nothing new in v3
From: Cyrille Pitchen <cyrille.pitc...@atmel.com>
This patch adds the pin muxing for classd and enables it.
Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Quentin Schulz <quentin.sch.
-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
added in v2:
- split from bigger patch with audio PLLs and DT binding,
- updated all variables and macros named ACLK to GCLK,
sound/soc/atmel/atmel-classd.c | 47 +-
1 file changed, 14 inse
of the clock.
Since audio IPs are most likely to request the same rate, we enforce
that the only clks able to modify gck rate are those of audio IPs.
To remain consistent, we deny other clocks to be children of audio_pll.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
-
From: Cyrille Pitchen <cyrille.pitc...@atmel.com>
This patch adds nodes for the classd device and its generated clock.
Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Quentin Schulz &l
of the clock.
Since audio IPs are most likely to request the same rate, we enforce
that the only clks able to modify gck rate are those of audio IPs.
To remain consistent, we deny other clocks to be children of audio_pll.
Signed-off-by: Quentin Schulz
---
v2:
- added conditions for audio pll
From: Cyrille Pitchen
This patch adds nodes for the classd device and its generated clock.
Signed-off-by: Cyrille Pitchen
Signed-off-by: Nicolas Ferre
Signed-off-by: Quentin Schulz
---
arch/arm/boot/dts/sama5d2.dtsi | 39 ++-
1 file changed, 38 insertions
From: Cyrille Pitchen
This patch adds the pin muxing for classd and enables it.
Signed-off-by: Cyrille Pitchen
Signed-off-by: Nicolas Ferre
Signed-off-by: Quentin Schulz
---
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 16
1 file changed, 16 insertions(+)
diff --git
-by: Quentin Schulz
---
added in v2:
- split from bigger patch with audio PLLs and DT binding,
- updated all variables and macros named ACLK to GCLK,
sound/soc/atmel/atmel-classd.c | 47 +-
1 file changed, 14 insertions(+), 33 deletions(-)
diff --git a/sound
Since gclk (generated-clk) is now able to determine the rate of the
audio_pll, there is no need for classd to have a direct phandle to the
audio_pll while already having a phandle to gclk.
This binding is used by no board in mainline so it is safe to be
modified.
Signed-off-by: Quentin Schulz
Since gclk (generated-clk) is now able to determine the rate of the
audio_pll, there is no need for classd to have a direct phandle to the
audio_pll while already having a phandle to gclk.
This binding is used by no board in mainline so it is safe to be
modified.
Signed-off-by: Quentin Schulz
(passed along req argument of the function) and
the parent clock rate, thus we know the closest rounded divisor, we
don't need to iterate over the available divisors to find the best one
for a given clock.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Boris Bre
(passed along req argument of the function) and
the parent clock rate, thus we know the closest rounded divisor, we
don't need to iterate over the available divisors to find the best one
for a given clock.
Signed-off-by: Quentin Schulz
Acked-by: Boris Brezillon
---
drivers/clk/at91/clk-generated.c
://patchwork.kernel.org/patch/9462349/
[4] https://www.spinics.net/lists/arm-kernel/msg436120.html
[5] http://www.spinics.net/lists/linux-clk/msg17927.html
Cyrille Pitchen (2):
ARM: dts: at91: sama5d2: add classd nodes
ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd
Quentin
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers.
This adds the audio plls (frac, pad and pmc) to the compatible list of
at91 clocks in DT binding.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by: Rob H
://patchwork.kernel.org/patch/9462349/
[4] https://www.spinics.net/lists/arm-kernel/msg436120.html
[5] http://www.spinics.net/lists/linux-clk/msg17927.html
Cyrille Pitchen (2):
ARM: dts: at91: sama5d2: add classd nodes
ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd
Quentin
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers.
This adds the audio plls (frac, pad and pmc) to the compatible list of
at91 clocks in DT binding.
Signed-off-by: Quentin Schulz
Acked-by: Rob Herring
---
added in v2:
- split from
The way to find the best_diff and do the appropriate process afterwards
can be re-used.
This patch prepares the driver for an upcoming patch that will allow
clk_generated to determine the rate of the audio_pll.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
Acked-by:
The way to find the best_diff and do the appropriate process afterwards
can be re-used.
This patch prepares the driver for an upcoming patch that will allow
clk_generated to determine the rate of the audio_pll.
Signed-off-by: Quentin Schulz
Acked-by: Boris Brezillon
---
drivers/clk/at91/clk
ed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
v2:
- split DT binding in a different patch,
- removed unused AUDIO_PLL_*FOUT* defines from clk-audio-pll-pmc,
- split classD modifications in a different patch,
arch/arm/mach-at91/Kconfig | 4 +
driv
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.
The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre
Signed-off-by: Quentin Schulz
Reported-by: Andreas Färber <afaer...@suse.de>
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
drivers/iio/adc/sun4i-gpadc-iio.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/s
Reported-by: Andreas Färber
Signed-off-by: Quentin Schulz
---
drivers/iio/adc/sun4i-gpadc-iio.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 81d4c39e414a..137f577d9432 100644
--- a/drivers/iio
The way to find the best_diff and do the appropriate process afterwards
can be re-used.
This patch prepares the driver for an upcoming patch that will allow
clk_generated to determine the rate of the audio_pll.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
drive
The way to find the best_diff and do the appropriate process afterwards
can be re-used.
This patch prepares the driver for an upcoming patch that will allow
clk_generated to determine the rate of the audio_pll.
Signed-off-by: Quentin Schulz
---
drivers/clk/at91/clk-generated.c | 41
From: Cyrille Pitchen <cyrille.pitc...@atmel.com>
This patch adds nodes for the classd device and its generated clock.
Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Quentin Schulz &l
From: Cyrille Pitchen
This patch adds nodes for the classd device and its generated clock.
Signed-off-by: Cyrille Pitchen
Signed-off-by: Nicolas Ferre
Signed-off-by: Quentin Schulz
---
arch/arm/boot/dts/sama5d2.dtsi | 39 ++-
1 file changed, 38 insertions
ed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
.../devicetree/bindings/clock/at91-clock.txt | 10 +
arch/arm/mach-at91/Kconfig | 4 +
drivers/clk/at91/Makefile |
-by: Quentin Schulz
---
.../devicetree/bindings/clock/at91-clock.txt | 10 +
arch/arm/mach-at91/Kconfig | 4 +
drivers/clk/at91/Makefile | 2 +
drivers/clk/at91/clk-audio-pll-pad.c | 204 ++
drivers/clk/at91/clk
://patchwork.kernel.org/patch/9462349/
[4] https://www.spinics.net/lists/arm-kernel/msg436120.html
Cyrille Pitchen (2):
ARM: dts: at91: sama5d2: add classd nodes
ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd
Nicolas Ferre (1):
clk: at91: add audio pll clock driver
Quentin Schulz (3):
clk
://patchwork.kernel.org/patch/9462349/
[4] https://www.spinics.net/lists/arm-kernel/msg436120.html
Cyrille Pitchen (2):
ARM: dts: at91: sama5d2: add classd nodes
ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd
Nicolas Ferre (1):
clk: at91: add audio pll clock driver
Quentin Schulz (3):
clk
to be re-worked once we have a rate locking system so two
clocks could be children of the same clock and be sure the clock rate
isn't changed by one or the other.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
drivers/clk/at91/clk-generated.
to be re-worked once we have a rate locking system so two
clocks could be children of the same clock and be sure the clock rate
isn't changed by one or the other.
Signed-off-by: Quentin Schulz
---
drivers/clk/at91/clk-generated.c | 41 ++--
1 file changed, 35
(passed along req argument of the function) and
the parent clock rate, thus we know the closest rounded divisor, we
don't need to iterate over the available divisors to find the best one
for a given clock.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
drivers/clk/at
(passed along req argument of the function) and
the parent clock rate, thus we know the closest rounded divisor, we
don't need to iterate over the available divisors to find the best one
for a given clock.
Signed-off-by: Quentin Schulz
---
drivers/clk/at91/clk-generated.c | 25
From: Cyrille Pitchen <cyrille.pitc...@atmel.com>
This patch adds the pin muxing for classd and enables it.
Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Quentin Schulz <quentin.sch.
From: Cyrille Pitchen
This patch adds the pin muxing for classd and enables it.
Signed-off-by: Cyrille Pitchen
Signed-off-by: Nicolas Ferre
Signed-off-by: Quentin Schulz
---
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 16
1 file changed, 16 insertions(+)
diff --git
Hi Adrian,
On 20/06/2017 08:36, Adrian Hunter wrote:
> On 16/06/17 10:29, Quentin Schulz wrote:
>> The setting of clocks and presets is currently done in probe only but
>> once deep PM support is added, it'll be needed in the resume function.
>>
>> Let's create
Hi Adrian,
On 20/06/2017 08:36, Adrian Hunter wrote:
> On 16/06/17 10:29, Quentin Schulz wrote:
>> The setting of clocks and presets is currently done in probe only but
>> once deep PM support is added, it'll be needed in the resume function.
>>
>> Let's create
Hi Adrian,
On 20/06/2017 09:39, Adrian Hunter wrote:
> On 16/06/17 10:29, Quentin Schulz wrote:
>> This adds deepest (Backup+Self-Refresh) PM support to the ATMEL SAMA5D2
>> SoC's SDHCI controller.
>>
>> When resuming from deepest state, it is required to
Hi Adrian,
On 20/06/2017 09:39, Adrian Hunter wrote:
> On 16/06/17 10:29, Quentin Schulz wrote:
>> This adds deepest (Backup+Self-Refresh) PM support to the ATMEL SAMA5D2
>> SoC's SDHCI controller.
>>
>> When resuming from deepest state, it is required to
The setting of clocks and presets is currently done in probe only but
once deep PM support is added, it'll be needed in the resume function.
Let's create a function for this setting.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
drivers/mmc/host/sdhci-of-at91.c
to be
reconfigured as well.
The other registers and init process are taken care of by the SDHCI
core.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
drivers/mmc/host/sdhci-of-at91.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
The setting of clocks and presets is currently done in probe only but
once deep PM support is added, it'll be needed in the resume function.
Let's create a function for this setting.
Signed-off-by: Quentin Schulz
---
drivers/mmc/host/sdhci-of-at91.c | 147
to be
reconfigured as well.
The other registers and init process are taken care of by the SDHCI
core.
Signed-off-by: Quentin Schulz
---
drivers/mmc/host/sdhci-of-at91.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci
process and will be disabled when shutting down.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
.../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 +++
drivers/pci/dwc/pci-imx6.c | 34 +-
2 files changed, 37 insertions
process and will be disabled when shutting down.
Signed-off-by: Quentin Schulz
---
.../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 +++
drivers/pci/dwc/pci-imx6.c | 34 +-
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/Documentation
.
Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com>
---
v2:
- return -EINVAL when phy-reset-post-delay is greater than 1000ms
instead of defaulting to 1ms,
- remove `default to 1ms` when phy-reset-post-delay > 1000Ms from DT
binding doc and commit log,
- move
.
Signed-off-by: Quentin Schulz
---
v2:
- return -EINVAL when phy-reset-post-delay is greater than 1000ms
instead of defaulting to 1ms,
- remove `default to 1ms` when phy-reset-post-delay > 1000Ms from DT
binding doc and commit log,
- move phy-reset-post-delay property reading bef
Hi Andrew
On 22/05/2017 15:57, Andrew Lunn wrote:
> On Mon, May 22, 2017 at 11:15:17AM +0200, Quentin Schulz wrote:
>> Some PHY require to wait for a bit after the reset GPIO has been
>> toggled. This adds support for the DT property `phy-reset-post-delay`
>> which gives the
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