ared data SD.
* Am I guaranteed serialized execution of A and B, or should I play
safe and use a semaphore (acquire/release) with A and B ?
Thanks,
Vijay
PS: Please CC me in the reply.
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Hello,
I am new to the Kernel-Mailing list. I am not subscribed at the moment
and would really appreciate it, if I can be CC'd in the
reply/responses for my question.
I am studying the different logging mechanisms on Linux in case of a
Kernel panic (OOPS). So far from my search on the web, I hav
Hello,
I am new to the Kernel-Mailing list. I am not subscribed at the moment
and would really appreciate it, if I can be CC'd in the
reply/responses for my question.
I have searched all over the web but haven't found a convincing answer
to a couple of related questions I have, with regard to the
Hello,
I am new to the Kernel-Mailing list. I am not subscribed at the moment
and would really appreciate it, if I can be CC'd for all the
reply/responses for my question.
I have searched all over the web but haven't found a convincing answer
to a couple of related questions I have, with regard
> +{ "ListenDrops", N_("%u SYNs to LISTEN sockets dropped"), opt_number },
>
> (see the file debian/patches/CVS-20081003-statistics.c_sync.patch
> in the net-tools src)
>
> i.e., the netstat pkg is printing the value of the TCPEXT MIB counter
> that's counting TCPExtListenDrops.
>
> Theoretica
0 +---
> 1 files changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/filesystems/porting
> b/Documentation/filesystems/porting
> index 2bef2b3..d6d53fb 100644
> +static struct file_system_type foo_fs_type = {
> + .owner = THIS_MODOU
d with Patch v1 and it resolves this
issue.
Thanks,
Vijay
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Please read the FAQ at http://www.tux.org/lkml/
> 1)
goto drop;
These drops do not seem to be tracked by any MIB variable and so will
not show up in netstat
(Also, newer nstat is preferred to netstat ).
Maybe we need to track these drops too?
Vijay
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Please read the FAQ at http://www.tux.org/lkml/
From: Vijay Sampath <[EMAIL PROTECTED]>
The files cfi_cmdset_0002.c and cfi_cmdset_0020.c do not initialize
their wait queues like is done in cfi_cmdset_0001.c. This causes an
oops when the wait queue is accessed. I have copied the code from
cfi_cmdset_0001.c that is pertinent to initiali
HW issue with power IRQ handling during reset
mmc: sdhci-msm: Add support to wait for power irq
Subhash Jadavani (1):
mmc: sdhci-msm: fix issue with power irq
Vijay Viswanath (2):
mmc: sdhci-msm: Add ops to do sdhc register write
defconfig: msm: Enable CONFIG_MMC_SDHCI_IO_ACCESSORS
arch
status
is acknowledged otherwise power irq interrupt handler would be fired
prematurely.
Signed-off-by: Subhash Jadavani
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b
spurious power IRQ which results in system instability.
Signed-off-by: Sahitya Tummala
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 43 ---
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b
SDHCI_POWER_CONTROL register.
* There is a state change in 1.8V enable bit (bit 3) of
SDHCI_HOST_CONTROL2 register.
* Bit 1 of SDHCI_SOFTWARE_RESET is set.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 39 +++
1 file changed, 39 insertions
Enable CONFIG_MMC_SDHCI_IO_ACCESSORS so that SDHC controller specific
register read and write APIs, if registered, can be used.
Signed-off-by: Vijay Viswanath
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs
From: Sahitya Tummala
Add support API which will check if power irq is expected to be
generated and wait for the power irq to come and complete if the irq is
expected.
Signed-off-by: Sahitya Tummala
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 125
Hi All,
I see "HAVE_PCI_MMAP" is defined in arm32 but missing in arm64 support.
Is it intentional or missed out because no-body asked for it.
Regards,
Vijay
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the msm driver and use them.
Voltage switching from core layer is causing CRC/cmd timeout errors in
some chipsets.
Tested on: sdm845, db410c
Requies patch series:"[PATCH V3 0/4] Changes for SDCC5 version"
Vijay Viswanath (2):
mmc: sdhci: Allow platform controlled voltage switching
Some controllers can have internal mechanism to inform the SW that it
is ready for voltage switching. For such controllers, changing voltage
before the HW is ready can result in various issues.
Add a quirk, which can be used by drivers of such controllers.
Signed-off-by: Vijay Viswanath
.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 99 ++--
1 file changed, 87 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index a0dc3e1..ebdde29 100644
--- a/drivers/mmc/host/sdhci
s if sdhci_msm layer is present.
Tested on: sdm845
Requies patch series:"[PATCH V3 0/4] Changes for SDCC5 version"
Vijay Viswanath (3):
mmc: sdhci: Allow platform controlled voltage switching
Documentation: sdhci-msm: Add entries for passing load values
mmc: sdhci-msm: Use internal v
driver.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 1c828e0..494a1e2 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
The load a particular sdhc controller should request from a regulator
is device specific and hence each device should individually vote for
the required load.
Signed-off-by: Vijay Viswanath
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 6 ++
1 file changed, 6 insertions(+)
diff
.
Signed-off-by: Asutosh Das
Signed-off-by: Venkat Gopalakrishnan
Signed-off-by: Veerabhadrarao Badiganti
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 220 ---
1 file changed, 209 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc
Hi Sayali,
On 7/13/2018 3:22 PM, Sayali Lokhande wrote:
This change adds the use of devfreq to MMC.
Both eMMC and SD card will use it.
For some workloads, such as video playback, it isn't
necessary for these cards to run at high speed.
Running at lower frequency, for example 52MHz, in such
cases
Hi Adrian,
On 7/25/2018 5:23 PM, Adrian Hunter wrote:
On 20/07/18 13:46, Vijay Viswanath wrote:
Some controllers can have internal mechanism to inform the SW that it
is ready for voltage switching. For such controllers, changing voltage
before the HW is ready can result in various issues
the
SDC1_SDCC_HC_VENDOR_SPECIFIC_FUNC register:
HC_IO_PAD_PWR_SWITCH: bit 16
HC_IO_PAD_PWR_SWITCH_EN: bit 15
Krishna Konda (1):
mmc: sdhci-msm: support voltage pad switching
Vijay Viswanath (1):
mmc: sdhci-msm: Add support to store supported vdd-io voltages
drivers/mmc/host/sd
During probe check whether the vdd-io regulator of sdhc platform device
can support 1.8V and 3V and store this information as a capability of
platform device.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 38 ++
1 file changed, 38
used for IO lines. So when power irq is
triggered for io high or io low, the driver should check the voltages
supported and set the pad accordingly.
Signed-off-by: Krishna Konda
Signed-off-by: Venkat Gopalakrishnan
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 38
Hi Dough, Jeremy,
On 3/3/2018 4:38 AM, Jeremy McNicoll wrote:
On 2018-03-02 10:23 AM, Doug Anderson wrote:
Hi,
On Sun, Feb 11, 2018 at 10:01 PM, Vijay Viswanath
wrote:
During probe check whether the vdd-io regulator of sdhc platform device
can support 1.8V and 3V and store this information
On 3/29/2018 4:23 AM, Doug Anderson wrote:
Hi,
On Wed, Mar 28, 2018 at 6:08 AM, Vijay Viswanath
wrote:
From: Krishna Konda
The PADs for SD card are dual-voltage that support 3v/1.8v. Those PADs
have a control signal (io_pad_pwr_switch/mode18 ) that indicates
whether the PAD works in 3v
On 5/22/2018 11:39 PM, Evan Green wrote:
Hi Vijay,
On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath
wrote:
From: Sayali Lokhande
For SDCC version 5.0.0, MCI registers are removed from SDCC
interface and some registers are moved to HC.
Define a new data structure where we can statically
On 5/22/2018 11:40 PM, Evan Green wrote:
On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath
wrote:
In addition to offsets of certain registers changing, the registers in
core_mem have been shifted to HC mem as well. To access these registers,
define msm version specific functions. These
On 5/22/2018 11:42 PM, Evan Green wrote:
Hi Vijay. Thanks for this patch.
On Thu, May 17, 2018 at 3:30 AM Vijay Viswanath
wrote:
From: Sayali Lokhande
For SDCC version 5.0.0 and higher, new compatible string
"qcom,sdhci-msm-v5" is added.
Based on the msm variant, pick th
-by: Vijay Viswanath
Reviewed-by: Evan Green
Acked-by: Adrian Hunter
---
drivers/mmc/host/sdhci-msm.c | 89
1 file changed, 89 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index bb11916..4050c99 100644
--- a
ss map
Documentation: sdhci-msm: Add new compatible string for SDCC v5
mmc: host: Register changes for sdcc V5
Vijay Viswanath (1):
mmc: sdhci-msm: Add msm version specific ops and data structures
.../devicetree/bindings/mmc/sdhci-msm.txt | 7 +-
drivers/mmc/host/s
.
Also defind new data structure to hold version specific Ops and
register addresses.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
Reviewed-by: Evan Green
---
drivers/mmc/host/sdhci-msm.c | 75
1 file changed, 75 insertions(+)
diff
From: Sayali Lokhande
For SDCC version 5.0.0 and higher, new compatible string
"qcom,sdhci-msm-v5" is added.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 7 ++-
1 file changed, 6
From: Sayali Lokhande
Add support to use the new compatible string "qcom,sdhci-msm-v5".
Based on the msm variant, pick the relevant variant data and
use it for register read/write to msm specific registers.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
Reviewed-by:
nd I didn't get any "Reset 0x1 never completed" error during card
insert/remove or shutdown.
Thanks,
Vijay
On 5/29/2018 5:49 PM, Georgi Djakov wrote:
Hello Vijay,
On 09/27/2017 08:34 AM, Vijay Viswanath wrote:
Register writes which change voltage of IO lines or turn the IO bus
Hi Stephen,
On 6/13/2018 5:06 AM, Stephen Boyd wrote:
Quoting Vijay Viswanath (2018-05-29 02:52:39)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 4050c99..2a66aa0 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -226,6 +226,24
On 6/13/2018 4:55 AM, Stephen Boyd wrote:
Quoting Vijay Viswanath (2018-05-29 02:52:41)
@@ -137,6 +125,12 @@
/* Timeout value to avoid infinite waiting for pwr_irq */
#define MSM_PWR_IRQ_TIMEOUT_MS 5000
+#define MSM_HOST_READL(msm_host, host, offset) \
+ msm_host->var_
-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 89
1 file changed, 89 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index bb11916..2524455 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc
From: Sayali Lokhande
For SDCC version 5.0.0 and higher, new compatible string
"qcom,sdhci-msm-v5" is added.
Based on the msm variant, pick the relevant variant data and
use it for register read/write to msm specific registers.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay
mmc: host: Register changes for sdcc V5
Vijay Viswanath (1):
mmc: sdhci-msm: Add msm version specific ops and data structures
.../devicetree/bindings/mmc/sdhci-msm.txt | 5 +-
drivers/mmc/host/sdhci-msm.c | 545 -
2 files changed, 423 insertio
.
Also defind new data structure to hold version specific Ops and register
addresses.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 112 +++
1 file changed, 112 insertions(+)
diff --git a/drivers/mmc/host
Added kcs device and lpc ctrl device to enable LPC clock in Facebook
Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 30 +++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-g5.dtsi | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8
On 12/12/18, 5:04 PM, "Joel Stanley" wrote:
On Thu, 13 Dec 2018 at 07:34, Vijay Khemka wrote:
>
> Added kcs device and lpc ctrl device to enable LPC clock in Facebook
> Tiogapass device tree.
As we're going to re-spin, it's a good
Added ADC and other sensor devices in Facebook Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 33 +--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
b
Added lpc ctrl device to enable LPC clock in Facebook
Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../boot/dts/aspeed-bmc-facebook-tiogapass.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
b/arch/arm
Added kcs device in Facebook Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
b/arch/arm/boot/dts/aspeed-bmc-facebook
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-g5.dtsi | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8
On 12/14/18, 12:42 PM, "Linux-aspeed on behalf of Vijay Khemka"
wrote:
On 12/14/18, 11:22 AM, "openbmc on behalf of Jae Hyun Yoo"
wrote:
Hi Vijay,
On 12/14/2018 10:11 AM, Vijay Khemka wrote:
> On 12/13/18, 2:56 PM
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-g5.dtsi | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8
Added kcs device in Facebook Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
b/arch/arm/boot/dts/aspeed-bmc-facebook
Added lpc ctrl device to enable LPC clock in Facebook
Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../boot/dts/aspeed-bmc-facebook-tiogapass.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
b/arch/arm
Added ADC and other sensor devices in Facebook Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
b
On 12/13/18, 2:56 PM, "Joel Stanley" wrote:
On Fri, 14 Dec 2018 at 06:23, Vijay Khemka wrote:
>
> Added ADC and other sensor devices in Facebook Tiogapass device tree.
>
> Signed-off-by: Vijay Khemka
> ---
> .../dts/aspeed-bmc-fac
On 12/14/18, 11:22 AM, "openbmc on behalf of Jae Hyun Yoo"
wrote:
Hi Vijay,
On 12/14/2018 10:11 AM, Vijay Khemka wrote:
> On 12/13/18, 2:56 PM, "Joel Stanley" wrote:
> > + oemname0 = "MB_P3V3"
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-g5.dtsi | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-g5.dtsi | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8
Added kcs device and lpc ctrl device to enable LPC clock in Facebook
Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 30 +++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
Please ignore this patch as it is duplicate. It is included in list of 2
patches I have sent just before.
On 12/10/18, 12:08 PM, "Vijay Khemka" wrote:
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-g5
Added ADC and other sensor devices in Facebook Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 33 +--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
b
Thanks Jay,
I will take care of your comments and send next version.
Regards
-Vijay
On 12/11/18, 10:40 AM, "Jae Hyun Yoo" wrote:
Hi Vijay,
On 12/10/2018 12:07 PM, Vijay Khemka wrote:
> Added kcs device support for lpc BMC.
>
> Signed-o
Added kcs device and lpc ctrl device to enable LPC clock in Facebook
Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 30 +++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-g5.dtsi | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8
Added kcs device support for lpc BMC.
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/aspeed-g5.dtsi | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8
Added kcs device and lpc ctrl device to enable LPC clock in Facebook
Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../dts/aspeed-bmc-facebook-tiogapass.dts | 30 +++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
Joel, Can you please take care of these patches merge.
On 12/17/18, 12:04 PM, "Vijay Khemka" wrote:
Added lpc ctrl device to enable LPC clock in Facebook
Tiogapass device tree.
Signed-off-by: Vijay Khemka
---
.../boot/dts/aspeed-bmc-facebook-tiogapass
Please merge these patches in upstream kernel.
Regards
-Vijay
On 12/20/18, 10:06 AM, "Linux-aspeed on behalf of Vijay Khemka"
wrote:
Joel, Can you please take care of these patches merge.
On 12/17/18, 12:04 PM, "Vijay Khemka" wrote:
Added lpc c
Thanks David
On 10/26/18, 10:36 AM, "David Miller" wrote:
From: Vijay Khemka
Date: Fri, 26 Oct 2018 17:19:49 +
> Do you have any timeline when it is going to open next or how do I
> know.
I always announce net-next openning and closing
machines.
This also adds an entry of tiogapass device tree file in Makefile
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/Makefile| 1 +
.../dts/aspeed-bmc-facebook-tiogapass.dts | 146 ++
2 files changed, 147 insertions(+)
create mode 100644 arch/arm
machines.
This also adds an entry of tiogapass device tree file in Makefile
Signed-off-by: Vijay Khemka
---
arch/arm/boot/dts/Makefile| 1 +
.../dts/aspeed-bmc-facebook-tiogapass.dts | 146 ++
2 files changed, 147 insertions(+)
create mode 100644 arch/arm
On 7/10/2018 4:37 PM, Adrian Hunter wrote:
On 21/06/18 15:23, Vijay Viswanath wrote:
Some controllers can have internal mechanism to inform the SW that it
is ready for voltage switching. For such controllers, changing voltage
before the HW is ready can result in various issues.
Add a quirk
On 7/17/2018 1:00 PM, Adrian Hunter wrote:
On 17/07/18 08:14, Vijay Viswanath wrote:
On 7/10/2018 4:37 PM, Adrian Hunter wrote:
On 21/06/18 15:23, Vijay Viswanath wrote:
Some controllers can have internal mechanism to inform the SW that it
is ready for voltage switching. For such
On 7/17/2018 2:12 PM, Adrian Hunter wrote:
On 17/07/18 11:40, Vijay Viswanath wrote:
On 7/17/2018 1:00 PM, Adrian Hunter wrote:
On 17/07/18 08:14, Vijay Viswanath wrote:
On 7/10/2018 4:37 PM, Adrian Hunter wrote:
On 21/06/18 15:23, Vijay Viswanath wrote:
Some controllers can have
On 7/17/2018 3:24 PM, Adrian Hunter wrote:
On 17/07/18 12:45, Vijay Viswanath wrote:
On 7/17/2018 2:12 PM, Adrian Hunter wrote:
On 17/07/18 11:40, Vijay Viswanath wrote:
On 7/17/2018 1:00 PM, Adrian Hunter wrote:
On 17/07/18 08:14, Vijay Viswanath wrote:
On 7/10/2018 4:37 PM
supported fifo bytes
Signed-off-by: Vijay Rai
Signed-off-by: Priyanka Jain
Signed-off-by: Poonam Aggrwal
---
Changes from V1:
- tx_loadsz is set to 63-bytes now earlier it was set to 36
- Added comment mentioning the erratum A-008006
- Updated PORT_MAX_8250 to 30
drivers/tty/serial/8250/8250_core.c
supported fifo bytes
Signed-off-by: Vijay Rai
Signed-off-by: Priyanka Jain
Signed-off-by: Poonam Aggrwal
---
drivers/tty/serial/8250/8250_core.c | 20 +++-
include/uapi/linux/serial_core.h|3 ++-
include/uapi/linux/serial_reg.h |3 ++-
3 files changed, 23 insertions
During probe check whether the vdd-io regulator of sdhc platform device
can support 1.8V and 3V and store this information as a capability of
platform device.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 36 +++-
1 file changed, 35 insertions
v2:
IO_PAD_PWR_SWITCH_EN will be set only if we have info regarding what
voltage is suported by the regulators.
Replaced regulator_list_voltage() API with
regulator_is_supported_voltage().
Krishna Konda (1):
mmc: sdhci-msm: support voltage pad switching
Vijay Viswanath (1):
for IO lines. So when power irq is
triggered for io high or io low, the driver should check the voltages
supported and set the pad accordingly.
Signed-off-by: Krishna Konda
Signed-off-by: Venkat Gopalakrishnan
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 65
mmc: sdhci-msm: support voltage pad switching
Vijay Viswanath (1):
mmc: sdhci-msm: Add support to store supported vdd-io voltages
drivers/mmc/host/sdhci-msm.c | 99 +++-
1 file changed, 97 insertions(+), 2 deletions(-)
--
Qualcomm India Private Limited,
During probe check whether the vdd-io regulator of sdhc platform device
can support 1.8V and 3V and store this information as a capability of
platform device.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 35 ++-
1 file changed, 34 insertions
for IO lines. So when power irq is
triggered for io high or io low, the driver should check the voltages
supported and set the pad accordingly.
Signed-off-by: Krishna Konda
Signed-off-by: Venkat Gopalakrishnan
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 64
With SDCC5, the MCI register space got removed and the offset/order of
several registers have changed. Based on SDCC version used and the register,
we need to pick the base address and offset.
Also power irq is a signal from controller to SW that it is ready for
voltage switch. So added support to
Change-Id: I0febfd9bb436a8eff20c20107dd4180c9781
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
---
.../devicetree/bindings/mmc/sdhci-msm.txt | 5 +-
drivers/mmc/host/sdhci-msm.c | 485 +++--
2 files changed, 365 insertions(+), 125
[vvisw...@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Vijay Viswanath
Change-Id: I3370a2411beec1f03cc5f102bf95cd816c60351e
---
drivers/mmc/host/sdhci.c | 11 ---
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdh
From: Sahitya Tummala
This is needed to get the current capabilities of vdd
regulator that is not managed by SDHCI driver.
Change-Id: I927c14b9890f1d672fe8a3e89d0b334f43463b36
Signed-off-by: Sahitya Tummala
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host
instead of relying on core layer voltage switching.
Change-Id: Iaa98686e71a5bfe0092c68e9ffa563b060c5ac60
Signed-off-by: Asutosh Das
Signed-off-by: Venkat Gopalakrishnan
Signed-off-by: Subhash Jadavani
Signed-off-by: Vijay Viswanath
---
.../devicetree/bindings/mmc/sdhci-msm.txt | 27
c: sdhci-msm: Define new Register address map
Documentation: sdhci-msm: Add new compatible string for SDCC v5
Vijay Viswanath (2):
mmc: sdhci-msm: Add msm version specific ops and data structures
mmc: host: Register changes for sdcc V5
.../devicetree/bindings/mmc/sdhci-msm.txt |
-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 89
1 file changed, 89 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index bb11916..4050c99 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc
.
Also defind new data structure to hold version specific Ops and
register addresses.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 77
1 file changed, 77 insertions(+)
diff --git a/drivers/mmc/host
From: Sayali Lokhande
For SDCC version 5.0.0 and higher, new compatible string
"qcom,sdhci-msm-v5" is added.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 7 ++-
1 file changed, 6 insertions(+), 1 deletio
Add support to use the new compatible string "qcom,sdhci-msm-v5".
Based on the msm variant, pick the relevant variant data and
use it for register read/write to msm specific registers.
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-m
Hi Joel,
Can you please apply this below patch to kernel 5.0.
Regards
-Vijay
On 3/18/19, 12:46 PM, "openbmc on behalf of Vijay Khemka"
wrote:
Hi Joel,
Can you please apply this patch as "
Documentation/devicetree/bindings/mfd/aspeed-lpc.txt" has already been appl
Hi Joel,
Please apply this patch.
Regards
-Vijay
On 3/18/19, 12:46 PM, "openbmc on behalf of Vijay Khemka"
wrote:
Hi Joel,
Please apply this patch.
Regards
-Vijay
On 3/5/19, 12:06 PM, "openbmc on behalf of Vijay Khemka"
wrote:
On 4/3/2021 8:21 AM, Ondrej Mosnacek wrote:
On Sat, Apr 3, 2021 at 4:33 PM Paul Moore wrote:
On Fri, Apr 2, 2021 at 6:35 PM Vijay Balakrishna
wrote:
Seeing oops in 5.4.83 sidtab_context_to_sid(). I checked with Tyler (copied),
he said it might be
https://lore.kernel.org/selinux
Hi Akashi,
On Fri, Sep 26, 2014 at 5:24 PM, AKASHI Takahiro
wrote:
> I tried to verify kgdb in vanilla kernel on fast model, but it seems that
> the single stepping with kgdb doesn't work correctly since its first
> appearance at v3.15.
>
> On v3.15, 'stepi' command after breaking the kernel at s
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