From: Hou Zhiqiang
On NXP Layerscape platforms, it results in SError in the
enumeration of the PCIe controller, which is not connecting
with an Endpoint device. And it doesn't make sense to
enumerate the Endpoints when the PCIe link is down. So this
patch added the link up check to avoid to fire
From: Xiaowei Bao
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Andrew Murray
---
V9:
- Rebase the patch since V8 patch was not accepted due to conflict.
- Correct the number of outbound windows.
- Add lables for EP
From: Hou Zhiqiang
Add PCIe Endpoint mode compatible string "fsl,lx2160ar2-pcie-ep"
Signed-off-by: Hou Zhiqiang
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
From: Hou Zhiqiang
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2
PCIe controller is integrated with different stride between PFs'
register address.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 7 +++
1 file changed, 7 insertions(+)
From: Hou Zhiqiang
This patch series is to add PCIe power management support for NXP
Layerscape platfroms.
Hou Zhiqiang (7):
PCI: dwc: Fix a bug of the case dw_pci->ops is NULL
PCI: layerscape: Change to use the DWC common link-up check function
dt-bindings: pci: layerscape-pci: Add a
From: Hou Zhiqiang
The dw_pci->ops may be a NULL, and fix it by adding one more check.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
Acked-by: Gustavo Pimentel
---
V2:
- Rebased the patch against the latest code.
drivers/pci/controller/dwc/pcie-designware.c | 14 +++---
1
From: Hou Zhiqiang
The current Layerscape PCIe driver directly uses the physical layer
LTSSM code to check the link-up state, which treats the > L0 states
as link-up. This is not correct, since there is not explicit map
between link-up state and LTSSM. So this patch changes to use the
DWC common
From: Hou Zhiqiang
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V2:
- No change.
From: Hou Zhiqiang
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
From: Hou Zhiqiang
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V2:
- No change.
From: Hou Zhiqiang
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.
Signed-off-by: Hou Zhiqiang
---
V2:
- Correct the order of the subject prefixes.
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file
From: Hou Zhiqiang
Add PME_Turn_Off/PME_TO_Ack handshake sequence, and finally
put the PCIe controller into D3 state after the L2/L3 ready
state transition process completion.
Signed-off-by: Hou Zhiqiang
---
V2:
- Change to use the common defines to access the RC configuration
registers.
From: Hou Zhiqiang
The current check will result in the multiple function device
fails to initialize. So fix the check by masking out the
multiple function bit.
Fixes: 0b24134f7888 ("PCI: dwc: Add validation that PCIe core is set to correct
mode")
Signed-off-by: Hou Zhiqiang
---
V2:
- Add
From: Hou Zhiqiang
The current Layerscape PCIe driver directly uses the physical layer
LTSSM code to check the link-up state, which treats the > L0 states
as link-up. This is not correct, since there is not explicit map
between link-up state and LTSSM. So this patch changes to use the
DWC common
From: Hou Zhiqiang
This patch series is to add PCIe power management support for NXP
Layerscape platfroms.
Hou Zhiqiang (7):
PCI: dwc: Fix a bug of the case dw_pci->ops is NULL
PCI: layerscape: Change to use the DWC common link-up check function
dt-bindings: pci: layerscape-pci: Add a
From: Hou Zhiqiang
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |
From: Hou Zhiqiang
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4
1
From: Hou Zhiqiang
Add PME_Turn_Off/PME_TO_Ack handshake sequence, and finally
put the PCIe controller into D3 state after the L2/L3 ready
state transition process completion.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/dwc/pci-layerscape.c | 384 ++-
From: Hou Zhiqiang
The dw_pci->ops may be a NULL, and fix it by adding one more check.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/controller/dwc/pcie-designware.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
From: Hou Zhiqiang
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.
Signed-off-by: Hou Zhiqiang
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Hou Zhiqiang
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
From: Xiaowei Bao
Add PCIe EP mode support for ls1088a and ls2088a, there are some
difference between LS1 and LS2 platform, so refactor the code of
the EP driver.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
---
V8:
- No change.
From: Xiaowei Bao
Add LS1088a in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in LS1088a.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Andrew Murray
---
V8:
- No change.
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2
From: Xiaowei Bao
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Andrew Murray
---
V8:
- s/pcie_ep/pcie-ep.
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff
From: Xiaowei Bao
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver
before, because the ls1046a platform don't support the MSIX feature
and msix_capable was always set to false.
Now that add the ls1088a platform with MSIX support, use the doorbell
method to support the MSIX
From: Xiaowei Bao
Each PF of EP device should have its own MSI or MSIX capabitily
struct, so create a dw_pcie_ep_func struct and move the msi_cap
and msix_cap to this struct from dw_pcie_ep, and manage the PFs
via a list.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V8:
- Put
From: Xiaowei Bao
The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
---
V8:
- No change.
From: Hou Zhiqiang
The commit 0a121f9bc3f5 ("misc: pci_endpoint_test: Use streaming DMA
APIs for buffer allocation") changed to use streaming DMA APIs, however,
dma_map_single() might not return a 4KB aligned address, so add the
default_data as driver data for Layerscape PCIe controllers to make
From: Xiaowei Bao
Fix some format issue of the code in EP driver.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Andrew Murray
---
V8:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Xiaowei Bao
Add compatible strings for ls1088a and ls2088a.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V8:
- No change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Xiaowei Bao
Add the doorbell mode of MSI-X in DWC EP driver.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Andrew Murray
---
V8:
- Add msix cap check.
.../pci/controller/dwc/pcie-designware-ep.c | 19 +++
From: Hou Zhiqiang
Add the PCIe EP multiple PF support for DWC and Layerscape, and use
a list to manage the PFs of each PCIe controller; add the doorbell
MSIX function for DWC; and refactor the Layerscape EP driver due to
some difference in Layercape platforms PCIe integration.
Rebased this
From: Xiaowei Bao
Add multiple PFs support for DWC, due to different PF have different
config space, we use func_conf_select callback function to access
the different PF's config space, the different chip company need to
implement this callback function when use the DWC IP core and intend
to
From: Xiaowei Bao
Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Andrew
From: Xiaowei Bao
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Andrew Murray
---
V10:
- Add a space between compatibles.
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++
1 file changed, 31
From: Hou Zhiqiang
The commit 6d2c89441571 ("PCI/ERR: Update error status after reset_link()")
overrode the 'status' returned by the error_detect() call back function,
which is depended on by the next step. This overriding makes the Endpoint
driver's required info (kept in the var status) lost,
From: Hou Zhiqiang
The pcie compatible string for LS1043A was lost, so add it.
Signed-off-by: Hou Zhiqiang
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
From: Hou Zhiqiang
Removed the compatible string "snps,dw-pcie" from FSL layerscape-pci compatible
string list.
Hou Zhiqiang (4):
doc/layerscape-pci: update the PCIe compatible strings
doc/layerscape-pci: removed unsuitable compatible string
dts/arm/ls1021a: Clean PCIe controller
From: Hou Zhiqiang
Removed the compatible string "snps,dw-pcie", it is for the reference
platform driver for PCI RC IP Protoyping Kits based on the ARC SDP,
so it is not suitable for all platform with designware PCIe controller,
and platform vendors have themselves' drivers.
The compatible
From: Hou Zhiqiang
Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: Hou Zhiqiang
---
arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi
From: Hou Zhiqiang
Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: Hou Zhiqiang
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
From: Hou Zhiqiang
The dw_pci->ops may be a NULL, and fix it by adding one more check.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
Acked-by: Gustavo Pimentel
---
V3:
- Rebased against the latest code base
drivers/pci/controller/dwc/pcie-designware-host.c | 2 +-
From: Hou Zhiqiang
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V3:
- Rebased against the latest code base
From: Hou Zhiqiang
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V3:
- Rebased against the latest code
From: Hou Zhiqiang
This patch series is to add PCIe power management support for NXP
Layerscape platfroms.
Hou Zhiqiang (7):
PCI: dwc: Fix a bug of the case dw_pci->ops is NULL
PCI: layerscape: Change to use the DWC common link-up check function
dt-bindings: pci: layerscape-pci: Add a
From: Hou Zhiqiang
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang
---
V3:
- Rebased against the latest code base
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
From: Hou Zhiqiang
The current Layerscape PCIe driver directly uses the physical layer
LTSSM code to check the link-up state, which treats the > L0 states
as link-up. This is not correct, since there is not explicit map
between link-up state and LTSSM. So this patch changes to use the
DWC common
From: Hou Zhiqiang
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.
Signed-off-by: Hou Zhiqiang
---
V3:
- Rebased against the latest code base
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file
From: Hou Zhiqiang
Add PME_Turn_Off/PME_TO_Ack handshake sequence, and finally
put the PCIe controller into D3 state after the L2/L3 ready
state transition process completion.
Signed-off-by: Hou Zhiqiang
---
V3:
- Rebased against the latest code base
From: Hou Zhiqiang
The current Layerscape PCIe driver directly uses the physical layer
LTSSM code to check the link-up state, which treats the > L0 states
as link-up. This is not correct, since there is not explicit map
between link-up state and LTSSM. So this patch changes to use the
DWC common
From: Hou Zhiqiang
This patch series is to add PCIe power management support for NXP
Layerscape platforms.
Hou Zhiqiang (6):
PCI: layerscape: Change to use the DWC common link-up check function
dt-bindings: pci: layerscape-pci: Add a optional property big-endian
arm64: dts: layerscape:
From: Hou Zhiqiang
Add PME_Turn_Off/PME_TO_Ack handshake sequence, and finally
put the PCIe controller into D3 state after the L2/L3 ready
state transition process completion.
Signed-off-by: Hou Zhiqiang
---
V5:
- Fix a typo of the parameter given to function dw_pcie_setup_rc()
From: Hou Zhiqiang
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang
---
V5:
- No change
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
From: Hou Zhiqiang
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.
Signed-off-by: Hou Zhiqiang
---
V5:
- No change
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff
From: Hou Zhiqiang
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V5:
- No change
From: Hou Zhiqiang
This patch series is to add PCIe power management support for NXP
Layerscape platforms.
Hou Zhiqiang (6):
PCI: layerscape: Change to use the DWC common link-up check function
dt-bindings: pci: layerscape-pci: Add a optional property big-endian
arm64: dts: layerscape:
From: Hou Zhiqiang
The current Layerscape PCIe driver directly uses the physical layer
LTSSM code to check the link-up state, which treats the > L0 states
as link-up. This is not correct, since there is not explicit map
between link-up state and LTSSM. So this patch changes to use the
DWC common
From: Hou Zhiqiang
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V5:
- No change
From: Hou Zhiqiang
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.
Signed-off-by: Hou Zhiqiang
---
V4:
- Rebased against the latest code base
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file
From: Hou Zhiqiang
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V4:
- Rebased against the latest code
From: Hou Zhiqiang
Add PME_Turn_Off/PME_TO_Ack handshake sequence, and finally
put the PCIe controller into D3 state after the L2/L3 ready
state transition process completion.
Signed-off-by: Hou Zhiqiang
---
V4:
- Rebased against the latest code base
From: Hou Zhiqiang
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V4:
- Rebased against the latest code base
From: Hou Zhiqiang
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang
---
V4:
- Rebased against the latest code base
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
From: Hou Zhiqiang
Currently the core struct dw_pcie includes both struct pcie_port
and dw_pcie_ep and the RC and EP platform drivers directly
includes the dw_pcie. So it results in a RC or EP platform driver
has 2 indirect parents pcie_port and dw_pcie_ep, but it doesn't
make sense let RC
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