On Mon, 7 Nov 2016, Moritz Fischer wrote:
> Add FPGA capabilities as a way to express the capabilities
> of a given FPGA manager.
>
> Removes code duplication by comparing the low-level driver's
> capabilities at the framework level rather than having each driver
> check for supported operations
On Mon, 7 Nov 2016, Moritz Fischer wrote:
Hi Moritz,
One nit below. Otherwise,
Acked-by: Alan Tull
Alan
> Expose FPGA capabilities to userland via sysfs.
>
> Add Documentation for currently supported capabilities
> that get exported via sysfs.
>
> Signed-off-by: Moritz Fischer
> Cc:
On Mon, 14 Nov 2016, Moritz Fischer wrote:
Hi Moritz,
> Hi Alan,
>
> On Mon, Nov 14, 2016 at 6:06 AM, atull wrote:
> > On Mon, 7 Nov 2016, Moritz Fischer wrote:
> >
> >> Add FPGA capabilities as a way to express the capabilities
> >> of a given FPGA mana
On Mon, 7 Nov 2016, Moritz Fischer wrote:
Hi Moritz,
This looks good. Probably the socfpga changes could get
folded into this patch (was patch 4/4) unless you thought of
a reason not to (after that patch is changed to see if the
MSEL bits are set to enable decrypt).
There also could be a uncomp
On Tue, 15 Nov 2016, Moritz Fischer wrote:
> Hi Dan,
> On Tue, Nov 15, 2016 at 1:54 AM, Dan Carpenter
> wrote:
> > This is a cut and paste bug. We had intended to check "sysmgr".
> >
> > Fixes: e5f8efa5c8bf ("ARM: socfpga: fpga bridge driver support")
> > Signed-off-by: Dan Carpenter
> Acked
On Thu, 10 Nov 2016, Greg Kroah-Hartman wrote:
> On Tue, Nov 01, 2016 at 02:14:22PM -0500, Alan Tull wrote:
> > This patch add of overlay notifications.
>
> Your crazy way of doing [ ] in the subject messed up git, please don't
> do that...
>
> Just do:
> [PATCH repost v21 01/11]
>
>
On Mon, 7 Nov 2016, Moritz Fischer wrote:
> Expose support for on the fly decryption of bitstreams.
> This needs no additional work or configuration,
> so just expose the new capability.
Hi Moritz,
When we talked about this, I was thinking about the arria10
support which I'd done more recently.
On Mon, 31 Oct 2016, Moritz Fischer wrote:
> Found a couple of issues, will resubmit after cleaning up. Feel free to add
> general feedback on the idea anyways in the meantime. Sorry for double post.
Hi Moritz,
This looks good and useful to me. One comment below.
>
> On Sun, Oct 30, 2016 at 1
On Mon, 24 Oct 2016, Joel Holdsworth wrote:
> The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
> and very regular structure, designed for low-cost, high-volume consumer
> and system applications.
>
> This patch adds support to the FPGA manager for configuring the SRAM of
>
On Tue, 25 Oct 2016, Joel Holdsworth wrote:
>
> > Hi Joel,
> >
> > Thanks for submitting your driver!
> >
> > I didn't see any huge problems, just minor things below...
> >
> > Alan
> >
>
> Hi Alan, Thanks for your feedback. I've implemented all your suggestions and
> I'll resubmit.
>
> I h
On Sat, 3 Dec 2016, Moritz Fischer wrote:
> On Fri, Dec 2, 2016 at 1:23 PM, Dinh Nguyen wrote:
> > Fix up these sparse warnings:
> >
> > drivers/fpga/fpga-mgr.c:189:21: warning: symbol '__fpga_mgr_get' was not
> > declared. Should it be static?
> > drivers/fpga/fpga-bridge.c:30:12: warning: symbo
On Wed, 30 Nov 2016, Joshua Clayton wrote:
Hi Clayton,
I just have a few minor one line changes below. Only one
is operational, I should have caught that earlier.
> cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
> interface on Altera Cyclone FPGAS.
>
> This is one of t
On Wed, 30 Nov 2016, Joshua Clayton wrote:
Hi Joshua,
The DT bindings will need Rob Herring's ack. The bitrev.h
changes will need Russell King's ack.
I've made some comments on patch 3/3 but it looks good to me
besides that.
Once we have those other acks, please submit your v4 including fixes
On Wed, 30 Nov 2016, Joshua Clayton wrote:
Hi Joshua,
> Hi Alan,
>
> On 11/30/2016 09:45 AM, atull wrote:
> > On Wed, 30 Nov 2016, Joshua Clayton wrote:
> >
> > Hi Clayton,
> >
> > I just have a few minor one line changes below. Only one
> > is o
On Mon, 14 Nov 2016, Rob Herring wrote:
> On Sun, Nov 06, 2016 at 07:49:21PM -0700, Joel Holdsworth wrote:
> > This adds documentation of the device tree bindings of the Lattice iCE40
> > FPGA driver for the FPGA manager framework.
> >
> > Signed-off-by: Joel Holdsworth
> > ---
> > .../bindings
On Sat, 29 Oct 2016, Joel Holdsworth wrote:
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
> b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 1992aa9..d64
On Fri, 4 Nov 2016, Joel Holdsworth wrote:
> The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
> and very regular structure, designed for low-cost, high-volume consumer
> and system applications.
>
> This patch adds support to the FPGA manager for configuring the SRAM of
> i
On Fri, 4 Nov 2016, Joel Holdsworth wrote:
> The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
> and very regular structure, designed for low-cost, high-volume consumer
> and system applications.
>
> This patch adds support to the FPGA manager for configuring the SRAM of
> i
On Mon, 1 Aug 2016, Rob Herring wrote:
> On Tue, Jul 12, 2016 at 02:36:41PM -0500, Alan Tull wrote:
> > Add bindings documentation for Altera SOCFPGA bridges:
> > * fpga2sdram
> > * fpga2hps
> > * hps2fpga
> > * lwhps2fpga
> >
> > Signed-off-by: Alan Tull
> > Signed-off-by: Matthew Gerlach
On Sun, 5 Jun 2016, Geert Uytterhoeven wrote:
> If NO_DMA=y:
>
> ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined!
>
> Add a dependency on HAS_DMA to fix this.
>
> Signed-off-by: Geert Uytterhoeven
> Reviewed-by: Moritz Fischer
> ---
> v2:
> - Add Reviewed-by,
> - Updated er
On Mon, 6 Jun 2016, Moritz Fischer wrote:
> Hi Alan, Geert
>
> On Mon, Jun 6, 2016 at 11:02 AM, atull wrote:
> > On Sun, 5 Jun 2016, Geert Uytterhoeven wrote:
> >
> >> If NO_DMA=y:
> >>
> >> ERROR: "bad_dma_ops" [drivers/fpga/zynq-fp
On Sun, 5 Jun 2016, Geert Uytterhoeven wrote:
> If NO_DMA=y:
>
> ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined!
>
> Add a dependency on HAS_DMA to fix this.
>
> Signed-off-by: Geert Uytterhoeven
> Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Thanks!
Alan
> ---
> v2:
>
On Tue, 12 Jul 2016, Alan Tull wrote:
> v18 has very minimal changes to address comments about the device
> tree bindings and device tree examples in the bindings document.
>
> The diffstat from v17 is:
> 4 files changed, 11 insertions(+), 18 deletions(-)
> If there are more changes, it would b
On Fri, 10 Jun 2016, Trent Piepho wrote:
> On Fri, 2016-02-05 at 15:30 -0600, at...@opensource.altera.com wrote:
> > Supports Altera SOCFPGA bridges:
> > * fpga2sdram
> > * fpga2hps
> > * hps2fpga
> > * lwhps2fpga
> >
> > Allows enabling/disabling the bridges through the FPGA
> > Bridge Frame
On Thu, 3 Mar 2016, Rob Herring wrote:
> On Wed, Mar 2, 2016 at 12:49 PM, atull wrote:
> > On Wed, 2 Mar 2016, Rob Herring wrote:
> >
> >> On Fri, Feb 26, 2016 at 3:44 PM, Alan Tull
> >> wrote:
> >> > This patch add of overlay notifications.
> &g
On Sat, 5 Mar 2016, Rob Herring wrote:
> On Thu, Feb 25, 2016 at 05:25:07PM -0600, Alan Tull wrote:
> > Add bindings documentation for Altera SOCFPGA bridges:
> > * fpga2sdram
> > * fpga2hps
> > * hps2fpga
> > * lwhps2fpga
> >
> > Signed-off-by: Alan Tull
> > Signed-off-by: Matthew Gerlach
On Mon, 22 Feb 2016, Pantelis Antoniou wrote:
> Hi Rob,
>
> > On Feb 22, 2016, at 04:55 , Rob Herring wrote:
> >
> > On Wed, Feb 17, 2016 at 11:41:25AM -0600, Alan Tull wrote:
> >> Add overlay callback functionality.
> >>
> >> When DT overlays are being added, some drivers/subsystems
> >> will
On Fri, 5 Feb 2016, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> v16 Refactors the FPGA Area and FPGA Bus into single thing called an
> FPGA Region and eliminates using simple-bus. I'm using the word
> "region" as it's a term is used in the literature of both the major
> FPGA manufa
On Thu, 11 Feb 2016, Rob Herring wrote:
> On Thu, Feb 11, 2016 at 2:49 PM, atull wrote:
> > On Fri, 5 Feb 2016, at...@opensource.altera.com wrote:
> >
> >> From: Alan Tull
> >>
> >> v16 Refactors the FPGA Area and FPGA Bus into single thing called an
&g
On Thu, 11 Feb 2016, atull wrote:
> On Thu, 11 Feb 2016, Rob Herring wrote:
>
> > On Thu, Feb 11, 2016 at 2:49 PM, atull wrote:
> > > On Fri, 5 Feb 2016, at...@opensource.altera.com wrote:
> > >
> > >> From: Alan Tull
> > >>
> > &
On Tue, 1 Mar 2016, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer
> ---
> include/linux/fpga/fpga-mgr.h | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
> index 0940bf4..8064f1b 100644
> --- a/incl
On Wed, 2 Mar 2016, Rob Herring wrote:
> On Fri, Feb 26, 2016 at 3:44 PM, Alan Tull
> wrote:
> > This patch add of overlay notifications.
> >
> > When DT overlays are being added, some drivers/subsystems
> > need to see device tree overlays before the changes go into
> > the live tree.
> >
> > T
On Wed, 23 Sep 2015, Dan Carpenter wrote:
> On Wed, Sep 23, 2015 at 03:23:54PM +0200, Pavel Machek wrote:
> > > > +int fpga_mgr_firmware_load(struct fpga_manager *mgr, u32 flags,
> > > > + const char *image_name)
> > > > +{
> > > > + struct device *dev = &mgr->dev;
>
Hi Josh,
Thanks for the review. This is all at the tail end of a long
(>2 years) discussion on this. I hope that the way this has
shaped out still meets the needs of the people who have been
in this discussion the most and have had the strongest feelings
(due to being current users of FPGAs unde
On Wed, 23 Sep 2015, Josh Cartwright wrote:
> On Wed, Sep 23, 2015 at 12:10:13PM -0500, atull wrote:
> > On Tue, 22 Sep 2015, Josh Cartwright wrote:
> [..]
> > > > +struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
> > > > +{
>
On Thu, 24 Sep 2015, Dan Carpenter wrote:
> Of course, the maintainer gets the last word regardless of what anyone
> else thinks.
>
> Generally, minimal code is better. Trying to future proof code is a
> waste of time because you can't predict what will happen in the future.
> It's way more like
From: Alan Tull
Add a document on the new FPGA manager core.
Signed-off-by: Alan Tull
---
v9: initial version where this patch was added
v10: requested cleanups to formatting and otherwise
s/fpga/FPGA/g
rewrite implementation section to not reference socfpga.c by name
other rew
From: Alan Tull
API to support programming FPGA's.
The following functions are exported as GPL:
* fpga_mgr_buf_load
Load fpga from image in buffer
* fpga_mgr_firmware_load
Request firmware and load it to the FPGA.
* fpga_mgr_register
* fpga_mgr_unregister
FPGA device drivers can be ad
From: Alan Tull
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull
Acked-by: Michal Simek
Acked-by: Moritz Fischer
---
v2: fpga_manager struct now contains struct device
fpga_manager_register parameters now take device
v3
From: Alan Tull
This patch set adds the FPGA manager core which exports API functions that
write an image to a FPGA
I'm holding off on the DT overlay support a little for now.
The core's API is minimal to start with: only 6 functions. This gives a
manufacturer-agnostic interface for programmin
From: Alan Tull
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move document to drivers/staging/fpga/Documentation/ABI
v6 :
From: Alan Tull
Add documentation for new FPGA bridge class's sysfs interface.
Signed-off-by: Alan Tull
---
Documentation/ABI/testing/sysfs-class-fpga-bridge | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-class-fpga-bridge
diff --git a
From: Alan Tull
Add bindings documentation for Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpga
Signed-off-by: Alan Tull
Signed-off-by: Matthew Gerlach
Signed-off-by: Dinh Nguyen
---
v2: separate into 2 documents for the 2 drivers
v12: bump version to line up with
From: Alan Tull
For v14 I'm dropping the concept of "simple-fpga-bus" for "fpga-area"
with reworked bindings.
An FPGA Area describes a section of an FPGA including the FPGA image needed to
program it and the hardware contained once it is programmed. The intent is
to support Device Tree controll
From: Alan Tull
New bindings document for FPGA Area for reprogramming
FPGA's under Device Tree control
Signed-off-by: Alan Tull
---
v9: initial version added to this patchset
v10: s/fpga/FPGA/g
replace DT overlay example with slightly more complicated example
move to staging/simple-f
From: Alan Tull
FPGA Areas support programming FPGA under control of the
Device Tree.
When a Device Tree Overlay containing a FPGA Area is
applied, the FPGA Area will be probed and will:
* check to see if there is an image to program to a FPGA
* get references to the FPGA manager and bridges i
From: Alan Tull
Add a document spelling out usage of the FPGA Area for
reprogramming FPGA's under Device Tree control.
Signed-off-by: Alan Tull
---
v9: Initial version of this patch in patchset
v10: s/fpga/FPGA/g
improve formatting
some rewriting
move to staging/simple-fpga-bus
From: Alan Tull
This framework adds API functions for enabling/
disabling FPGA bridges under kernel control.
This allows the Linux kernel to disable FPGA bridges
during FPGA reprogramming and to enable FPGA bridges
when FPGA reprogramming is done. This framework is
be manufacturer-agnostic, all
From: Alan Tull
Supports Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpga
Allows enabling/disabling the bridges through the FPGA
Bridge Framework API functions.
The fpga2sdram driver only supports enabling and disabling
of the ports that been configured early on. Thi
On Fri, 11 Dec 2015, Rob Herring wrote:
Hi Rob,
> > +Device Tree Example: Partial Reconfiguration with no Bridges
> > +
> > +
> > +Live Device Tree contains:
> > + fpgamgr@0 {
>
> Unit address should be ffd03000 here.
I'll clean up t
From: Alan Tull
v16 Refactors the FPGA Area and FPGA Bus into single thing called an
FPGA Region and eliminates using simple-bus. I'm using the word
"region" as it's a term is used in the literature of both the major
FPGA manufacturors.
Changes for v16:
* Refactor the FPGA Area and FPGA Bus int
From: Alan Tull
Add documentation for new FPGA bridge class's sysfs interface.
Signed-off-by: Alan Tull
--
v15: Document added in v15 of patch set
v16: No change to this patch in v16 of patch set
---
Documentation/ABI/testing/sysfs-class-fpga-bridge | 11 +++
1 file changed, 11 inser
From: Alan Tull
FPGA Regions support programming FPGA under control of the Device
Tree.
Signed-off-by: Alan Tull
---
v9: initial version (this patch added during rest of patchset's v9)
v10: request deferral if fpga mgr or bridges not available yet
cleanup as fpga manager core goes into th
From: Alan Tull
This framework adds API functions for enabling/
disabling FPGA bridges under kernel control.
This allows the Linux kernel to disable FPGA bridges
during FPGA reprogramming and to enable FPGA bridges
when FPGA reprogramming is done. This framework is
be manufacturer-agnostic, all
From: Alan Tull
Supports Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpga
Allows enabling/disabling the bridges through the FPGA
Bridge Framework API functions.
The fpga2sdram driver only supports enabling and disabling
of the ports that been configured early on. Thi
From: Alan Tull
Add bindings documentation for Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpga
Signed-off-by: Alan Tull
Signed-off-by: Matthew Gerlach
Signed-off-by: Dinh Nguyen
---
v2: separate into 2 documents for the 2 drivers
v12: bump version to line up with
From: Alan Tull
New bindings document for FPGA Region to support programming
FPGA's under Device Tree control
Signed-off-by: Alan Tull
Signed-off-by: Moritz Fischer
---
v9: initial version added to this patchset
v10: s/fpga/FPGA/g
replace DT overlay example with slightly more complicated
On Fri, 5 Feb 2016, Josh Cartwright wrote:
> Hey Alan-
>
> First off, thanks for all of your (and others') work on this.
>
> On Fri, Feb 05, 2016 at 03:29:58PM -0600, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > New bindings document for FPGA Region to support programming
> >
On Mon, 25 Jan 2016, Rob Herring wrote:
> On Fri, Jan 22, 2016 at 6:07 PM, Moritz Fischer
> wrote:
> > On Fri, Jan 22, 2016 at 5:37 PM, atull wrote:
> >> On Fri, 22 Jan 2016, Moritz Fischer wrote:
> >>
> >>> Alan,
> >>>
> >>> O
On Mon, 25 Jan 2016, Rob Herring wrote:
> On Wed, Jan 20, 2016 at 01:24:22PM -0600, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > New bindings document for FPGA Area for reprogramming
> > FPGA's under Device Tree control
> >
> > Signed-off-by: Alan Tull
> > ---
> > v9: initia
On Mon, 17 Oct 2016, Alan Tull wrote:
> +/**
> + * of_fpga_bridge_get - get an exclusive reference to a fpga bridge
> + *
> + * @np: node pointer of a FPGA bridge
> + * @info: fpga image specific information
> + *
> + * Return fpga_bridge struct if successful.
> + * Return -EBUSY if someone alread
On Thu, 29 Sep 2016, Moritz Fischer wrote:
> Hi Alan,
>
> On Wed, Sep 28, 2016 at 11:22 AM, Alan Tull
> wrote:
>
> > +static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv,
> > + u32 count)
> > +{
> > + u32 val;
> > + unsig
On Mon, 17 Oct 2016, Moritz Fischer wrote:
> Hi Alan,
>
> couple of nits inline and some comments on ordering the patches ;-)
>
> On Mon, Oct 17, 2016 at 6:09 PM, Alan Tull
> wrote:
> > This patch adds a minor change in the FPGA Mangager API
>
> s/Mangager/Manager/
Yup!
>
> > to hold infor
On Tue, 18 Oct 2016, Rob Herring wrote:
> On Mon, Oct 17, 2016 at 11:09:34AM -0500, Alan Tull wrote:
> > Add bindings document for the Altera Freeze Bridge. A Freeze
> > Bridge is used to gate traffic to/from a region of a FPGA
> > such that that region can be reprogrammed. The Freeze Bridge
> >
On Tue, 18 Oct 2016, Moritz Fischer wrote:
> On Mon, Oct 17, 2016 at 11:09:41AM -0500, Alan Tull wrote:
> > Add low level driver to support reprogramming FPGAs for Altera
> > SoCFPGA Arria10.
> >
> > Signed-off-by: Alan Tull
>
> Reviewed-by: Moritz Fischer
> > +
> > +MODULE_AUTHOR("Alan Tull
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