[PATCH 06/14] clocksource/drivers/c-sky: fixup qemu fail to bootup sometimes.

From: Guo Ren Timer startup must after timer_irq_enable. For qemu, timer tick irq hanppens but irq not enable, so it will cause qemu boot failed. Signed-off-by: Guo Ren Tested-by: Liu Zhiwei --- drivers/clocksource/timer-mp-csky.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dif

[PATCH 13/14] clocksource/drivers/c-sky: fixup ftrace call-graph panic

From: Guo Ren We must add notrace on sched_clock_read, because it's called by ftrace_graph_caller. Signed-off-by: Guo Ren --- drivers/clocksource/timer-mp-csky.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-mp-csky.c b/drivers/clocksource/timer

[PATCH 01/14] csky: fixup abiv2 mmap(... O_SYNC) failed.

From: Guo Ren Glibc function mmap(... O_SYNC) will make page to _PAGE_UNCACHE + _PAGE_SO and strong-order page couldn't support unalignment access. So remove _PAGE_SO from _PAGE_UNCACHE, also sync abiv1 with the macro of _PAGE_SO. Signed-off-by: Guo Ren Reported-by: Liu Renwei Tested-by: Yuan

[PATCH 02/14] csky: bugfix gdb coredump error.

From: Guo Ren In gdb/bfd elf32-csky.c, csky_elf_grok_prstatus() use fixed size of elf_prstatus. It's 148 for abiv1 and 220 for abiv2, the size is enough for coredump and no need full sizeof(struct pt_regs). Signed-off-by: Guo Ren Reported-by: Lu Baoquan Reported-by: Liu Mao --- arch/csky/inc

[PATCH 03/14] csky: fixup remove vdsp implement for kernel.

From: Guo Ren The vr regs for vdsp only saved in task_switch not in every exception trap-in. The memcpy with vdsp instructions will destroy the vr regs for user space applications. Signed-off-by: Guo Ren --- arch/csky/abiv2/memcpy.S | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-)

[PATCH 04/14] csky: remove syscall_exit_work

From: Guo Ren Remove syscall_exit_work and union all to ret_from_exception. Signed-off-by: Guo Ren --- arch/csky/kernel/entry.S | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/arch/csky/kernel/entry.S b/arch/csky/kernel/entry.S index 79f92b8..2b4a851 10064

[PATCH 05/14] csky: fixup save hi,lo,dspcr regs in switch_stack.

From: Guo Ren HI, LO, DSPCR registers are 807/810 related regs and no need for 610/860. All of the regs must be saved in pt_regs and switch_stack. This patch fixup saving dspcr reg in switch_stack and pt_regs. Signed-off-by: Guo Ren --- arch/csky/abiv1/inc/abi/switch_context.h | 17 +++

[PATCH 07/14] csky: CPU-hotplug supported for SMP

From: Guo Ren This is a simple implement of CPU-hotplug for power saving. CPU use wait instruction to enter power saving mode and waiting for IPI wakeup signal. Signed-off-by: Guo Ren --- arch/csky/Kconfig | 9 ++ arch/csky/include/asm/smp.h | 4 +++ arch/csky/kernel/smp.c

[PATCH 08/14] csky: stacktrace supported.

From: Guo Ren The gcc option "-mbacktrace" will push fp(r8),lr into stack and we could unwind the stack with: fp = *fp lr = (unsigned int *)fp[1] Signed-off-by: Guo Ren --- arch/csky/Kconfig | 3 ++ arch/csky/Makefile | 4 +++ arch/csky/incl

[PATCH 09/14] csky: optimize kernel panic print.

From: Guo Ren Use STACKTRACE to optimize panic print more pretty and align registers printing. Signed-off-by: Guo Ren --- arch/csky/kernel/dumpstack.c | 59 ++-- arch/csky/kernel/ptrace.c| 34 ++--- arch/csky/mm/fault.c |

[PATCH 12/14] csky: ftrace call graph supported.

From: Guo Ren With csky-gcc -pg -mbacktrace, ftrace call graph supported. Signed-off-by: Guo Ren --- arch/csky/Kconfig | 1 + arch/csky/abiv2/mcount.S | 116 ++--- arch/csky/include/asm/ftrace.h | 6 ++- arch/csky/kernel/ftrace.c

[PATCH 11/14] csky: basic ftrace supported

From: Guo Ren When gcc with -pg, it'll add _mcount stub in every function. We need implement the _mcount in kernel and ftrace depends on stackstrace. To do: call-graph, dynamic ftrace Signed-off-by: Guo Ren --- arch/csky/Kconfig | 1 + arch/csky/abiv2/Makefile | 1 + arch

[PATCH 14/14] csky: Add EM_CSKY_OLD 39

From: Guo Ren C-SKY historically used 39, the same value as MCORE, from which the architecture was derived. C-SKY binutils support both EM_CSKY and EM_CSKY_OLD, confirmed by binutils:include/elf/common.h Signed-off-by: Guo Ren --- arch/csky/include/asm/elf.h | 4 +++- 1 file changed, 3 insert

[PATCH 10/14] csky: remove unused members in processor.h

From: Guo Ren Cleanup struct cpuinfo_csky and struct thread_struct, remove all esp0 related code. We could get pt_regs from sp and backtrace could use fp in switch_stack. Signed-off-by: Guo Ren --- arch/csky/include/asm/processor.h | 12 arch/csky/kernel/asm-offsets.c| 1 - a

[PATCH] csky: Add perf support for C-SKY

From: Guo Ren This adds basic perf support for all C-SKY CPUs. Hardware events are only supported by 807/810/860. Signed-off-by: Guo Ren --- arch/csky/Kconfig | 16 +- arch/csky/include/asm/perf_event.h |7 + arch/csky/kernel/Makefile |1 + arch/csky/kernel/

[GIT PULL] csky patches for the 4.21 merge window

Hi Linus, The following changes since commit 7566ec393f4161572ba6f11ad5171fd5d59b0fbd: Linux 4.20-rc7 (2018-12-16 15:46:55 -0800) are available in the git repository at: g...@github.com:c-sky/csky-linux.git tags/csky-for-linus-4.21 for you to fetch changes up to f50fd2d8524c15b08da9e7e9d84

[PATCH] Documentation/features: Add csky kernel features

From: Guo Ren core/ cBPF-JIT : TODO | core/ eBPF-JIT : TODO | core/ generic-idle-thread : ok | core/ jump-labels : TODO | core/ tracehook: ok | debug/ KASAN: TODO | debug/ gcov-profile-all

[PATCH V12 00/14] riscv: Add Native/Paravirt qspinlock support

From: Guo Ren patch[1 - 8]: Native qspinlock patch[9 -14]: Paravirt qspinlock This series based on: - v6.7-rc7 - Rework & improve riscv cmpxchg.h and atomic.h https://lore.kernel.org/linux-riscv/20230810040349.92279-2-leob...@redhat.com/ You can directly try it: https://github.com/guore

[PATCH V12 01/14] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock

From: Guo Ren The arch_spinlock_t of qspinlock has contained the atomic_t val, which satisfies the ticket-lock requirement. Thus, unify the arch_spinlock_t into qspinlock_types.h. This is the preparation for the next combo spinlock. Reviewed-by: Leonardo Bras Suggested-by: Arnd Bergmann Link:

[PATCH V12 02/14] asm-generic: ticket-lock: Add separate ticket-lock.h

From: Guo Ren Add a separate ticket-lock.h to include multiple spinlock versions and select one at compile time or runtime. Reviewed-by: Leonardo Bras Suggested-by: Arnd Bergmann Link: https://lore.kernel.org/linux-riscv/cak8p3a2rnz9mqqhn6-e0cguuv9rntrelfdxt_weid7fxh7f...@mail.gmail.com/ Sign

[PATCH V12 03/14] riscv: errata: Move errata vendor func-id into vendorid_list.h

From: Guo Ren Move errata vendor func-id definitions from errata_list into vendorid_list.h. Unifying these definitions is also for following rwonce errata implementation. Suggested-by: Leonardo Bras Link: https://lore.kernel.org/linux-riscv/zqlfj1cmq8pao...@redhat.com/ Signed-off-by: Guo Ren S

[PATCH V12 04/14] riscv: qspinlock: errata: Add ERRATA_THEAD_WRITE_ONCE fixup

From: Guo Ren The early version of T-Head C9xx cores has a store merge buffer delay problem. The store merge buffer could improve the store queue performance by merging multi-store requests, but when there are not continued store requests, the prior single store request would be waiting in the st

[PATCH V12 05/14] riscv: qspinlock: Add basic queued_spinlock support

From: Guo Ren The requirements of qspinlock have been documented by commit: a8ad07e5240c ("asm-generic: qspinlock: Indicate the use of mixed-size atomics"). Although RISC-V ISA gives out a weaker forward guarantee LR/SC, which doesn't satisfy the requirements of qspinlock above, it won't prevent

[PATCH V12 06/14] riscv: qspinlock: Introduce combo spinlock

From: Guo Ren Combo spinlock could support queued and ticket in one Linux Image and select them during boot time via command line. Here is the func size (Bytes) comparison table below: TYPE: COMBO | TICKET | QUEUED arch_spin_lock : 106 | 60 | 50 arch_spin_unloc

[PATCH V12 07/14] riscv: qspinlock: Add virt_spin_lock() support for VM guest

From: Guo Ren Add a static key controlling whether virt_spin_lock() should be called or not. When running on bare metal set the new key to false. The VM guests should fall back to a Test-and-Set spinlock, because fair locks have horrible lock 'holder' preemption issues. The virt_spin_lock_key wo

[PATCH V12 08/14] riscv: qspinlock: Force virt_spin_lock for KVM guests

From: Guo Ren Force to enable virt_spin_lock when KVM guest, because fair locks have horrible lock 'holder' preemption issues. Suggested-by: Leonardo Bras Link: https://lkml.kernel.org/kvm/zqk9-tn2mepxl...@redhat.com/ Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/s

[PATCH V12 09/14] RISC-V: paravirt: Add pvqspinlock KVM backend

From: Guo Ren Add the files functions needed to support the SBI PVLOCK (paravirt qspinlock kick_cpu) extension. Implement kvm_sbi_ext_pvlock_kick_- cpu(), and we only need to call the kvm_vcpu_kick() and bring target_vcpu from the halt state. No irq raised, no other request, just a pure vcpu_kick

[PATCH V12 10/14] RISC-V: paravirt: Add pvqspinlock frontend skeleton

From: Guo Ren Using static_call to switch between: native_queued_spin_lock_slowpath()__pv_queued_spin_lock_slowpath() native_queued_spin_unlock() __pv_queued_spin_unlock() Finish the pv_wait implementation, but pv_kick needs the SBI definition of the next patches. Reviewed-by:

[PATCH V12 11/14] RISC-V: paravirt: pvqspinlock: Add SBI implementation

From: Guo Ren Implement pv_kick with SBI guest implementation, and add SBI_EXT_PVLOCK extension detection. The backend part is in the KVM pvqspinlock patch. Reviewed-by: Leonardo Bras Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/sbi.h | 6 ++ arch/ri

[PATCH V12 12/14] RISC-V: paravirt: pvqspinlock: Add nopvspin kernel parameter

From: Guo Ren Disables the qspinlock slow path using PV optimizations which allow the hypervisor to 'idle' the guest on lock contention. Reviewed-by: Leonardo Bras Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/riscv/kernel/qsp

[PATCH V12 13/14] RISC-V: paravirt: pvqspinlock: Add kconfig entry

From: Guo Ren Add kconfig entry for paravirt_spinlock, an unfair qspinlock virtualization-friendly backend, by halting the virtual CPU rather than spinning. Reviewed-by: Leonardo Bras Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 12 arch/riscv/k

[PATCH V12 14/14] RISC-V: paravirt: pvqspinlock: Add trace point for pv_kick/wait

From: Guo Ren Add trace point for pv_kick&wait, here is the output: ls /sys/kernel/debug/tracing/events/paravirt/ enable filter pv_kick pv_wait cat /sys/kernel/debug/tracing/trace entries-in-buffer/entries-written: 33927/33927 #P:12 _-=> irqs-off/BH

[PATCH] set_thread_area.2: Add C-SKY document

From: Guo Ren C-SKY only needs set_thread_area, no need for get_thread_area, the same as MIPS. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- man2/set_thread_area.2 | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/man2/set_thread_area.2 b/man2/set_thread_area.

[PATCH 1/3] nds32: Cleanup deprecated function strlen_user

From: Guo Ren $ grep strlen_user * -r arch/csky/include/asm/uaccess.h:#define strlen_user(str) strnlen_user(str, 32767) arch/csky/lib/usercopy.c: * strlen_user: - Get the size of a string in user space. arch/ia64/lib/strlen.S: // Please note that in the case of strlen() as opposed to strlen_us

[PATCH 2/3] nios2: Cleanup deprecated function strlen_user

From: Guo Ren $ grep strlen_user * -r arch/csky/include/asm/uaccess.h:#define strlen_user(str) strnlen_user(str, 32767) arch/csky/lib/usercopy.c: * strlen_user: - Get the size of a string in user space. arch/ia64/lib/strlen.S: // Please note that in the case of strlen() as opposed to strlen_us

[PATCH 3/3] riscv: Cleanup deprecated function strlen_user

From: Guo Ren $ grep strlen_user * -r arch/csky/include/asm/uaccess.h:#define strlen_user(str) strnlen_user(str, 32767) arch/csky/lib/usercopy.c: * strlen_user: - Get the size of a string in user space. arch/ia64/lib/strlen.S: // Please note that in the case of strlen() as opposed to strlen_us

[GIT PULL] csky fixes for v5.1-rc7

The following changes since commit 085b7755808aa11f78ab9377257e1dad2e6fa4bb: Linux 5.1-rc6 (2019-04-21 10:45:57 -0700) are available in the git repository at: https://github.com/c-sky/csky-linux.git tags/csky-for-linus-5.1-rc7 for you to fetch changes up to a691f3334d58b833e41d56de1b9820e68

[PATCH] csky: Add non-uapi asm/ptrace.h namespace

From: Guo Ren Move #ifdef __KERNEL__ code in the uapi namespace to non-uapi include/asm/ptrace.h namespace and remove #ifdef __KERNEL__ in include/asm/ptrace.h. Seperate ptrace.h in uapi and non-uapi is more common and clear. Signed-off-by: Guo Ren Cc: Dmitry V. Levin --- arch/csky/include/as

[PATCH 2/3] csky: Reconstruct signal.c and entry.S

From: Guo Ren Linux kernel has provided some apis for arch signal's implementation. For example: restore_saved_sigmask() set_current_blocked() restore_altstack() But in last version of csky signal.c didn't use them and some codes are confusing, so reconstruct signal.c wit

[PATCH 1/3] csky: Use in_syscall & forget_syscall instead of r11_sig

From: Guo Ren We could use regs->sr 16-24 bits to detect syscall: VEC_TRAP0 and r11_sig is no necessary for current implementation. In this patch, we implement the in_syscall and forget_syscall which are inspired from arm & nds32, but csky pt_regs has no syscall_num element and we just set zero

[PATCH 3/3] riscv/signal: Fixup additional syscall restarting

From: Guo Ren The function of do_notify_resume called by entry.S could be entered in loop when SIGPENDING was setted again before sret. So we must add prevent code to make syscall restart (regs->sepc -= 0x4) or it may re-execute unexpected instructions. Just like in_syscall & forget_syscall used

[PATCH] csky: Support dynamic start physical address

From: Guo Ren Before this patch csky-linux need CONFIG_RAM_BASE to determine start physical address. Now we use phys_offset variable to replace the macro of PHYS_OFFSET and we setup phys_offset with real physical address which is determined during startup in head.S. With this patch we needn't re

[PATCH V2] csky: Add perf_arch_fetch_caller_regs support

From: Mao Han In trace events as tracepoints context are not able to be retrieve with task_pt_regs. Without arch caller regs support the pt_regs context will be all zero, perf can not parsing the callchain and resolving the symbols correctly, some time will even get into deadlock while handling t

[PATCH] csky: Fixup wrong update_mmu_cache implementation

From: Guo Ren In our stress test, we found some crash problem caused by: if (!(vma->vm_flags & VM_EXEC)) return; in update_mmu_cache(). Seems current update_mmu_cache implementation is wrong and we retread to the conservative implementation. Also the usage of kmap_atomic in update_mmu

[PATCH 2/2] drivers/clocksource: Fixup csky,mpintc compile error with CPU_CK610

From: Guo Ren The timer-mp-csky.c only could support CPU_CK860 and it will compile error with CPU_CK610. Signed-off-by: Guo Ren Cc: Daniel Lezcano Cc: Thomas Gleixner --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconf

[PATCH 1/2] drivers/irqchip: Fixup csky,mpintc compile error with CPU_CK610

From: Guo Ren The irq-csky-mpintc.c only could support CPU_CK860 and it will compile error with CPU_CK610. Signed-off-by: Guo Ren Cc: Marc Zyngier --- drivers/irqchip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig

[PATCH v2 1/2] drivers/irqchip: Fixup csky,mpintc compile error with CPU_CK610

From: Guo Ren The irq-csky-mpintc.c only could support CPU_CK860 and it will compile error with CPU_CK610. It has beed selected in arch/csky/Kconfig Signed-off-by: Guo Ren Cc: Marc Zyngier --- drivers/irqchip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- v2: Drop the str

[PATCH v2 2/2] drivers/clocksource: Fixup csky,mptimer compile error with CPU_CK610

From: Guo Ren The timer-mp-csky.c only could support CPU_CK860 and it will compile error with CPU_CK610. It has been selected in arch/csky/Kconfig. Signed-off-by: Guo Ren Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 inser

[PATCH 01/13] csky: remove unusued thread_saved_pc and *_segments functions/macros

From: Tobias Klauser These are used nowhere in the tree (except for some architectures which define them for their own use) and were already removed for other architectures in: commit 6474924e2b5d ("arch: remove unused macro/function thread_saved_pc()") commit c17c02040bf0 ("arch: remove unused

[PATCH 02/13] csky: Add SECCOMP_FILTER supported

From: Guo Ren secure_computing() is called first in syscall_trace_enter() so that a system call will be aborted quickly without doing succeeding syscall tracing if seccomp rules want to deny that system call. TODO: - Update https://github.com/seccomp/libseccomp csky support Signed-off-by: Guo

[PATCH 00/13] Update csky subsystem for linux-5.9-rc1

From: Guo Ren Here are the patchess for the next linux version. Add features (seccomp-filter, err-injection, top-down&random mmap-layout, irq_work, show_ipi, context-tracking), and fixup (kprobe_on_ftrace, ...), Optimize (fault print, ...). I think we'll finish most of features for arch/csky thi

[PATCH 04/13] csky: Fixup duplicated restore sp in RESTORE_REGS_FTRACE

From: Guo Ren There is no user return for RESTORE_REGS_FTRACE, so it's no need to save sp into ss0 as RESTORE_REGS_ALL. Signed-off-by: Guo Ren Cc: Arnd Bergmann --- arch/csky/abiv2/inc/abi/entry.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/csky/abiv2/inc/abi/entry.h b/arch/csk

[PATCH 13/13] csky: Add context tracking support

From: Guo Ren This patch support context tracking with no hz full. Here is the test result with dynticks-testing (see tick_stop): cat /sys/kernel/debug/tracing/per_cpu/cpu0/trace tracer: nop entries-in-buffer/entries-written: 356/356 #P:1 _-=> irqs-off

[PATCH 05/13] csky: Fixup kprobes handler couldn't change pc

From: Guo Ren The "Changing Execution Path" section in the Documentation/kprobes.txt said: Since kprobes can probe into a running kernel code, it can change the register set, including instruction pointer. Signed-off-by: Guo Ren Cc: Arnd Bergmann --- arch/csky/abiv2/mcount.S | 4 +++- 1 file

[PATCH 12/13] csky: Add arch_show_interrupts for IPI interrupts

From: Guo Ren Here is the result: cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 15: 1348 1299952 1076 C-SKY SMP Intc 15 IPI Interrupt 16: 1203 1825 1598 1307 C-SKY SMP Intc 16 csky_mp_timer 43:292

[PATCH 06/13] csky: Add support for function error injection

From: Guo Ren Inspired by the commit 42d038c4fb00 ("arm64: Add support for function error injection"), this patch supports function error injection for csky. This patch mainly support two functions: one is regs_set_return_value() which is used to overwrite the return value; the another function

[PATCH 08/13] csky: Use top-down mmap layout

From: Guo Ren Follow riscv mmap layout with commit "riscv: make mmap allocation top-down by default (54c95a11cc1b)". Before: cat /proc/self/maps 8000-000dc000 r-xp fe:00 17 /bin/busybox 000dc000-000dd000 r--p 000d3000 fe:00 17 /bin/busybox 000dd000-000de000 rw-p 000

[PATCH 07/13] csky: Optimize the trap processing flow

From: Guo Ren - Seperate different trap functions - Add trap_no() - Remove panic code print - Redesign die_if_kerenl to die with riscv's - Print exact trap info for app segment fault [ 17.389321] gzip[126]: unhandled signal 11 code 0x3 at 0x0007835a in busybox[8000+d4000] [ 17.393882]

[PATCH 09/13] csky: Set CONFIG_NR_CPU 4 as default

From: Guo Ren The C860 processors support 4 cores smp for maximum, so set NR_CPU to 4 as default Signed-off-by: Guo Ren Cc: Arnd Bergmann --- arch/csky/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig index fd92d73..ad98b93 1006

[PATCH 11/13] csky: Add irq_work support

From: Guo Ren Running work in hardware interrupt context for csky. Implement: - arch_irq_work_raise() - arch_irq_work_has_interrupt() Signed-off-by: Guo Ren Cc: Arnd Bergmann --- arch/csky/include/asm/irq_work.h | 11 +++ arch/csky/kernel/smp.c | 12 2 files c

[PATCH 10/13] csky: Fixup warning by EXPORT_SYMBOL(kmap)

From: Guo Ren This a wrong code, and no kmap symbol for export. Signed-off-by: Guo Ren Cc: Arnd Bergmann --- arch/csky/mm/highmem.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/csky/mm/highmem.c b/arch/csky/mm/highmem.c index 89ec32e..89c1080 100644 --- a/arch/csky/mm/highmem.c +

[PATCH 03/13] csky: Add cpu feature register hint for smp

From: Guo Ren CPU features registers are setup by customers' bootloader, but Linux must help transfer them from the primary to secondary cores. This patch add hint2 CPU feature register supported. Signed-off-by: Guo Ren Cc: Arnd Bergmann --- arch/csky/kernel/smp.c | 3 +++ 1 file changed, 3 i

[GIT PULL] csky updates for v5.9-rc1

Hi Linus, Please pull csky updates for v5.9-rc1: The following changes since commit 92ed301919932f13b9172e525674157e983d: Linux 5.8-rc7 (2020-07-26 14:14:06 -0700) are available in the git repository at: https://github.com/c-sky/csky-linux.git tags/csky-for-linus-5.9-rc1 for you to fe

[PATCH] ftrace: Fixup lockdep assert held of text_mutex

From: Guo Ren The function ftrace_process_locs() will modify text code, so we should give a text_mutex lock. Because some arch's patch code will assert held of text_mutex even during start_kernel-> ftrace_init(). backtrace log: assert by lockdep_assert_held(&text_mutex) 0 patch_insn_write (a

[PATCH] mmc: Kconfig: Add RISCV and CSKY for MMC_DW

From: Guo Ren Synopsys DesignWare MMC controller could be used in RISC-V and C-SKY architectures. Signed-off-by: Guo Ren Cc: Ulf Hansson --- drivers/mmc/host/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 3

[PATCH] clocksource/drivers/timer-gx6605s: Fixup counter reload

From: Guo Ren When the timer counts to the upper limit, an overflow interrupt is generated, and the count is reset with the value in the TIME_INI register. But the software expects to start counting from 0 when the count overflows, so it forces TIME_INI to 0 to solve the potential interrupt storm

[PATCH] riscv: Remove duplicate definition in pagtable.h

From: Guo Ren PAGE_KERNEL_EXEC has been defined above. Signed-off-by: Guo Ren Cc: Palmer Dabbelt Cc: Pekka Enberg --- arch/riscv/include/asm/pgtable.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 41a72861987c..df

[PATCH] riscv: mm: abort uaccess retries upon fatal signal

From: Guo Ren Pick up the patch from the 'Link' made by Mark Rutland. Keep the same with x86, arm, arm64, arc, sh, power. Link: https://lore.kernel.org/linux-arm-kernel/1499782763-31418-1-git-send-email-mark.rutl...@arm.com/ Signed-off-by: Guo Ren Cc: Mark Rutland Cc: Pekka Enberg Cc: Palmer

[PATCH] mm: page-flags.h: Typo fix (It -> If)

From: Guo Ren The "If" was wrongly spelled as "It". Signed-off-by: Guo Ren Cc: Andrew Morton Cc: Oscar Salvador Cc: Alexander Duyck Cc: David Hildenbrand Cc: Steven Price --- include/linux/page-flags.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/

[PATCH] riscv: locks: introduce ticket-based spinlock implementation

From: Guo Ren This patch introduces a ticket lock implementation for riscv, along the same lines as the implementation for arch/arm & arch/csky. Signed-off-by: Guo Ren Cc: Catalin Marinas Cc: Will Deacon Cc: Peter Zijlstra Cc: Palmer Dabbelt Cc: Anup Patel Cc: Arnd Bergmann --- arch/risc

[PATCH v3 0/4] riscv: Add qspinlock/qrwlock

From: Guo Ren Current riscv is still using baby spinlock implementation. It'll cause fairness and cache line bouncing problems. Many people are involved and pay the efforts to improve it: - The first version of patch was made in 2019.1: https://lore.kernel.org/linux-riscv/20190211043829.300

[PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

From: Michael Clark Update the RISC-V port to use the generic qspinlock and qrwlock. This patch requires support for xchg for short which are added by a previous patch. Guo fixed up compile error which made by below include sequence: +#include +#include Signed-off-by: Michael Clark Co-devel

[PATCH v3 2/4] riscv: cmpxchg.h: Merge macros

From: Guo Ren To reduce assembly codes, let's merge duplicate codes into one (xchg_acquire, xchg_release, cmpxchg_release). Signed-off-by: Guo Ren Link: https://lore.kernel.org/linux-riscv/CAJF2gTT1_mP-wiK2HsCpTeU61NqZVKZX1A5ye=twqvgn4tp...@mail.gmail.com/ Cc: Peter Zijlstra Cc: Michael Clark

[PATCH v3 3/4] riscv: cmpxchg.h: Implement xchg for short

From: Guo Ren riscv only support lr.wd/s(c).w(d) with word(double word) size & align access. There are not lr.h/sc.h instructions. But qspinlock.c need xchg with short type variable: xchg_tail -> xchg_releaxed(&lock->tail, ... typedef struct qspinlock { union { atomic_t

[PATCH v3 1/4] riscv: cmpxchg.h: Cleanup unused code

From: Guo Ren Remove unnecessary marco, they are no use or handled by generic files (atomic-fallback.h, asm-generic/cmpxchg*). Signed-off-by: Guo Ren Link: https://lore.kernel.org/linux-riscv/CAJF2gTT1_mP-wiK2HsCpTeU61NqZVKZX1A5ye=twqvgn4tp...@mail.gmail.com/ Cc: Peter Zijlstra Cc: Michael Cl

[PATCH v6 0/9] riscv: Add qspinlock/qrwlock

From: Guo Ren Current riscv is still using baby spinlock implementation. It'll cause fairness and cache line bouncing problems. Many people are involved and pay the efforts to improve it: - The first version of patch was made in 2019.1: https://lore.kernel.org/linux-riscv/20190211043829.300

[PATCH v6 2/9] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

From: Michael Clark Update the RISC-V port to use the generic qspinlock and qrwlock. This patch requires support for xchg_xtail for full-word which are added by a previous patch: Guo added select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in Kconfig Guo fixed up compile error which made by below include

[PATCH v6 1/9] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren Some architectures don't have sub-word swap atomic instruction, they only have the full word's one. The sub-word swap only improve the performance when: NR_CPUS < 16K * 0- 7: locked byte * 8: pending * 9-15: not used * 16-17: tail index * 18-31: tail cpu (+1) The 9-15 b

[PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation

From: Guo Ren This patch introduces a ticket lock implementation for riscv, along the same lines as the implementation for arch/arm & arch/csky. We still use qspinlock as default. Signed-off-by: Guo Ren Cc: Peter Zijlstra Cc: Anup Patel Cc: Arnd Bergmann --- arch/riscv/Kconfig

[PATCH v6 4/9] csky: locks: Optimize coding convention

From: Guo Ren - Using smp_cond_load_acquire in arch_spin_lock by Peter's advice. - Using __smp_acquire_fence in arch_spin_trylock - Using smp_store_release in arch_spin_unlock All above are just coding conventions and won't affect the function. TODO in smp_cond_load_acquire for architectu

[PATCH v6 5/9] csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

From: Guo Ren Update the C-SKY port to use the generic qspinlock and qrwlock. C-SKY only support ldex.w/stex.w with word(double word) size & align access. So it must select XCHG32 to let qspinlock only use word atomic xchg_tail. Default is still ticket lock. Signed-off-by: Guo Ren Cc: Waiman

[PATCH v6 8/9] xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it. Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations. This patch cancels the dependency of on qspinlock generic code on architecture's xc

[PATCH v6 7/9] sparc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it. Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations. This patch cancels the dependency of on qspinlock generic code on architecture's xc

[PATCH v6 6/9] openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it. Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations. This patch cancels the dependency of on qspinlock generic code on architecture's xc

[PATCH v6 9/9] powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it. Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations. This patch cancels the dependency of on qspinlock generic code on architecture's xc

[PATCH v4 1/4] riscv: cmpxchg.h: Cleanup unused code

From: Guo Ren Remove unnecessary marco, they are no use or handled by generic files (atomic-fallback.h, asm-generic/cmpxchg*). Signed-off-by: Guo Ren Link: https://lore.kernel.org/linux-riscv/CAJF2gTT1_mP-wiK2HsCpTeU61NqZVKZX1A5ye=twqvgn4tp...@mail.gmail.com/ Cc: Peter Zijlstra Cc: Michael Cl

[PATCH v4 0/4] riscv: Add qspinlock/qrwlock

From: Guo Ren Current riscv is still using baby spinlock implementation. It'll cause fairness and cache line bouncing problems. Many people are involved and pay the efforts to improve it: - The first version of patch was made in 2019.1: https://lore.kernel.org/linux-riscv/20190211043829.300

[PATCH v4 2/4] riscv: cmpxchg.h: Merge macros

From: Guo Ren To reduce assembly codes, let's merge duplicate codes into one (xchg_acquire, xchg_release, cmpxchg_release). Signed-off-by: Guo Ren Link: https://lore.kernel.org/linux-riscv/CAJF2gTT1_mP-wiK2HsCpTeU61NqZVKZX1A5ye=twqvgn4tp...@mail.gmail.com/ Cc: Peter Zijlstra Cc: Michael Clark

[PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren Some architectures don't have sub-word swap atomic instruction, they only have the full word's one. The sub-word swap only improve the performance when: NR_CPUS < 16K * 0- 7: locked byte * 8: pending * 9-15: not used * 16-17: tail index * 18-31: tail cpu (+1) The 9-15 b

[PATCH v4 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

From: Michael Clark Update the RISC-V port to use the generic qspinlock and qrwlock. This patch requires support for xchg for short which are added by a previous patch. Guo fixed up compile error which made by below include sequence: +#include +#include Signed-off-by: Michael Clark Co-devel

[PATCH v5 0/7] riscv: Add qspinlock/qrwlock

From: Guo Ren Current riscv is still using baby spinlock implementation. It'll cause fairness and cache line bouncing problems. Many people are involved and pay the efforts to improve it: - The first version of patch was made in 2019.1: https://lore.kernel.org/linux-riscv/20190211043829.300

[PATCH v5 2/7] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

From: Michael Clark Update the RISC-V port to use the generic qspinlock and qrwlock. This patch requires support for xchg_xtail for full-word which are added by a previous patch: Guo added select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in Kconfig Guo fixed up compile error which made by below include

[PATCH v5 1/7] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren Some architectures don't have sub-word swap atomic instruction, they only have the full word's one. The sub-word swap only improve the performance when: NR_CPUS < 16K * 0- 7: locked byte * 8: pending * 9-15: not used * 16-17: tail index * 18-31: tail cpu (+1) The 9-15 b

[PATCH v5 3/7] csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

From: Guo Ren Update the C-SKY port to use the generic qspinlock and qrwlock. C-SKY only support ldex.w/stex.w with word(double word) size & align access. So it must select XCHG32 to let qspinlock only use word atomic xchg_tail. Signed-off-by: Guo Ren Cc: Waiman Long Cc: Peter Zijlstra Cc: W

[PATCH v5 4/7] powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it. Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations. This patch cancels the dependency of on qspinlock generic code on architecture's xc

[PATCH v5 6/7] sparc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it. Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations. This patch cancels the dependency of on qspinlock generic code on architecture's xc

[PATCH v5 5/7] openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it. Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations. This patch cancels the dependency of on qspinlock generic code on architecture's xc

[PATCH v5 7/7] xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32

From: Guo Ren We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it. Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations. This patch cancels the dependency of on qspinlock generic code on architecture's xc

[PATCH v2 1/2] locking/atomics: Fixup GENERIC_ATOMIC64 conflict with atomic-arch-fallback.h

From: Guo Ren Current GENERIC_ATOMIC64 in atomic-arch-fallback.h is broken. When a 32-bit arch use atomic-arch-fallback.h will cause compile error. In file included from include/linux/atomic.h:81, from include/linux/rcupdate.h:25, from include/linux/rculis

[PATCH v2 2/2] riscv: atomic: Using ARCH_ATOMIC in asm/atomic.h

From: Guo Ren The linux/atomic-arch-fallback.h has been there for a while, but only x86 & arm64 support it. Let's make riscv follow the linux/arch/* development trendy and make the codes more readable and maintainable. This patch also cleanup some codes: - Add atomic_andnot_* operation - Using

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