Summary' these power domains
are positioned directly under VD_LOGIC, so fix that in 'rk3399.dtsi'.
Signed-off-by: Johan Jonker
Reviewed-by: Caesar Wang
Thanks,
-Caesar
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++--
1 file changed, 10 insertions(+), 10 deletions
isplay Port PHY")
Signed-off-by: Douglas Anderson
Reviewed-by: Caesar Wang
---
As far as I know Yakir (the original author) is no longer at Rockchip.
I've added a few other Rockchip people and hopefully one of them can
help direct even if they're not directly responsible.
drivers/phy/rockch
On 2018/12/17 下午11:02, Thierry Reding wrote:
From: Thierry Reding
Get rid of some boilerplate driver removal code by using the newly added
device-managed registration API.
Reviewed-by: Caesar Wang
Thanks,
Caesar
Cc: Caesar Wang
Signed-off-by: Thierry Reding
---
drivers/mailbox
Kishon,
Can you help merge this in your or next tree? I'm hoping that we can
land this somewhere.:-)
Thanks,
-Caesar
在 2018年01月11日 10:40, Caesar Wang 写道:
Hi Kishon,
Since the Shawn isn't available, I take over this series patches for now.
As the original bug had tracked on https
Kishon,
Can you help merge this in your or next tree? I'm hoping that we can
land this somewhere.:-)
Thanks,
-Caesar
在 2018年01月11日 10:40, Caesar Wang 写道:
Hi Kishon,
Since the Shawn isn't available, I take over this series patches for now.
As the original bug had tracked on https
Hi Kishon,
Since the Shawn isn't available, I take over this series patches for now.
As the original bug had tracked on https://issuetracker.google.com/71561742.
In some cases, the mmc phy power on failed during booting up.
The log as below:
...
[ 2.375333] rockchip_emmc_phy_power: caldone
Hi Kishon,
Since the Shawn isn't available, I take over this series patches for now.
As the original bug had tracked on https://issuetracker.google.com/71561742.
In some cases, the mmc phy power on failed during booting up.
The log as below:
...
[ 2.375333] rockchip_emmc_phy_power: caldone
From: Shawn Lin <shawn@rock-chips.com>
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin <shawn@rock-chips.com>
Tested-by: Ziyuan Xu <xzy...@rock-chips.com>
Signed-off-by: Caesar Wang &l
From: Shawn Lin <shawn@rock-chips.com>
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin <shawn@rock-chips.com>
Reviewed-by: Brian Norris <briannor...@chromium.org>
Signed-off-by: Caesar Wang <w...@rock-chips.com
From: Shawn Lin
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Signed-off-by: Caesar Wang
---
Changes in v3:
- As Doug commented on https://patchwork.kernel.org/patch/10154797,
Change "1, 50"
From: Shawn Lin
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin
Tested-by: Ziyuan Xu
Signed-off-by: Caesar Wang
---
Changes in v3:
- As Doug commented on both upstream and gerrit.
Change "5, 50"
在 2018年01月11日 03:36, Doug Anderson 写道:
Hi,
On Wed, Jan 10, 2018 at 9:46 AM, Brian Norris wrote:
*/
- timeout = jiffies + msecs_to_jiffies(50);
- do {
- udelay(1);
-
- regmap_read(rk_phy->reg_base,
-
在 2018年01月11日 03:36, Doug Anderson 写道:
Hi,
On Wed, Jan 10, 2018 at 9:46 AM, Brian Norris wrote:
*/
- timeout = jiffies + msecs_to_jiffies(50);
- do {
- udelay(1);
-
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset +
the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin <shawn@rock-chips.com>
Reviewed-by: Brian Norris <briannor...@chromium.org>
Tested-by: Caesar Wang <w...@rock-chips.com>
Tested-by: Ziyuan Xu <xzy...@rock-chips.com>
---
Changes in v
the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Tested-by: Caesar Wang
Tested-by: Ziyuan Xu
---
Changes in v2:
- propagate the error and print it
- avoid using busy wait
drivers/phy/rockchip/phy-rockchip-emmc.c | 32
From: Shawn Lin <shawn@rock-chips.com>
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin <shawn@rock-chips.com>
Reviewed-by: Brian Norris <briannor...@chromium.org>
Signed-off-by: Caesar Wang <w...@rock-chips.com
From: Shawn Lin
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Signed-off-by: Caesar Wang
---
Changes in v2:
- As Brian commented on https://patchwork.kernel.org/patch/10139891/,
changed the note and added
Hi Kishon,
Since the Shawn isn't available, I take over this series patches for now.
As the original bug had tracked on https://issuetracker.google.com/71561742.
In some cases, the mmc phy power on failed during booting up.
The log as below:
...
[ 2.375333] rockchip_emmc_phy_power: caldone
Hi Kishon,
Since the Shawn isn't available, I take over this series patches for now.
As the original bug had tracked on https://issuetracker.google.com/71561742.
In some cases, the mmc phy power on failed during booting up.
The log as below:
...
[ 2.375333] rockchip_emmc_phy_power: caldone
From: Shawn Lin <shawn@rock-chips.com>
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin <shawn@rock-chips.com>
Tested-by: Ziyuan Xu <xzy...@rock-chips.com>
Signed-off-by: Caesar Wang &l
From: Shawn Lin
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin
Tested-by: Ziyuan Xu
Signed-off-by: Caesar Wang
---
Changes in v2:
- print the return valut with regmap_read_poll_timeout failing.
drivers/phy
ned-off-by: Shawn Lin <shawn@rock-chips.com>
Tested-by: Caesar Wang <w...@rock-chips.com>
I had tested on rk3399 chromebook, so feel free to add my tag.
-Caesar
---
drivers/phy/rockchip/phy-rockchip-emmc.c | 21 +
1 file changed, 13 insertions(+), 8 delet
ned-off-by: Shawn Lin
Tested-by: Caesar Wang
I had tested on rk3399 chromebook, so feel free to add my tag.
-Caesar
---
drivers/phy/rockchip/phy-rockchip-emmc.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c
b/
在 2017年09月15日 10:10, Caesar Wang 写道:
Hi Rocky,
在 2017年08月24日 18:27, Rocky Hao 写道:
RV1108 SOC has one Temperature Sensor for CPU.
Signed-off-by: Rocky Hao <rocky@rock-chips.com>
Reviewed-by: Caesar Wang <w...@rock-chips.com>
---
drivers/thermal/rockchip_th
在 2017年09月15日 10:10, Caesar Wang 写道:
Hi Rocky,
在 2017年08月24日 18:27, Rocky Hao 写道:
RV1108 SOC has one Temperature Sensor for CPU.
Signed-off-by: Rocky Hao
Reviewed-by: Caesar Wang
---
drivers/thermal/rockchip_thermal.c | 67
++
1 file changed, 67
Hi Rocky,
在 2017年08月24日 18:27, Rocky Hao 写道:
RV1108 SOC has one Temperature Sensor for CPU.
Signed-off-by: Rocky Hao
---
drivers/thermal/rockchip_thermal.c | 67 ++
1 file changed, 67 insertions(+)
diff --git
Hi Rocky,
在 2017年08月24日 18:27, Rocky Hao 写道:
RV1108 SOC has one Temperature Sensor for CPU.
Signed-off-by: Rocky Hao
---
drivers/thermal/rockchip_thermal.c | 67 ++
1 file changed, 67 insertions(+)
diff --git a/drivers/thermal/rockchip_thermal.c
Rocky,
在 2017年08月24日 18:27, Rocky Hao 写道:
Add tsadc needed main information for RV1108 SoC.
75Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao
---
arch/arm/boot/dts/rv1108.dtsi | 29 +
1 file changed, 29
Rocky,
在 2017年08月24日 18:27, Rocky Hao 写道:
Add tsadc needed main information for RV1108 SoC.
75Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao
---
arch/arm/boot/dts/rv1108.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git
Hi Rocky,
在 2017年08月24日 18:27, Rocky Hao 写道:
Add a new compatible for thermal founding on RV1108 SoCs.
Signed-off-by: Rocky Hao
---
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi Rocky,
在 2017年08月24日 18:27, Rocky Hao 写道:
Add a new compatible for thermal founding on RV1108 SoCs.
Signed-off-by: Rocky Hao
---
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
在 2017年08月04日 16:06, Rocky Hao 写道:
add thermal zone and dynamic CPU power coefficients for rk3328
Signed-off-by: Rocky Hao
---
Change in v2:
- remove gerrit Change-Id
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 43
1 file changed,
在 2017年08月04日 16:06, Rocky Hao 写道:
add thermal zone and dynamic CPU power coefficients for rk3328
Signed-off-by: Rocky Hao
---
Change in v2:
- remove gerrit Change-Id
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 43
1 file changed, 43 insertions(+)
diff
在 2017年08月04日 16:06, Rocky Hao 写道:
add tsadc needed main information for rk3328 SoC.
5Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao
---
Change in v2:
- remove gerrit Change-Id
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 20
在 2017年08月04日 16:06, Rocky Hao 写道:
add tsadc needed main information for rk3328 SoC.
5Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao
---
Change in v2:
- remove gerrit Change-Id
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 20
1 file
在 2017年08月11日 11:02, Zhang Rui 写道:
On Tue, 2017-07-25 at 17:09 +0800, Rocky Hao wrote:
RK3328 SOC has one Temperature Sensor for CPU.
Change-Id: I176c76bae1801d815a513986cfefcb55272c69a8
Signed-off-by: Rocky Hao <rocky@rock-chips.com>
Reviewed-by: Caesar Wang <w...@rock-
在 2017年08月11日 11:02, Zhang Rui 写道:
On Tue, 2017-07-25 at 17:09 +0800, Rocky Hao wrote:
RK3328 SOC has one Temperature Sensor for CPU.
Change-Id: I176c76bae1801d815a513986cfefcb55272c69a8
Signed-off-by: Rocky Hao
Reviewed-by: Caesar Wang
Caesar,
what do you think of this patch?
Have
~443
216 0.8 82 ~438
312 0.8 115 ~430
408 0.8 150 ~455
So the dynamic-power-coefficient average value is about 436.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk339
~443
216 0.8 82 ~438
312 0.8 115 ~430
408 0.8 150 ~455
So the dynamic-power-coefficient average value is about 436.
Signed-off-by: Caesar Wang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
1 file
Hi Heiko,
Thanks your comments.
在 2017年07月23日 05:48, Heiko Stuebner 写道:
Hi Caesar,
Am Montag, 17. Juli 2017, 16:14:31 CEST schrieb Caesar Wang:
As RK3399 had used the Power allocator thermal governor by default,
enabled this to manage thermals by dynamically allocating and limiting
power
Hi Heiko,
Thanks your comments.
在 2017年07月23日 05:48, Heiko Stuebner 写道:
Hi Caesar,
Am Montag, 17. Juli 2017, 16:14:31 CEST schrieb Caesar Wang:
As RK3399 had used the Power allocator thermal governor by default,
enabled this to manage thermals by dynamically allocating and limiting
power
fter.
-Caesar
在 2017年07月17日 16:14, Caesar Wang 写道:
This series patches supported the mail in devicetree and used the
thermal IPA by default.
Verified with kernel is based on Linus's master branch and Heiko's
v4.14-armsoc-tmp/dts64 branch. ( The Linux version 4.12.0 for now).
The most rockchip
fter.
-Caesar
在 2017年07月17日 16:14, Caesar Wang 写道:
This series patches supported the mail in devicetree and used the
thermal IPA by default.
Verified with kernel is based on Linus's master branch and Heiko's
v4.14-armsoc-tmp/dts64 branch. ( The Linux version 4.12.0 for now).
The most rockchip
Rob,
在 2017年07月18日 04:07, Rob Herring 写道:
On Mon, Jul 17, 2017 at 04:14:28PM +0800, Caesar Wang wrote:
This patch adds the MALI's power-model to set the IPA model to be used
for power management.
What's IPA? India Pale Ale or Intermediate Physical Address?
IPA is intelligent Power Allocator
Rob,
在 2017年07月18日 04:07, Rob Herring 写道:
On Mon, Jul 17, 2017 at 04:14:28PM +0800, Caesar Wang wrote:
This patch adds the MALI's power-model to set the IPA model to be used
for power management.
What's IPA? India Pale Ale or Intermediate Physical Address?
IPA is intelligent Power Allocator
RK3399's GPU uses the quad-core Mali-T860, which is the new generation of
high-end graphics processors from ARM.
This patch added "rockchip,rk3399-mali" for dt-bindings, in order to
support IPA of gpu thermal in later.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
Cha
RK3399's GPU uses the quad-core Mali-T860, which is the new generation of
high-end graphics processors from ARM.
This patch added "rockchip,rk3399-mali" for dt-bindings, in order to
support IPA of gpu thermal in later.
Signed-off-by: Caesar Wang
---
Changes in v2: None
Doc
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.
RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. Also, the ARM's mali driver found on
https://developer.arm.com/products/software/mali-drivers/midgard-kernel.
Signed-off-by: Caesar Wang &l
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.
RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. Also, the ARM's mali driver found on
https://developer.arm.com/products/software/mali-drivers/midgard-kernel.
Signed-off-by: Caesar Wang
This patch enables the gpu and adds the mali-supply power for RK3399-GRU
devices.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/
This patch enables the gpu and adds the mali-supply power for RK3399-GRU
devices.
Signed-off-by: Caesar Wang
---
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
b/arch/arm64
.
The Thermal power allocator governor works optimatly with two passive trip
points, for the better performance we will use the trip-point0 with 70
degree above which the governor control starts operating and trip-point1
with 85 degree is the target temperature by controlling.
Signed-off-by: Caesar
.
The Thermal power allocator governor works optimatly with two passive trip
points, for the better performance we will use the trip-point0 with 70
degree above which the governor control starts operating and trip-point1
with 85 degree is the target temperature by controlling.
Signed-off-by: Caesar
This patch adds the MALI's power-model to set the IPA model to be used
for power management.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
Changes in v2: None
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 12
1 file changed, 12 insertions(+)
diff
This patch adds the MALI's power-model to set the IPA model to be used
for power management.
Signed-off-by: Caesar Wang
---
Changes in v2: None
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree
foo@ will produce warnings when used without reg property.
- update the commit to explain the two passive trip points changed.
Caesar Wang (5):
dt-bindings: gpu: add the RK3399 mali for rockchip specifics
dt-bindings: gpu: add a power_model optional properties for MALI
arm64: dts: rockchip: a
foo@ will produce warnings when used without reg property.
- update the commit to explain the two passive trip points changed.
Caesar Wang (5):
dt-bindings: gpu: add the RK3399 mali for rockchip specifics
dt-bindings: gpu: add a power_model optional properties for MALI
arm64: dts: rockchip: a
在 2017年07月12日 15:19, Heiko Stuebner 写道:
Hi Caesar,
Am Mittwoch, 12. Juli 2017, 14:29:28 CEST schrieb Caesar Wang:
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.
RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. As the ARM's mali driver
在 2017年07月12日 15:19, Heiko Stuebner 写道:
Hi Caesar,
Am Mittwoch, 12. Juli 2017, 14:29:28 CEST schrieb Caesar Wang:
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.
RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. As the ARM's mali driver
ts to have a look at the actual control.
"
while true; do grep "" /sys/class/thermal/thermal_zone[0-1]/temp
/sys/devices/system/cpu/cpu[0-5]/cpufreq/scaling_cur_freq
/sys/devices/platform/ff9a.gpu/devfreq/ff9a.gpu/cur_freq;date;sleep .5;
done &
"
-Caesar
Caesar
ts to have a look at the actual control.
"
while true; do grep "" /sys/class/thermal/thermal_zone[0-1]/temp
/sys/devices/system/cpu/cpu[0-5]/cpufreq/scaling_cur_freq
/sys/devices/platform/ff9a.gpu/devfreq/ff9a.gpu/cur_freq;date;sleep .5;
done &
"
-Caesar
Caesar
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.
RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. As the ARM's mali driver found on
https://developer.arm.com/products/software/mali-drivers/midgard-kernel.
Signed-off-by: Caesar Wang &l
.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 62 +++-
1 file changed, 29 insertions(+), 33 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 8
.
Signed-off-by: Caesar Wang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 62 +++-
1 file changed, 29 insertions(+), 33 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 8c6438b..139f58c 100644
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.
RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. As the ARM's mali driver found on
https://developer.arm.com/products/software/mali-drivers/midgard-kernel.
Signed-off-by: Caesar Wang
RK3399's GPU uses the quad-core Mali-T860, which is the new generation of
high-end graphics processors from ARM.
This patch added "rockchip,rk3399-mali" for dt-bindings, in order to
support IPA of gpu thermal in later.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
This patch enables the gpu and adds the mali-supply power for RK3399-GRU
devices.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
b/arch
RK3399's GPU uses the quad-core Mali-T860, which is the new generation of
high-end graphics processors from ARM.
This patch added "rockchip,rk3399-mali" for dt-bindings, in order to
support IPA of gpu thermal in later.
Signed-off-by: Caesar Wang
---
Documentation/devicetree/bindin
This patch enables the gpu and adds the mali-supply power for RK3399-GRU
devices.
Signed-off-by: Caesar Wang
---
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
b/arch/arm64/boot/dts/rockchip
The SdioAudio power domain includes the i2s/spdif/spi5/sdio.
So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order
to save more power consumption.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
Changes note:
- As the Jeffy fixes the spi'cs issue recently as f
The SdioAudio power domain includes the i2s/spdif/spi5/sdio.
So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order
to save more power consumption.
Signed-off-by: Caesar Wang
---
Changes note:
- As the Jeffy fixes the spi'cs issue recently as follows:
aa09938 spi: rockchip
ock-chips.com>
Tested-by: Caesar Wang <w...@rock-chips.com>
I have fetched these patches to test S2R with my board for chromeos4.4.
localhost ~ # cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
...
pd_sdioaudioon
/devices/platform/ff20.spi
[ 5.585784 ] cros-ec-spi spi5.0: Transfer error 1/3: -110
..
Feels like that a workaround way to fix it, but that should be a good
solution.
在 2017年06月14日 11:38, Jeffy Chen 写道:
Support using "cs-gpios" property to specify cs gpios.
Signed-off-by: Jeffy Chen
Tested-by: Caesa
domain rules
if (ch->flags & IEEE80211_CHAN_DISABLED)
continue;
so it should not been an ERROR. WARN looks fine to me.
you can add me acked-by in v2.
Okay, thanks for explanation and having a look at it.
-Caesar
Regards,
Simon
From: Caesar Wang [mailto:w...@r
if (ch->flags & IEEE80211_CHAN_DISABLED)
continue;
so it should not been an ERROR. WARN looks fine to me.
you can add me acked-by in v2.
Okay, thanks for explanation and having a look at it.
-Caesar
Regards,
Simon
From: Caesar Wang [mailto:w...@rock-chips.com]
Sent: 2017年6
ED)
continue;
So it should not been an ERROR, use the WARN level to instead it for now.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
Acked-by: Xinming Hu <h...@marvell.com>
---
Changes in v2:
- Fixes the commit and title as Kalle and Xinming comments on
https://patc
ED)
continue;
So it should not been an ERROR, use the WARN level to instead it for now.
Signed-off-by: Caesar Wang
Acked-by: Xinming Hu
---
Changes in v2:
- Fixes the commit and title as Kalle and Xinming comments on
https://patchwork.kernel.org/patch/9786047/
- Add the Acked by &
在 2017年06月13日 15:04, Kalle Valo 写道:
Caesar Wang <w...@rock-chips.com> writes:
Kalle,
在 2017年06月13日 14:28, Kalle Valo 写道:
Caesar Wang <w...@rock-chips.com> writes:
We have always met the unused log be printed as following.
...
[23193.523182] mwifiex_pcie :01:00.0: mwi
在 2017年06月13日 15:04, Kalle Valo 写道:
Caesar Wang writes:
Kalle,
在 2017年06月13日 14:28, Kalle Valo 写道:
Caesar Wang writes:
We have always met the unused log be printed as following.
...
[23193.523182] mwifiex_pcie :01:00.0: mwifiex_get_cfp:
cannot find cfp by band 2& channel=13
Kalle,
在 2017年06月13日 14:28, Kalle Valo 写道:
Caesar Wang <w...@rock-chips.com> writes:
We have always met the unused log be printed as following.
...
[23193.523182] mwifiex_pcie :01:00.0: mwifiex_get_cfp:
cannot find cfp by band 2& channel=13 freq=0
[23378.633684] mwifiex_pc
Kalle,
在 2017年06月13日 14:28, Kalle Valo 写道:
Caesar Wang writes:
We have always met the unused log be printed as following.
...
[23193.523182] mwifiex_pcie :01:00.0: mwifiex_get_cfp:
cannot find cfp by band 2& channel=13 freq=0
[23378.633684] mwifiex_pcie :01:00.0: mwifiex_get
7 MHz [8] (30.0 dBm)
* 2452 MHz [9] (30.0 dBm)
* 2457 MHz [10] (30.0 dBm)
* 2462 MHz [11] (30.0 dBm)
* 2467 MHz [12] (disabled)
* 2472 MHz [13] (disabled)
* 2484 MHz [14] (disabled)
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
drivers/net/wireless/marvell/mwifiex/cfp.c | 2 +-
1 f
7 MHz [8] (30.0 dBm)
* 2452 MHz [9] (30.0 dBm)
* 2457 MHz [10] (30.0 dBm)
* 2462 MHz [11] (30.0 dBm)
* 2467 MHz [12] (disabled)
* 2472 MHz [13] (disabled)
* 2484 MHz [14] (disabled)
Signed-off-by: Caesar Wang
---
drivers/net/wireless/marvell/mwifiex/cfp.c | 2 +-
1 file changed, 1 insertion(+), 1
As the allocation and free buffer that need to add mutex lock for drm mm,
but it lacks the locking on error path in rockchip_gem_iommu_map().
Also, the trivial changes like The comment should be placed in the
kerneldoc and unused blank line.
Signed-off-by: Caesar Wang <w...@rock-chips.
As the allocation and free buffer that need to add mutex lock for drm mm,
but it lacks the locking on error path in rockchip_gem_iommu_map().
Also, the trivial changes like The comment should be placed in the
kerneldoc and unused blank line.
Signed-off-by: Caesar Wang
---
drivers/gpu/drm
在 2017年04月24日 16:26, Heiko Stübner 写道:
Hi Caesar,
Am Montag, 24. April 2017, 14:18:50 CEST schrieb Caesar Wang:
Update the cpu opp table for rk3399 op1.
Ideally this should contain something about the "why".
Are these new voltage settings safer to operate under?
The before
在 2017年04月24日 16:26, Heiko Stübner 写道:
Hi Caesar,
Am Montag, 24. April 2017, 14:18:50 CEST schrieb Caesar Wang:
Update the cpu opp table for rk3399 op1.
Ideally this should contain something about the "why".
Are these new voltage settings safer to operate under?
The before
Update the cpu opp table for rk3399 op1.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
b/arch/arm64/bo
Update the cpu opp table for rk3399 op1.
Signed-off-by: Caesar Wang
---
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
Shunqian,
something is depending on these patches, can you resend these patches to
solve the
compile errors?
-Caesar
在 2016年07月16日 00:16, Joerg Roedel 写道:
On Fri, Jul 15, 2016 at 05:32:02PM +0200, Matthias Brugger wrote:
The drm rockchip patches are dependent on iommu/rockchip patches, can
Shunqian,
something is depending on these patches, can you resend these patches to
solve the
compile errors?
-Caesar
在 2016年07月16日 00:16, Joerg Roedel 写道:
On Fri, Jul 15, 2016 at 05:32:02PM +0200, Matthias Brugger wrote:
The drm rockchip patches are dependent on iommu/rockchip patches, can
("thermal: rockchip: optimize the conversion table")
Reported-by: ayaka <ay...@soulik.info>
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
drivers/thermal/rockchip_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/rockchip_therma
("thermal: rockchip: optimize the conversion table")
Reported-by: ayaka
Signed-off-by: Caesar Wang
---
drivers/thermal/rockchip_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index cbbf0c
在 2017年01月03日 07:57, Randy Li 写道:
On 01/02/2017 09:16 PM, Caesar Wang wrote:
在 2016年12月31日 00:11, ayaka 写道:
BTW, Caesar have you ever met this at RK3288 at booting time?
[8.430582] thermal thermal_zone1: critical temperature
reached(125 C),shutting down
[8.439038] thermal
在 2017年01月03日 07:57, Randy Li 写道:
On 01/02/2017 09:16 PM, Caesar Wang wrote:
在 2016年12月31日 00:11, ayaka 写道:
BTW, Caesar have you ever met this at RK3288 at booting time?
[8.430582] thermal thermal_zone1: critical temperature
reached(125 C),shutting down
[8.439038] thermal
for
your linux kernel?
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/380446.html
-Caesar
On 12/12/2016 07:05 PM, Caesar Wang wrote:
There are five patches posted for upstream.
89267b5 thermal: rockchip: improve conversion error messages
a0b5649 thermal: rockchip: don't
for
your linux kernel?
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/380446.html
-Caesar
On 12/12/2016 07:05 PM, Caesar Wang wrote:
There are five patches posted for upstream.
89267b5 thermal: rockchip: improve conversion error messages
a0b5649 thermal: rockchip: don't
在 2016年12月17日 08:59, Brian Norris 写道:
In the pattern of many other devices, support a system-sleep pin
configuration.
Signed-off-by: Brian Norris <briannor...@chromium.org>
Tested-by: Caesar Wang <w...@rock-chips.com>
---
Documentation/devicetree/bindings/spi/spi-rock
在 2016年12月17日 08:59, Brian Norris 写道:
In the pattern of many other devices, support a system-sleep pin
configuration.
Signed-off-by: Brian Norris
Tested-by: Caesar Wang
---
Documentation/devicetree/bindings/spi/spi-rockchip.txt | 7 +++
drivers/spi/spi-rockchip.c
Detailed mode2: Clock 57.500 MHz, 216 mm x 135 mm
1280 1328 1360 1440 hborder 0
800 803 808 832 vborder 0
+hsync -vsync
Add the both edid to support more modes for BOE nv101wxmn51.
Signed-off-by: Caesar Wang <w...@rock-chips.com>
---
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