this change device can be assigned to VMs with VFIO,
> but it will leak state between VMs.
>
> Reference: https://e2e.ti.com/support/processors/f/791/t/954382
> Signed-off-by: Antti Järvinen
Reviewed-by: Kishon Vijay Abraham I
> ---
> drivers/pci/quirks.c | 10 ++
&g
Add Documentation to help users use PCI endpoint to create virtual
functions using configfs. An endpoint function is designated as a
virtual endpoint function device when it is linked to a physical
endpoint function device (instead of a endpoint controller).
Signed-off-by: Kishon Vijay Abraham I
Populate sriov_configure ops with pci_sriov_configure_simple to
configure SR-IOV device.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index
Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 44 +++---
.../pci/controller/dwc/pcie
Now that support for SR-IOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 241 +++---
drivers/pci/controller/cadence/pcie-cadence.h
While the physical function has to be linked to endpoint controller, the
virtual function has to be linked to a physical function. Add support to
link a physical function to a virtual function in pci-ep-cfs.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 24
[2] -> http://lore.kernel.org/r/20201112175358.2653-1-kis...@ti.com
[3] -> https://lore.kernel.org/r/20210305050410.9201-1-kis...@ti.com
[4] -> http://lore.kernel.org/r/20210310160943.7606-1-kis...@ti.com
Kishon Vijay Abraham I (7):
dt-bindings: PCI: pci-ep: Add binding to specify virt
Add support to add virtual function in endpoint core. The virtual
function can only be associated with a physical function instead of a
endpoint controller. Provide APIs to associate a virtual function with
a physical function here.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint
Add binding to specify virtual function (associated with each physical
function) in endpoint mode.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/pci-ep.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation
Hi Aswath,
On 15/04/21 8:19 pm, Aswath Govindraju wrote:
> Add API for devm_of_phy_optional_get_by_index, to obtain a reference to an
> optional phy by index.
Rob has posted a patch
http://lore.kernel.org/r/20210414135525.3535787-1-r...@kernel.org
that doesn't require consumers to get a phy by
Hi,
On 01/04/21 1:08 pm, Kishon Vijay Abraham I wrote:
> Hi Usama,
>
> On 01/04/21 1:03 pm, Muhammad Usama Anjum wrote:
>> Hi,
>>
>> `mode` remains uninitialized when `lane_phy_type` isn't PHY_TYPE_DP
>> or
>> PHY_TYPE_QSGMII. I've checked the d
Hi Usama,
On 01/04/21 1:03 pm, Muhammad Usama Anjum wrote:
> Hi,
>
> `mode` remains uninitialized when `lane_phy_type` isn't PHY_TYPE_DP
> or
> PHY_TYPE_QSGMII. I've checked the dtsi (k3-j721e-common-proc-
> board.dts)
> and possible values of `lane_phy_type` are justPHY_TYPE_USB3 and
>
set of parameters
> should cover all potential users.
>
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: NXP Linux Team
> Signed-off-by: Liu Ying
> ---
> v4->v5:
> * Align kernel-doc style to include/linux/phy/phy.h. (Vinod)
> * Trivial tweaks.
> * Drop R
Configure 'p_standard_mode' only for DP/QSGMII as for other modes
it's not used as per the programming sequence. Add "continue" in the
else to prevent random value from being written to p_standard_mode.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 2
Do not configure torrent SERDES if it's already configured.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 32 ---
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/cadence/phy
No functional change intended. Group reset APIs and clock APIs in
preparation for adding support to skip configuration if the SERDES
is already configured by bootloader.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 84
The Torrent spec specifies delay of 660.5us after phy_reset is
asserted by the controller. To be on the safe side provide a delay
of 5ms to 10ms in ->phy_on() callback where the SERDES is already
configured in bootloader.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cade
No functional change. Since the reset controls obtained in
Torrent is exclusively used by the Torrent device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 2 +-
1 file changed
if any of the lanes has
already been enabled.
Signed-off-by: Faiz Abbas
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
if its already configured
Kishon Vijay Abraham I (4):
phy: cadence-torrent: Group reset APIs and clock APIs
phy: cadence-torrent: Do not configure SERDES if it's already
configured
phy: cadence-torrent: Explicitly request exclusive reset control
phy: cadence-torrent: Add delay for PIPE
Hi Swapnil,
On 18/03/21 3:25 pm, Swapnil Kashinath Jakhade wrote:
>
>
>> -Original Message-----
>> From: Kishon Vijay Abraham I
>> Sent: Wednesday, March 10, 2021 9:25 PM
>> To: Kishon Vijay Abraham I ; Vinod Koul
>> ; Rob Herring ; Philipp Zabel
>
Hi Rob,
On 26/03/21 5:08 am, Rob Herring wrote:
> On Thu, Mar 25, 2021 at 02:30:21PM +0530, Kishon Vijay Abraham I wrote:
>> Add PCIe host mode dt-bindings for TI's AM65 SoC.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> .../bindings/pci/t
B – APRIL 2020 – REVISED JANUARY 2021)
>
> Signed-off-by: Aswath Govindraju
> Reviewed-by: Kishon Vijay Abraham I
Thanks! Patch looks good to me.
Regards
Kishon
> ---
> .../dts/ti/k3-j7200-common-proc-board.dts | 78 +++
> arch/arm64/boot/dts/ti/k3-j7200-m
7B – APRIL 2020 – REVISED JANUARY 2021)
minor comments below.. once you fix them, please add
Reviewed-by: Kishon Vijay Abraham I
>
> Signed-off-by: Aswath Govindraju
> ---
> .../dts/ti/k3-j7200-common-proc-board.dts | 78 +++
> arch/arm64/boot/dts/ti/k3-
AM64 has the same PCIe IP as in J7200 (legacy interrupt handling is
same as J7200 instead of J721E). Add support for "ti,am64-pcie-host"
compatible that is specific to AM64.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 4
1 file
-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 111 ++---
1 file changed, 99 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/controller/cadence/pci-j721e.c
index 17db86a51ca8..f175f116abf6 100644
functionality to edge interrupt line, PCIe
in J721E has provided IRQ_EOI register. When the SW writes to IRQ_EOI
register after handling the interrupt, the IP checks the state of
legacy interrupt and re-triggers pulse interrupt invoking the handler
again.
Signed-off-by: Kishon Vijay Abraham I
by configuring EOI
register.
Kishon Vijay Abraham I (4):
dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts
PCI: j721e: Add PCI legacy interrupt support for J721E
PCI: j721e: Add PCIe support for j7200
PCI: j721e: Add PCIe support for AM64
.../bindings/pci/ti,j721e-pci
Add bindings to specify interrupt controller for legacy interrupts.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
b
K2G provides separate IRQ lines for each of the four legacy interrupts.
Model this using hierarchy domain instead of linear domain with chained
IRQ handler.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 214 --
1 file changed, 120
ttp://www.ti.com/lit/er/sprz452d/sprz452d.pdf
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 42 +++
1 file changed, 42 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c
b/drivers/pci/controller/dwc/pci-keystone.c
in
functionality to edge interrupt line, PCIe
in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
register after handling the interrupt, the IP checks the state of
legacy interrupt and re-triggers pulse interrupt invoking the handler
again.
Signed-off-by: Kishon Vijay Abraham I
Add PCIe endpoint mode dt-bindings for TI's AM65 SoC.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/pci/ti,am65-pci-ep.yaml | 80 +++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
diff --git
ild-wind.fr.eu.org/
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/irqdomain.h | 2 ++
kernel/irq/irqdomain.c| 6 +++---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
index 42d196805f58..0236f508259e 100644
--- a/incl
hon Vijay Abraham I (6):
dt-bindings: PCI: ti,am65: Add PCIe host mode dt-bindings for TI's
AM65 SoC
dt-bindings: PCI: ti,am65: Add PCIe endpoint mode dt-bindings for TI's
AM65 SoC
irqdomain: Export of_phandle_args_to_fwspec()
PCI: keystone: Convert to using hierarchy domain for leg
Add PCIe host mode dt-bindings for TI's AM65 SoC.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/pci/ti,am65-pci-host.yaml| 111 ++
1 file changed, 111 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
diff --git
driver
commit 15b23906347c ("PCI: dwc: Add link up check in
dw_child_pcie_ops.map_bus()").
Fixes: 10a797c6e54a ("PCI: dwc: keystone: Use pci_ops for config space
accessors")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.10
---
drivers/pci/controller/dwc/pci-keystone.c | 11
Patch series includes a couple of fixes in pci-keystone driver
for issues seen when testing Root Complex mode in K2G driver.
Kishon Vijay Abraham I (2):
PCI: keystone: Set mode as RootComplex for "ti,keystone-pcie"
compatible
PCI: keystone: Add link up check in ks_child_pcie_o
ode as RootComplex for
"ti,keystone-pcie" compatible here.
Fixes: 23284ad677a9 ("PCI: keystone: Add support for PCIe EP in AM654x
Platforms")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.4+
---
drivers/pci/controller/dwc/pci-keystone.c | 1 +
1 file changed, 1 insertion(+
Hi,
On 23/03/21 8:42 pm, Bjorn Helgaas wrote:
> [-cc Dilip (mail to him bounced)]
>
> On Tue, Mar 23, 2021 at 11:01:15AM +0800, Jisheng Zhang wrote:
>> On Mon, 22 Mar 2021 20:24:41 -0500 Bjorn Helgaas wrote:
>>>
>>> [+cc Kishon, Richard, Lucas, Dilip]
>>>
>>> On Mon, Mar 01, 2021 at 11:10:31AM
Hi Aswath,
On 23/03/21 10:54 am, Aswath Govindraju wrote:
> Hi Nishanth,
>
> On 22/03/21 9:05 pm, Nishanth Menon wrote:
>> On 18:42-20210322, Aswath Govindraju wrote:
>>> The following speed modes are now supported in J7200 SoC,
>>> - HS200 and HS400 modes at 1.8 V card voltage, in MMCSD0
Hi Aswath,
On 19/03/21 1:30 pm, Aswath Govindraju wrote:
> From: Kishon Vijay Abraham I
>
> Add SERDES DT node for the single one lane SERDES present in
> AM64.
>
> Signed-off-by: Kishon Vijay Abraham I
> Signed-off-by: Aswath Govindraju
> ---
> arch/arm64/boot/dt
commit 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") enabled
the clock in probe and failed to disable in remove callback. Add missing
clk_disable_unprepare() in cdns_sierra_phy_remove().
Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by:
Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/phy/phy-cadence-sierra.yaml| 17 -
include/dt-bindings/phy/phy-cadence.h
Vijay Abraham I
Reviewed-by: Swapnil Jakhade
---
drivers/phy/cadence/Kconfig | 1 +
drivers/phy/cadence/phy-cadence-sierra.c | 267 ++-
2 files changed, 265 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2
No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Swapnil Jakhade
---
.../devicetree
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers
node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" subnod
d device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-ca
wiz_init() immediately before invoking
of_platform_device_create().
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Swapnil Jakhade
Cc: # v5.10
---
drivers/phy/ti/phy-j721e-
310154558.32078-1-kis...@ti.com
Kishon Vijay Abraham I (13):
phy: cadence: Sierra: Fix PHY power_on sequence
phy: ti: j721e-wiz: Invoke wiz_init() before
of_platform_device_create()
phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
phy: ti: j7
re.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.4+
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-sierra.c | 40
(SPRSP57B – APRIL 2020 – REVISED JANUARY 2021)
Thanks for fixing the link.
Reviewed-by: Kishon Vijay Abraham I
>
> Signed-off-by: Aswath Govindraju
> ---
> .../dts/ti/k3-j7200-common-proc-board.dts | 42 +++
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 14 ++-
Hi,
On 10/03/21 9:49 pm, Aswath Govindraju wrote:
> The following speed modes are now supported in J7200 SoC,
> - HS200 and HS400 modes at 1.8 V card voltage, in MMCSD0 subsystem [1].
> - UHS-I speed modes in MMCSD1 subsystem [1].
>
> Add support for UHS-I modes by adding voltage regulator
Aswath and Nishanth,
On 17/03/21 10:00 am, Aswath Govindraju wrote:
> The following series of patches, add USB support for AM642 evm.
>
> USB test logs,
> https://pastebin.ubuntu.com/p/YSQRBWGmzd/
Vinod has provided stable tag [1]
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git
Hi,
On 17/03/21 8:22 pm, Kishon Vijay Abraham I wrote:
> Aswath and Nishanth,
>
> On 17/03/21 10:00 am, Aswath Govindraju wrote:
>> The following series of patches, add USB support for AM642 evm.
>>
>> USB test logs,
>> https://pastebin.ubuntu.com/p/YSQRBWGmzd/
&
65x and K2. This breaks configuration space
access for AM65x platform. Fix it here.
Fixes: 10a797c6e54a ("PCI: dwc: keystone: Use pci_ops for config space
accessors")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.10
---
drivers/pci/controller/dwc/pci-keystone.c | 3 ++-
1 file changed
borg
> Cc: Vinod Koul
> Cc: Alexandre Belloni
> Cc: Jonathan Cameron
> Cc: Pavel Machek
> Cc: Kishon Vijay Abraham I
> Cc: Sebastian Reichel
> Cc: Mark Brown
> Cc: Greg Kroah-Hartman
> Cc: linux-...@vger.kernel.org
> Cc: dmaeng...@vger.kernel.org
> Cc: lin
Hi Vinod,
On 10/03/21 4:57 pm, Kishon Vijay Abraham I wrote:
> Patch series adds device tree bindings to support SERDES in AM64
> platform.
>
> This is split from [1] since this binding is also required for AM64
> USB DT patches to be merged.
>
> Vinod,
>
> Once
iewed-by: Andrew Lunn
> Reviewed-by: Alexandre Belloni
Acked-By: Kishon Vijay Abraham I
> ---
> drivers/phy/phy-core.c | 30 ++
> include/linux/phy/phy.h | 26 ++
> 2 files changed, 56 insertions(+)
>
> diff --git a/drive
Hi Nadeem,
On 09/03/21 1:01 pm, Nadeem Athani wrote:
> The parameter detect_quiet_min_delay can be used to program the minimum
> time that LTSSM waits on entering Detect.Quiet state.
> 00 : 0us minimum wait time in Detect.Quiet state.
> 01 : 100us minimum wait time in Detect.Quiet state.
> 10 :
Would prefer simple data transfer tests in the log but other than that
for the patches itself
Reviewed-by: Kishon Vijay Abraham I
>
> Aswath Govindraju (2):
> arm64: dts: ti: k3-am64-main: Add DT node for USB subsystem
> arm64: dts: ti: k3-am642-evm: Add USB support
>
> arc
Add Documentation to help users use PCI endpoint to create virtual
functions using configfs. An endpoint function is designated as a
virtual endpoint function device when it is linked to a physical
endpoint function device (instead of a endpoint controller).
Signed-off-by: Kishon Vijay Abraham I
Populate sriov_configure ops with pci_sriov_configure_simple to
configure SR-IOV device.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index
Now that support for SR-IOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 207 --
drivers/pci/controller/cadence/pcie-cadence.h
While the physical function has to be linked to endpoint controller, the
virtual function has to be linked to a physical function. Add support to
link a physical function to a virtual function in pci-ep-cfs.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 24
Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 44 +++---
.../pci/controller/dwc/pcie
Add binding to specify virtual function (associated with each physical
function) in endpoint mode.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/pci-ep.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation
Add support to add virtual function in endpoint core. The virtual
function can only be associated with a physical function instead of a
endpoint controller. Provide APIs to associate a virtual function with
a physical function here.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint
ttp://lore.kernel.org/r/20191231113534.30405-1-kis...@ti.com
[2] -> http://lore.kernel.org/r/20201112175358.2653-1-kis...@ti.com
[3] -> https://lore.kernel.org/r/20210305050410.9201-1-kis...@ti.com
Kishon Vijay Abraham I (7):
dt-bindings: PCI: pci-ep: Add binding to specify virtual function
PCI:
Do not configure torrent SERDES if it's already configured.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 32 ---
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy
No functional change intended. Group reset APIs and clock APIs in
preparation for adding support to skip configuration if the SERDES
is already configured by bootloader.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 84 ++-
1 file
No functional change. Since the reset controls obtained in
Torrent is exclusively used by the Torrent device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
if any of the lanes has
already been enabled.
Signed-off-by: Faiz Abbas
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
0-1-kis...@ti.com
Faiz Abbas (1):
phy: ti: j721e-wiz: Do not configure wiz if its already configured
Kishon Vijay Abraham I (3):
phy: cadence-torrent: Group reset APIs and clock APIs
phy: cadence-torrent: Do not configure SERDES if it's already
configured
phy: cadence-torrent: Explici
Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/phy/phy-cadence-sierra.yaml| 17 -
include/dt-bindings/phy/phy-cadence.h
Vijay Abraham I
---
drivers/phy/cadence/Kconfig | 1 +
drivers/phy/cadence/phy-cadence-sierra.c | 267 ++-
2 files changed, 265 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index 27e9d6c377e5..a62910ff5591
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 40 ++--
1 file changed, 37 insertions
No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I
---
d
commit 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") enabled
the clock in probe and failed to disable in remove callback. Add missing
clk_disable_unprepare() in cdns_sierra_phy_remove().
Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by:
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11
wiz_init() immediately before invoking
of_platform_device_create().
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.10
---
drivers/phy/ti/phy-j721e-wiz.c | 17 +++--
1 file
d device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 19f32ae877b9.
node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" subnod
re.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.4+
Reviewed-by: Philipp Zabel
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy
://lore.kernel.org/r/20210308050732.7140-1-kis...@ti.com
Kishon Vijay Abraham I (13):
phy: cadence: Sierra: Fix PHY power_on sequence
phy: ti: j721e-wiz: Invoke wiz_init() before
of_platform_device_create()
phy: cadence: cadence-sierra: Create PHY only for "phy" or "link&qu
Hi,
On 10/03/21 5:38 pm, Kishon Vijay Abraham I wrote:
> AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't
> have a clock generator (unlike J7200 base board). Here the clock from
> the SERDES has to be routed to the PCIE connector. This series adds
> support to dri
efclk both in local SERDES
and remote device. Add support here to drive refclk out.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/Kconfig | 1 +
drivers/phy/cadence/phy-cadence-torrent.c | 188 +-
2 files changed, 186 insertions(+), 3 deletion
as a clock, so that platforms like AM642 EVM can
enable it.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 89 ++
1 file changed, 89 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index f9299dcdbdb7
nt
DT node and model the clocks within the driver.
Model the mux clocks without device tree input for AM64x SoC. Don't
remove the earlier design since DT nodes for J7200 and J721e are already
upstreamed.
[1] -> http://lore.kernel.org/r/20210108025943.ga1790...@robh.at.kernel.org
Signed-off-by:
The frequency of the txmclk between PCIe and SERDES has
changed to 250MHz from 500MHz. Configure full rate divider
for AM64 accordingly.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 39 +++---
1 file changed, 36 insertions(+), 3
j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 956a93d96d9b..1a4e09a394a8
wiz_clk_div_sel" and
"struct wiz_clk_mux_sel" and make them point to constant data.
So far no issues are observed since both these structures are not
accessed outside the probe.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 75 +++---
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