the issue.
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
for creating the IRQ domain, the
gpio_irq_chip structure is now filled by the driver itself and then
gpiochip_add_data() takes care of instantiating the IRQ domain for us.
Suggested-by: Andy Shevchenko
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
warning). Hence let's return the error code directly
instead of overriding it with -ENODEV.
Suggested-by: Andy Shevchenko
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
the parent's device pointer and removes the
unnecessary setting of the of_node.
Suggested-by: Andy Shevchenko
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
: Fix interrupt handling")
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
Shevchenko
Looks good to me.
Acked-by: Laxman Dewangan
Biswas
Acked By: Laxman Dewangan
Thanks,
Laxman
to resend them
anymore, you can focus on the remaining patches now.
Question: The nominal maintainer for this driver is
Laxman Dewangan (supporter:TEGRA I2C DRIVER)
I wonder if he is still around and interested?
That aside, thanks a lot Dmitry for the review of this series!
Most of patches
struct rc5t583_regulator.
Signed-off-by: Axel Lin
Acked-by: Laxman Dewangan
On Wednesday 27 March 2019 06:59 AM, Axel Lin wrote:
Add a local variable *desc to avoid too many change lines due to over 80
characters.
Signed-off-by: Axel Lin
Acked-by: Laxman Dewangan
On Wednesday 27 March 2019 06:59 AM, Axel Lin wrote:
Use regulator_set/get_current_limit_regmap helpers to save some code.
Signed-off-by: Axel Lin
Acked-by: Laxman Dewangan
DULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.
Cc: Lee Jones
Cc: Laxman Dewangan
Signed-off-by: Paul Gortmaker
Acked-by: Linus Walleij
Acked-by: Laxman Dewangan
is a no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.
Cc: Lee Jones
Cc: Laxman Dewangan
Signed-off-by: Paul Gortmaker
Acked-by: Linus Walleij
Acked-by: Laxman Dewangan
On Monday 19 November 2018 10:44 PM, Tony Lindgren wrote:
Hi,
* Tony Lindgren [181119 16:19]:
* Peter Ujfalusi [181119 10:16]:
On 2018-11-13 20:06, Tony Lindgren wrote:
Looks like the IRQ_TYPE_NONE issue still is there for omap5 and
should be fixed with IRQ_TYPE_HIGH.
No idea about why
On Monday 19 November 2018 10:44 PM, Tony Lindgren wrote:
Hi,
* Tony Lindgren [181119 16:19]:
* Peter Ujfalusi [181119 10:16]:
On 2018-11-13 20:06, Tony Lindgren wrote:
Looks like the IRQ_TYPE_NONE issue still is there for omap5 and
should be fixed with IRQ_TYPE_HIGH.
No idea about why
-by: Laxman Dewangan
-by: Laxman Dewangan
ssert from the tegra_i2c_init(). So I'd go for
a complete suspend/resume removal for now as it is causes problem.
Laxman, are you convinced or do you have still objections?
Fine with me. Please add my Ack
Acked-by: Laxman Dewangan
ssert from the tegra_i2c_init(). So I'd go for
a complete suspend/resume removal for now as it is causes problem.
Laxman, are you convinced or do you have still objections?
Fine with me. Please add my Ack
Acked-by: Laxman Dewangan
On Monday 14 May 2018 05:29 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, May 14, 2018 at 12:13:47AM +0300, Dmitry Osipenko wrote:
Nothing prevents I2C clients to access I2C while Tegra's driver is being
suspended, this results in -EBUSY error returned to the clients and
On Monday 14 May 2018 05:29 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, May 14, 2018 at 12:13:47AM +0300, Dmitry Osipenko wrote:
Nothing prevents I2C clients to access I2C while Tegra's driver is being
suspended, this results in -EBUSY error returned to the clients and
On Thursday 08 March 2018 08:01 PM, Guenter Roeck wrote:
On 03/07/2018 10:06 PM, Laxman Dewangan wrote:
The RPM is measured speed via PWM signal capture which is output
from fan.
So should we have the fan[1..n]_output_rpm?
No. I hear you clearly that you for some reason dislike fan[1
On Thursday 08 March 2018 08:01 PM, Guenter Roeck wrote:
On 03/07/2018 10:06 PM, Laxman Dewangan wrote:
The RPM is measured speed via PWM signal capture which is output
from fan.
So should we have the fan[1..n]_output_rpm?
No. I hear you clearly that you for some reason dislike fan[1
On Wednesday 07 March 2018 07:50 PM, Guenter Roeck wrote:
On 03/07/2018 01:47 AM, Rajkumar Rampelli wrote:
While I am not opposed to ABI changes, the merits of those would
need to be
discussed on the mailing list. But replacing "fan1_input" with "rpm" is
not an acceptable ABI change,
On Wednesday 07 March 2018 07:50 PM, Guenter Roeck wrote:
On 03/07/2018 01:47 AM, Rajkumar Rampelli wrote:
While I am not opposed to ABI changes, the merits of those would
need to be
discussed on the mailing list. But replacing "fan1_input" with "rpm" is
not an acceptable ABI change,
On Tuesday 06 March 2018 05:23 AM, Gustavo A. R. Silva wrote:
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva <gust...@embeddedor.com>
Acked-by: Laxman Dewangan &
On Tuesday 06 March 2018 05:23 AM, Gustavo A. R. Silva wrote:
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva
Acked-by: Laxman Dewangan
On Wednesday 07 February 2018 09:07 PM, Mark Brown wrote:
On Wed, Feb 07, 2018 at 05:20:45PM +0200, Peter De Schrijver wrote:
On Wed, Feb 07, 2018 at 03:01:55PM +, Mark Brown wrote:
I can't really tell what you're saying here. If the driver needs to
know if it can set the a given
On Wednesday 07 February 2018 09:07 PM, Mark Brown wrote:
On Wed, Feb 07, 2018 at 05:20:45PM +0200, Peter De Schrijver wrote:
On Wed, Feb 07, 2018 at 03:01:55PM +, Mark Brown wrote:
I can't really tell what you're saying here. If the driver needs to
know if it can set the a given
Acked-by: Laxman Dewangan <ldewan...@nvidia.com>
On Friday 08 December 2017 01:49 AM, SF Markus Elfring wrote:
From: Markus Elfring
Date: Thu, 7 Dec 2017 21:00:05 +0100
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Acked-by: Laxman Dewangan
On Friday 08 December 2017 01:51 AM, SF Markus Elfring wrote:
From: Markus Elfring <elfr...@users.sourceforge.net>
Date: Thu, 7 Dec 2017 21:06:25 +0100
Delete a duplicate character in a word of this description.
Acked-by: Laxman Dewangan <ldewan...@nvidia.com>
On Friday 08 December 2017 01:51 AM, SF Markus Elfring wrote:
From: Markus Elfring
Date: Thu, 7 Dec 2017 21:06:25 +0100
Delete a duplicate character in a word of this description.
Acked-by: Laxman Dewangan
-devm version of thermal_zone_of_sensor_register().
Now the devm_iio_channel_get() is available, do the corresponding change in
this driver and remove gadc_thermal_remove().
Acked-by: Laxman Dewangan <ldewan...@nvidia.com>
Thanks,
Laxman
-devm version of thermal_zone_of_sensor_register().
Now the devm_iio_channel_get() is available, do the corresponding change in
this driver and remove gadc_thermal_remove().
Acked-by: Laxman Dewangan
Thanks,
Laxman
On Wednesday 19 July 2017 06:55 PM, Johan Hovold wrote:
On Fri, Apr 07, 2017 at 12:25:49PM +0200, Linus Walleij wrote:
On Thu, Apr 6, 2017 at 3:35 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and acti
On Wednesday 19 July 2017 06:55 PM, Johan Hovold wrote:
On Fri, Apr 07, 2017 at 12:25:49PM +0200, Linus Walleij wrote:
On Thu, Apr 6, 2017 at 3:35 PM, Laxman Dewangan wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said
On Tuesday 02 May 2017 11:13 PM, Laxman Dewangan wrote:
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
On 02/05/17 15:05, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 38.4MHz
On Tuesday 02 May 2017 11:13 PM, Laxman Dewangan wrote:
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
On 02/05/17 15:05, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 38.4MHz
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
On 02/05/17 15:05, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 38.4MHz.
In Tegra186, it is 102MHz.
Add support to limit
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
On 02/05/17 15:05, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 38.4MHz.
In Tegra186, it is 102MHz.
Add support to limit
SoC chipdata.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Changes from V1:
- Set the 48MHz maximum frequency for Tegra210 and earlier.
- Set the maximum frequency unconditionally as per V1 review comment.
---
drivers/pwm/pwm-tegra.c | 18 +-
1 file changed, 17 i
SoC chipdata.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Set the 48MHz maximum frequency for Tegra210 and earlier.
- Set the maximum frequency unconditionally as per V1 review comment.
---
drivers/pwm/pwm-tegra.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
d
org>
---
Acked-by: Laxman Dewangan <ldewan...@nvidia.com>
On Tuesday 02 May 2017 12:07 AM, Matthias Kaehlcke wrote:
Some regulators have different settling times for voltage increases and
decreases. Add DT properties to define separate settling times for up-
and downward voltage changes.
Signed-off-by: Matthias Kaehlcke
---
Acked-by: Laxman
t;m...@chromium.org>
---
Acked-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Acked-by: Laxman Dewangan
On Saturday 29 April 2017 05:36 AM, Matthias Kaehlcke wrote:
Some regulators have different settling times for voltage increases and
decreases. To avoid a time penalty on the faster transition extend the
settling time property to allow for different settings for upward and
downward transitions.
On Saturday 29 April 2017 05:36 AM, Matthias Kaehlcke wrote:
Some regulators have different settling times for voltage increases and
decreases. To avoid a time penalty on the faster transition extend the
settling time property to allow for different settings for upward and
downward transitions.
: Venkat Reddy Talla <vreddyta...@nvidia.com>
Signed-off-by: Fengguang Wu <fengguang...@intel.com>
---
LGTM,
Acked-by: Laxman Dewangan <ldewan...@nvidia.com>
: Venkat Reddy Talla
Signed-off-by: Fengguang Wu
---
LGTM,
Acked-by: Laxman Dewangan
On Thursday 13 April 2017 08:57 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Apr 13, 2017 at 07:40:28PM +0530, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
For Tegra210, it is 38.4MHz
On Thursday 13 April 2017 08:57 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Apr 13, 2017 at 07:40:28PM +0530, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
For Tegra210, it is 38.4MHz
SoC chipdata.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
drivers/pwm/pwm-tegra.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 8c6ed55..7016c08 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/driver
SoC chipdata.
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 8c6ed55..7016c08 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -4
in avoiding the clock call for getting clock rate
in the pwm_config() each time.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
drivers/pwm/pwm-tegra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index c
in avoiding the clock call for getting clock rate
in the pwm_config() each time.
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index c040f87..8c6ed55 100644
On Friday 07 April 2017 03:55 PM, Linus Walleij wrote:
On Thu, Apr 6, 2017 at 3:35 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and
On Friday 07 April 2017 03:55 PM, Linus Walleij wrote:
On Thu, Apr 6, 2017 at 3:35 PM, Laxman Dewangan wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and active HIGH.
The active HIGH
devices
require the PWM output to be tristated.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Changes from v1:
- Use standard pinctrl names for sleep and active state.
- U
devices
require the PWM output to be tristated.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Use standard pinctrl names for sleep and active state.
- Use API pinctrl_pm_select_
devices
require the PWM output to be tristated.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Changes from v1:
- Use standard pinctrl names for
devices
require the PWM output to be tristated.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Use standard pinctrl names for sleep and active state
on old formula:
hz = 59, rate = 3390
Based on new formula:
hz = 5951, rate = 3360
The PWM signal rate of 3360 is more near to requested period than .
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Changes from v1:
- None
Change
on old formula:
hz = 59, rate = 3390
Based on new formula:
hz = 5951, rate = 3360
The PWM signal rate of 3360 is more near to requested period than .
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- None
Changes from V2:
- Fix the commit
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closest one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Changes from v1:
- None
Changes from V2:
- Fix typo in commit message.
---
drivers/pwm/pwm-t
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closest one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- None
Changes from V2:
- Fix typo in commit message.
---
drivers/pwm/pwm-tegra.c | 3 +--
1 file
pinctrl_pm_select_*()
Changes from V2:
- Type fixes, rephrases commit message and use pinctrl_pm_state* return
value.
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
implementation
pwm: tegra: Increase precision in pwm rate calculation
pwm: tegra: Add DT
pinctrl_pm_select_*()
Changes from V2:
- Type fixes, rephrases commit message and use pinctrl_pm_state* return
value.
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
implementation
pwm: tegra: Increase precision in pwm rate calculation
pwm: tegra: Add DT
On Thursday 06 April 2017 09:40 PM, Andy Shevchenko wrote:
On Thu, Apr 6, 2017 at 4:35 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single
On Thursday 06 April 2017 09:40 PM, Andy Shevchenko wrote:
On Thu, Apr 6, 2017 at 4:35 PM, Laxman Dewangan wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and active HIGH.
The active
On Thursday 06 April 2017 08:56 PM, Jon Hunter wrote:
On 06/04/17 15:21, Laxman Dewangan wrote:
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty cycle of PWM signal decide
On Thursday 06 April 2017 08:56 PM, Jon Hunter wrote:
On 06/04/17 15:21, Laxman Dewangan wrote:
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty cycle of PWM signal decide
Oops, it was actually v2.
On Thursday 06 April 2017 08:47 PM, Jon Hunter wrote:
On 06/04/17 15:21, Laxman Dewangan wrote:
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty
Oops, it was actually v2.
On Thursday 06 April 2017 08:47 PM, Jon Hunter wrote:
On 06/04/17 15:21, Laxman Dewangan wrote:
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty
pinctrl_pm_select_*()
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
implementation
pwm: tegra: Increase precision in pwm rate calculation
pwm: tegra: Add DT binding details to configure pin in suspends/resume
pwm: tegra: Add support to configure pin state
pinctrl_pm_select_*()
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
implementation
pwm: tegra: Increase precision in pwm rate calculation
pwm: tegra: Add DT binding details to configure pin in suspends/resume
pwm: tegra: Add support to configure pin state
formula:
hz = 60, rate =
Based on new formula:
hz = 5951, rate = 3360
The rate of 3360 is more near to requested period then the .
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Changes from V1:
- None
drivers/pwm/pwm-tegra
formula:
hz = 60, rate =
Based on new formula:
hz = 5951, rate = 3360
The rate of 3360 is more near to requested period then the .
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- None
drivers/pwm/pwm-tegra.c | 8 ++--
1 file
define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Changes from v1:
- Use standard p
define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Use standard pinctrl names for sleep
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
Changes from V1:
None
drivers/pwm/pwm-tegra.c | 3 +--
1 file changed, 1 insertion(+), 2 del
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
None
drivers/pwm/pwm-tegra.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers
define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
C
define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Use standard
only when Single ended flag is enabled.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
drivers/gpio/gpiolib-of.c | 2 +-
drivers/gpio/gpiolib.c | 4 +++-
include/dt-bindings/gpio/gpio.h | 12
include/linux/of_gpio.h | 1 +
4 files chang
only when Single ended flag is enabled.
Signed-off-by: Laxman Dewangan
---
drivers/gpio/gpiolib-of.c | 2 +-
drivers/gpio/gpiolib.c | 4 +++-
include/dt-bindings/gpio/gpio.h | 12
include/linux/of_gpio.h | 1 +
4 files changed, 13 insertions(+), 6 deletions
On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote:
On 05/04/17 15:13, Laxman Dewangan wrote:
+state of the system. The configuration of pin is provided via the pinctrl
+DT node as detailed
On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote:
On 05/04/17 15:13, Laxman Dewangan wrote:
+state of the system. The configuration of pin is provided via the pinctrl
+DT node as detailed
This patch series have following fixes:
- Add more precession in PWM period register value calculation
for lower pwm frequency.
- Add support to configure PWM pins in different state in the
suspend/resume.
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
This patch series have following fixes:
- Add more precession in PWM period register value calculation
for lower pwm frequency.
- Add support to configure PWM pins in different state in the
suspend/resume.
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
drivers/pwm/pwm-tegra.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/d
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-tegra.c b
formula:
hz = 60, rate =
Based on new formula:
hz = 5951, rate = 3360
The rate of 3360 is more near to requested period then the .
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
drivers/pwm/pwm-tegra.c | 8 ++--
1 file c
formula:
hz = 60, rate =
Based on new formula:
hz = 5951, rate = 3360
The rate of 3360 is more near to requested period then the .
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 8 ++--
1 file changed, 6 insertions(+), 2
define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
drivers/pwm/pwm-tegra.
define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 66
define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.
define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan
---
.../devicetree/bindings/pwm
settling time.
Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
---
This patch is continuation of discussion on patch
regulator: pwm: Fix regulator ramp delay for continuous mode
https://patchwork.kernel.org/patch/9216857/
where is it discussed to have separate property for PWM whi
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