On 4/20/21 3:32 PM, Keqian Zhu wrote:
Hi Baolu,
Cheers for the your quick reply.
On 2021/4/20 10:09, Lu Baolu wrote:
Hi Keqian,
On 4/20/21 9:25 AM, Keqian Zhu wrote:
Hi Baolu,
On 2021/4/19 21:33, Lu Baolu wrote:
Hi Keqian,
On 2021/4/19 17:32, Keqian Zhu wrote:
+EXPORT_SYMBOL_GPL
Hi Keqian,
On 4/20/21 9:25 AM, Keqian Zhu wrote:
Hi Baolu,
On 2021/4/19 21:33, Lu Baolu wrote:
Hi Keqian,
On 2021/4/19 17:32, Keqian Zhu wrote:
+EXPORT_SYMBOL_GPL(iommu_split_block);
Do you really have any consumers of this interface other than the dirty
bit tracking? If not, I don't
Hi Keqian,
On 2021/4/19 17:32, Keqian Zhu wrote:
+EXPORT_SYMBOL_GPL(iommu_split_block);
Do you really have any consumers of this interface other than the dirty
bit tracking? If not, I don't suggest to make this as a generic IOMMU
interface.
There is an implicit requirement for such
Hi Bingbu,
On 4/19/21 12:57 PM, Bingbu Cao wrote:
Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
The IPU driver allocates its own page table that is not mapped
via the DMA, and thus the Intel IOMMU driver blocks access giving
this error:
DMAR: DRHD: handling fault status reg 3
Hi Keqian,
On 4/16/21 5:07 PM, Keqian Zhu wrote:
I am worrying about having two sets of APIs for single purpose. From
vendor iommu driver's point of view, this feature is per device. Hence,
it still needs to do the same thing.
Yes, we can unify the granule of feature reporting and status
Hi,
On 2021/4/15 15:43, Keqian Zhu wrote:
design it as not switchable. I will modify the commit message of patch#12,
thanks!
I am not sure that I fully get your point. But I can't see any gaps of
using iommu_dev_enable/disable_feature() to switch dirty log on and off.
Probably I missed
On 4/15/21 2:18 PM, Keqian Zhu wrote:
Hi Baolu,
Thanks for the review!
On 2021/4/14 15:00, Lu Baolu wrote:
Hi Keqian,
On 4/13/21 4:54 PM, Keqian Zhu wrote:
Some types of IOMMU are capable of tracking DMA dirty log, such as
ARM SMMU with HTTU or Intel IOMMU with SLADE. This introduces
: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse
Cc: Lu Baolu
Cc: Nadav Amit
Cc: Alex
Hi Jason,
On 4/14/21 7:26 PM, Jason Gunthorpe wrote:
On Wed, Apr 14, 2021 at 02:22:09PM +0800, Lu Baolu wrote:
I still worry about supervisor pasid allocation.
If we use iommu_sva_alloc_pasid() to allocate a supervisor pasid, which
mm should the pasid be set? I've ever thought about passing
On 4/13/21 4:54 PM, Keqian Zhu wrote:
Block(largepage) mapping is not a proper granule for dirty log tracking.
Take an extreme example, if DMA writes one byte, under 1G mapping, the
dirty amount reported is 1G, but under 4K mapping, the dirty amount is
just 4K.
This adds a new interface named
Hi Keqian,
On 4/13/21 4:54 PM, Keqian Zhu wrote:
Some types of IOMMU are capable of tracking DMA dirty log, such as
ARM SMMU with HTTU or Intel IOMMU with SLADE. This introduces the
dirty log tracking framework in the IOMMU base layer.
Three new essential interfaces are added, and we
Hi Jacob,
On 4/14/21 8:09 AM, Jacob Pan wrote:
Hi Jean,
On Fri, 9 Apr 2021 11:03:05 -0700, Jacob Pan
wrote:
problems:
* We don't have a use-case for binding the mm of a remote process (and
it's supposedly difficult for device drivers to do it securely). So
OK, we remove the mm argument
Hi Gustavo,
On 4/14/21 3:54 AM, Gustavo A. R. Silva wrote:
Replace call to memcpy() with just a couple of simple assignments in
order to fix the following out-of-bounds warning:
drivers/iommu/intel/svm.c:1198:4: warning: 'memcpy' offset [25, 32] from the
object at 'desc' is out of the bounds
I guess you need to ask Greg KH with this
Cc-ing to sta...@vger.kernel.org.
Best regards,
baolu
On 2021/4/12 3:36, Saeed Mirzamohammadi wrote:
Hi Lu,
Thanks for the review. May I know when do we expect this to be applied
to 5.4?
Thanks,
Saeed
On Apr 7, 2021, at 5:25 PM, Lu Baolu
goto error;
+ return -ENODEV;
if (!dmar_ir_support())
return -ENODEV;
Thanks!
Acked-by: Lu Baolu
Best regards,
baolu
andy Dunlap
Fixes: f68c7f539b6e9 ("iommu/vt-d: Enable write protect for supervisor SVM")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 477b2e1d303c..72646bafc52
Hi,
On 2021/4/9 1:08, Jacob Pan wrote:
/**
* iommu_sva_alloc_pasid - Allocate a PASID for the mm
- * @mm: the mm
* @min: minimum PASID value (inclusive)
* @max: maximum PASID value (inclusive)
*
- * Try to allocate a PASID for this mm, or take a reference to the existing one
- *
Hi Jacob,
On 2021/4/9 1:08, Jacob Pan wrote:
The void* drvdata parameter isn't really used in iommu_sva_bind_device()
API, the current IDXD code "borrows" the drvdata for a VT-d private flag
for supervisor SVA usage.
Supervisor/Privileged mode request is a generic feature. It should be
Hi Longpeng,
On 4/8/21 3:37 PM, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
Hi Baolu,
-Original Message-
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Thursday, April 8, 2021 12:32 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
; io
Hi Longpeng,
On 4/7/21 2:35 PM, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
Hi Baolu,
-Original Message-
From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Friday, April 2, 2021 12:44 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
; io
= cap_width;
domain->gaw = guest_width;
adjust_width = guestwidth_to_adjustwidth(guest_width);
agaw = width_to_agaw(adjust_width);
Reviewed-by: Lu Baolu
Best regards,
baolu
Hi Jason,
On 4/7/21 4:00 AM, Jason Gunthorpe wrote:
On Mon, Mar 25, 2019 at 09:30:34AM +0800, Lu Baolu wrote:
A parent device might create different types of mediated
devices. For example, a mediated device could be created
by the parent device with full isolation and protection
provided
Hi Saeed,
On 4/7/21 12:35 AM, Saeed Mirzamohammadi wrote:
The IOMMU driver calculates the guest addressability for a DMA request
based on the value of the mgaw reported from the IOMMU. However, this
is a fused value and as mentioned in the spec, the guest width
should be calculated based on the
On 3/20/21 10:54 AM, Lu Baolu wrote:
When first-level page tables are used for IOVA translation, we use user
privilege by setting U/S bit in the page table entry. This is to make it
consistent with the second level translation, where the U/S enforcement
is not available. Clear the SRE
On 4/2/21 11:41 AM, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
Hi Baolu,
在 2021/4/2 11:06, Lu Baolu 写道:
Hi Longpeng,
On 4/1/21 3:18 PM, Longpeng(Mike) wrote:
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following
Hi Longpeng,
On 4/1/21 3:18 PM, Longpeng(Mike) wrote:
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index ee09323..cbcb434 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -2342,9 +2342,20 @@ static inline int hardware_largepage_caps(struct
: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse
Cc: Lu Baolu
Cc: Nadav Amit
Cc: Alex
Ashok Raj
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.h | 1 +
drivers/iommu/intel/iommu.c | 11 ++-
drivers/iommu/intel/pasid.c | 16
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index 07
Hi Nadav,
On 3/27/21 12:36 PM, Nadav Amit wrote:
On Mar 26, 2021, at 7:31 PM, Lu Baolu wrote:
Hi Nadav,
On 3/19/21 12:46 AM, Nadav Amit wrote:
So here is my guess:
Intel probably used as a basis for the IOTLB an implementation of
some other (regular) TLB design.
Intel SDM says regarding
Hi Nadav,
On 3/19/21 12:46 AM, Nadav Amit wrote:
So here is my guess:
Intel probably used as a basis for the IOTLB an implementation of
some other (regular) TLB design.
Intel SDM says regarding TLBs (4.10.4.2 “Recommended Invalidation”):
"Software wishing to prevent this uncertainty should
Hi Christoph,
On 3/24/21 1:33 AM, Christoph Hellwig wrote:
On Tue, Mar 23, 2021 at 09:05:58AM +0800, Lu Baolu wrote:
The SVM_FLAG_PRIVATE_PASID has never been referenced in the tree, and
there's no plan to have anything to use it. So cleanup it.
Signed-off-by: Lu Baolu
Looks good
@ -57,7 +57,6 @@ enum cpuhp_state {
CPUHP_PAGE_ALLOC_DEAD,
CPUHP_NET_DEV_DEAD,
CPUHP_PCI_XGENE_DEAD,
- CPUHP_IOMMU_INTEL_DEAD,
CPUHP_IOMMU_IOVA_DEAD,
CPUHP_LUSTRE_CFS_DEAD,
CPUHP_AP_ARM_CACHE_B15_RAC_DEAD,
Reviewed-by: Lu Baolu
Best regards,
baolu
Make some functions static as they are only used inside pasid.c.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 4 ++--
drivers/iommu/intel/pasid.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index
The svm_dev_ops has never been referenced in the tree, and there's no
plan to have anything to use it. Remove it to make the code neat.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/svm.c | 15 +--
include/linux/intel-iommu.h | 3 ---
include/linux/intel-svm.h | 7 ---
3
The SVM_FLAG_PRIVATE_PASID has never been referenced in the tree, and
there's no plan to have anything to use it. So cleanup it.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/svm.c | 40 ++-
include/linux/intel-svm.h | 16 +++-
2 files changed
Hi Joerg et al,
This series includes several cleanups in the VT-d driver. Please help to
review.
Best regards,
baolu
Lu Baolu (5):
iommu/vt-d: Remove unused dma map/unmap trace events
iommu/vt-d: Remove svm_dev_ops
iommu/vt-d: Remove SVM_FLAG_PRIVATE_PASID
iommu/vt-d: Remove unused
With commit c588072bba6b5 ("iommu/vt-d: Convert intel iommu driver to
the iommu ops"), the trace events for dma map/unmap have no users any
more. Cleanup them to make the code neat.
Signed-off-by: Lu Baolu
---
include/trace/events/intel_iommu.h | 120 ---
Some functions have been deprecated. Remove the remaining function
delarations.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index 444c0bec221a..90a3268d7a77 100644
-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index dd69df5a188a..7a73385edcc0 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -502,6 +502,9 @@ void
mu/vt-d: Setup context and enable RID2PASID support")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 18 +-
include/linux/intel-iommu.h | 1 +
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iom
table entry of RID2PASID so that requests requesting the supervisor
privilege are blocked and treated as DMA remapping faults.
Suggested-by: Jacob Pan
Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 7 +--
dri
ons on second-level paging entries
- Refine the commit message to make the intention clear.
Lu Baolu (5):
iommu/vt-d: Report the right page fault address
iommu/vt-d: Remove WO permissions on second-level paging entries
iommu/vt-d: Invalidate PASID cache when root/context entry changed
io
The Address field of the Page Request Descriptor only keeps bit [63:12]
of the offending address. Convert it to a full address before reporting
it to device drivers.
Fixes: eb8d93ea3c1d3 ("iommu/vt-d: Report page request faults for guest SVA")
Signed-off-by: Lu Baolu
---
drivers/i
/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 167219ea8d70..132cbf9f214f 100644
--- a/drivers/iommu/intel/iommu.c
+++
cleared in prq_event_thread(). This breaks the rule defined
by the VT-d specification. Fix it by moving clearing code up.
Fixes: 5b438f4ba315d ("iommu/vt-d: Support page request in scalable mode")
Cc: Jacob Pan
Reviewed-by: Liu Yi L
Signed-off-by: Lu Baolu
---
drivers/iommu/intel
e pasid_lock with an atomic exchange operation.
Reported-and-tested-by: Dave Jiang
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
Log:
v1->v2:
- v1:
https://lore.kernel.org/linux-iommu/20210317005834
On 3/19/21 9:30 AM, Keqian Zhu wrote:
Hi Baolu,
On 2021/3/19 8:33, Lu Baolu wrote:
On 3/18/21 7:53 PM, Shenming Lu wrote:
On 2021/3/18 17:07, Tian, Kevin wrote:
From: Shenming Lu
Sent: Thursday, March 18, 2021 3:53 PM
On 2021/2/4 14:52, Tian, Kevin wrote:>>> In reality, many
devi
Hi Joerg,
On 3/18/21 6:10 PM, Joerg Roedel wrote:
Hi Baolu,
On Tue, Mar 09, 2021 at 08:46:41AM +0800, Lu Baolu wrote:
The private data field of a page group response descriptor is set then
immediately cleared in prq_event_thread(). Fix this by moving clearing
code up.
Fixes: 5b438f4ba315d
Hi Joerg,
On 3/18/21 6:21 PM, Joerg Roedel wrote:
On Wed, Mar 17, 2021 at 08:58:34AM +0800, Lu Baolu wrote:
The pasid_lock is used to synchronize different threads from modifying a
same pasid directory entry at the same time. It causes below lockdep splat.
[ 83.296538
On 3/18/21 7:53 PM, Shenming Lu wrote:
On 2021/3/18 17:07, Tian, Kevin wrote:
From: Shenming Lu
Sent: Thursday, March 18, 2021 3:53 PM
On 2021/2/4 14:52, Tian, Kevin wrote:>>> In reality, many
devices allow I/O faulting only in selective contexts. However, there
is no standard way (e.g.
Hi Joerg,
On 3/18/21 5:12 PM, Joerg Roedel wrote:
Hi,
On Mon, Mar 08, 2021 at 11:47:46AM -0800, Raj, Ashok wrote:
That is the primary motivation, given that we have moved to 1st level for
general IOVA, first level doesn't have a WO mapping. I didn't know enough
about the history to determine
On 3/18/21 4:56 PM, Tian, Kevin wrote:
From: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
-Original Message-
From: Tian, Kevin [mailto:kevin.t...@intel.com]
Sent: Thursday, March 18, 2021 4:27 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
; Nadav
Hi Nadav,
On 3/18/21 2:12 AM, Nadav Amit wrote:
On Mar 17, 2021, at 2:35 AM, Longpeng (Mike, Cloud Infrastructure Service Product
Dept.) wrote:
Hi Nadav,
-Original Message-
From: Nadav Amit [mailto:nadav.a...@gmail.com]
reproduce the problem with high probability (~50%).
I
Hi Alex,
On 3/17/21 11:18 PM, Alex Williamson wrote:
{MAP, 0x0, 0xc000}, - (b)
use GDB to pause at here, and then DMA read IOVA=0,
IOVA 0 seems to be a special one. Have you verified with other addresses
than IOVA 0?
It is???
When the invalidation queue errors are encountered, dump the information
logged by the VT-d hardware together with the pending queue invalidation
descriptors.
Signed-off-by: Ashok Raj
Tested-by: Guo Kaijie
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/dmar.c | 68
Hi Longpeng,
On 3/17/21 11:16 AM, Longpeng (Mike, Cloud Infrastructure Service
Product Dept.) wrote:
Hi guys,
We find the Intel iommu cache (i.e. iotlb) maybe works wrong in a special
situation, it would cause DMA fails or get wrong data.
The reproducer (based on Alex's vfio testsuite[1]) is
e pasid_lock with an atomic exchange operation.
Reported-and-tested-by: Dave Jiang
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index
)
return -EINVAL;
+ if (!info->pasid_enabled || !info->pri_enabled || !info->ats_enabled)
+ return -EINVAL;
+
if (info->iommu->flags & VTD_FLAG_SVM_CAPABLE)
return 0;
}
Thanks for the p
Hi Shenming,
On 3/9/21 2:22 PM, Shenming Lu wrote:
This patch follows the discussion here:
https://lore.kernel.org/linux-acpi/YAaxjmJW+ZMvrhac@myrica/
In order to support more scenarios of using IOPF (mainly consider
the nested extension), besides keeping IOMMU_DEV_FEAT_IOPF as a
general
The private data field of a page group response descriptor is set then
immediately cleared in prq_event_thread(). Fix this by moving clearing
code up.
Fixes: 5b438f4ba315d ("iommu/vt-d: Support page request in scalable mode")
Cc: Jacob Pan
Reviewed-by: Liu Yi L
Signed-off-by
Hi Joerg,
On 3/4/21 8:26 PM, Joerg Roedel wrote:
On Thu, Feb 25, 2021 at 02:26:51PM +0800, Lu Baolu wrote:
When the first level page table is used for IOVA translation, it only
supports Read-Only and Read-Write permissions. The Write-Only permission
is not supported as the PRESENT bit
-git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h
index 706b68d1359b..13d1f4c14d7b 100644
--- a/include/linux/dma-iommu.h
+++ b/include/linux/dma-iommu.h
@@ -40,6 +40,8 @@ void iommu_dma_get_resv_regions(struct device *dev, struct
list_head *list);
void iommu_dma_free_cpu_cached_iovas(unsigned int cpu
return -EINVAL;
}
pasid_set_sre(pte);
+ if (pasid_enable_wpe(pte))
+ return -EINVAL;
+
}
if (flags & PASID_FLAG_FL5LP) {
Acked-by: Lu Baolu
Best regards,
baolu
ID_WPE (1 << 6) /* Write protect enable */
+#define IOMMU_SVA_VTD_GPASID_LAST (1 << 7)
__u64 flags;
__u32 pat;
__u32 emt;
Acked-by: Lu Baolu
Best regards,
baolu
((e) >> 8) & 0xf)
#define VCMD_CMD_OPERAND(e) ((e) << 8)
/*
Thanks a lot for catching this.
Acked-by: Lu Baolu
Best regards,
baolu
-by: Lu Baolu
---
drivers/iommu/intel/pasid.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 07531e5edfa2..9fb3d3e80408 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -493,6 +493,9 @@ void
table entry of RID2PASID so that requests requesting the supervisor
privilege are blocked and treated as DMA remapping faults.
Suggested-by: Jacob Pan
Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 7 +--
dri
WriteOnly which seems inconsistent and awkward. There is no
use case we can think off, hence remove that configuration to make it
consistent.
Suggested-by: Ashok Raj
Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c
The Address field of the Page Request Descriptor only keeps bit [63:12]
of the offending address. Convert it to a full address before reporting
it to device drivers.
Fixes: eb8d93ea3c1d3 ("iommu/vt-d: Report page request faults for guest SVA")
Signed-off-by: Lu Baolu
---
drivers/i
mu/vt-d: Setup context and enable RID2PASID support")
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 18 +-
include/linux/intel-iommu.h | 1 +
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iom
Hi Joerg,
This series includes some misc fixes for the VT-d iommu driver. Please
help to review and merge.
Best regards,
baolu
Lu Baolu (5):
iommu/vt-d: Report the right page fault address
iommu/vt-d: Remove WO permissions on second-level paging entries
iommu/vt-d: Invalidate PASID cache
obtain.
Fixes: c588072bba6b5 ("iommu/vt-d: Convert intel iommu driver to the iommu ops")
Signed-off-by: Lu Baolu
---
drivers/iommu/dma-iommu.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index f6
key enforcement. Therefore, we should set FAULT_FLAG_REMOTE
to avoid faults when both SVM and PKEY are used.
References: commit 1b2ee1266ea6 ("mm/core: Do not enforce PKEY permissions on remote
mm access")
Reviewed-by: Raj Ashok
Signed-off-by: Jacob Pan
Acked-by: Lu Baolu
Best r
configurations,
reject them both with invalid responses.
Signed-off-by: Jacob Pan
Fixes: 1c4f88b7f1f92 ("iommu/vt-d: Shared virtual address in scalable mode")
Acked-by: Lu Baolu
Best regards,
baolu
---
drivers/iommu/intel/svm.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletio
Hi Jacob and Sanjay,
On 2/19/21 5:31 AM, Jacob Pan wrote:
Write protect bit, when set, inhibits supervisor writes to the read-only
pages. In supervisor shared virtual addressing (SVA), where page tables
are shared between CPU and DMA, IOMMU PASID entry WPE bit should match
CR0.WP bit in the
Hi Leon,
On 2/8/21 4:21 PM, Leon Romanovsky wrote:
On Wed, Feb 03, 2021 at 12:56:44PM -0800, Megha Dey wrote:
From: Lu Baolu
The pci_subdevice_msi_create_irq_domain() should fail if the underlying
platform is not able to support IMS (Interrupt Message Storage). Otherwise,
the isolation
Hi Jason,
On 2021/2/4 20:14, Jason Gunthorpe wrote:
On Wed, Feb 03, 2021 at 12:56:44PM -0800, Megha Dey wrote:
+bool arch_support_pci_device_ims(struct pci_dev *pdev)
+{
Consistent language please, we are not using IMS elsewhere, this
feature is called device_msi in Linux.
Thanks for
Hi Kevin,
On 2/4/21 9:59 AM, Tian, Kevin wrote:
From: Lu Baolu
Sent: Wednesday, February 3, 2021 5:33 PM
From: Yian Chen
Starting from Intel VT-d v3.2, Intel platform BIOS can provide a new SATC
table structure. SATC table lists a set of SoC integrated devices that
require ATC to work (VT-d
Add the change log. Sorry for the quick sent.
On 2021/2/3 17:33, Lu Baolu wrote:
The Intel VT-d specification v3.2 comes with a new ACPI SATC (SoC-
Integrated Address Translation Cache) reporting structure. The SoC
integrated device enumerated in this table has a functional
requirement
to the software. As the
result, software shouldn't enable ATS on that device, otherwise duplicate
device TLB invalidations will occur.
Signed-off-by: Yian Chen
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 73 +++--
1 file changed, 69 insertions(+), 4 deletions
The Intel VT-d specification v3.2 comes with a new ACPI SATC (SoC-
Integrated Address Translation Cache) reporting structure. The SoC
integrated device enumerated in this table has a functional
requirement to enable its ATC (Address Translation Cache) via the
ATS capability for device operation.
as needed.
Signed-off-by: Yian Chen
Signed-off-by: Lu Baolu
---
include/acpi/actbl1.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 43549547ed3e..c38e08cf1b9e 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi
From: Yian Chen
Software should parse every SATC table and all devices in the tables
reported by the BIOS and keep the information in kernel list for further
reference.
Signed-off-by: Yian Chen
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/dmar.c | 8
drivers/iommu/intel/iommu.c
Hi Christoph,
On 2021/2/3 16:41, Christoph Hellwig wrote:
On Tue, Feb 02, 2021 at 12:40:54PM +0800, Lu Baolu wrote:
Intel platform VT-d (v3.2) comes with a new type of DMAR subtable
SATC. The SATC table includes a list of SoC integrated devices
that require SATC. OS software can use this table
On 2/2/21 9:55 PM, Joerg Roedel wrote:
On Tue, Feb 02, 2021 at 12:40:57PM +0800, Lu Baolu wrote:
+ list_for_each_entry_rcu(satcu, _satc_units, list) {
+ satc = container_of(satcu->hdr, struct acpi_dmar_satc, header);
+ if (satc->segment == pci_domain_
Hi Ashok,
On 2/3/21 12:41 AM, Raj, Ashok wrote:
On Tue, Feb 02, 2021 at 12:40:56PM +0800, Lu Baolu wrote:
From: Yian Chen
Software should parse every SATC table and all devices in the tables
reported by the BIOS and keep the information in kernel list for further
SATC policy deployment
Hi Joerg,
On 2/2/21 9:53 PM, Joerg Roedel wrote:
On Tue, Feb 02, 2021 at 12:40:56PM +0800, Lu Baolu wrote:
+ case ACPI_DMAR_TYPE_SATC:
+ satc = container_of(header, struct acpi_dmar_satc, header);
+ pr_info("SATC flags: 0x%x\n", s
Hi Ashok,
On 2/3/21 12:02 AM, Raj, Ashok wrote:
On Tue, Feb 02, 2021 at 12:40:55PM +0800, Lu Baolu wrote:
From: Yian Chen
Starting from Intel Platform VT-d v3.2, BIOS may provide new remapping
structure SATC for SOC integrated devices, according to section 8.8 of
Intel VT-d architecture
Hi Joerg,
On 2/2/21 9:51 PM, Joerg Roedel wrote:
Hi Baolu,
On Tue, Feb 02, 2021 at 12:40:55PM +0800, Lu Baolu wrote:
@@ -514,7 +514,8 @@ enum acpi_dmar_type {
ACPI_DMAR_TYPE_ROOT_ATS = 2,
ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,
ACPI_DMAR_TYPE_NAMESPACE = 4
From: Yian Chen
Starting from Intel VT-d v3.2, Intel platform BIOS can provide a new SATC
table structure. SATC table lists a set of SoC integrated devices that
require ATC to work (VT-d specification v3.2, section 8.8). Furthermore,
the new version of IOMMU supports SoC device ATS in both its
From: Yian Chen
Software should parse every SATC table and all devices in the tables
reported by the BIOS and keep the information in kernel list for further
SATC policy deployment.
Signed-off-by: Yian Chen
---
drivers/iommu/intel/dmar.c | 9
drivers/iommu/intel/iommu.c | 89
From: Yian Chen
Starting from Intel Platform VT-d v3.2, BIOS may provide new remapping
structure SATC for SOC integrated devices, according to section 8.8 of
Intel VT-d architecture specification v3.2. The SATC structure reports
a list of the devices that require SATC enabling via ATS capacity.
Intel platform VT-d (v3.2) comes with a new type of DMAR subtable
SATC. The SATC table includes a list of SoC integrated devices
that require SATC. OS software can use this table to enable ATS
only for the devices in the list.
Yian Chen (3):
iommu/vt-d: Add new enum value and structure for SATC
ndy Dunlap
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/Makefile | 2 +-
drivers/iommu/intel/iommu.c| 1 -
include/trace/events/intel_iommu.h | 2 --
3 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/iommu/intel/Makefile b/drivers/iommu/intel/Makefile
index fb
ched TLB flushes when caching-mode is on, as the performance
benefit from using batched TLB invalidations is likely to be much
smaller than the overhead of the virtual-to-physical IOMMU page-tables
synchronization.
Fixes: 13cf01744608 ("iommu/vt-d: Make use of iova deferred flushing")
Signed-o
Isn't it
Fixes: 13cf01744608 ("iommu/vt-d: Make use of iova deferred flushing")
?
Best regards,
baolu
Signed-off-by: Nadav Amit
Cc: David Woodhouse
Cc: Lu Baolu
Cc: Joerg Roedel
Cc: Will Deacon
Cc: sta...@vger.kernel.org >
---
v1->v2:
* disable flush queue for all domai
On 1/27/21 8:26 AM, Lu Baolu wrote:
+{
+ struct dmar_domain *dmar_domain = to_dmar_domain(domain);
+ struct intel_iommu *iommu = domain_get_iommu(dmar_domain);
+
+ if (intel_iommu_strict)
+ return 0;
+
+ /*
+ * The flush queue implementation does not perform page-selective
flushes with caching mode.")
Signed-off-by: Nadav Amit
Cc: David Woodhouse
Cc: Lu Baolu
Cc: Joerg Roedel
Cc: Will Deacon
Cc: sta...@vger.kernel.org
---
drivers/iommu/intel/iommu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/driver
/mwhpr11mb18862d2ea5bd432bf22d99a48c...@mwhpr11mb1886.namprd11.prod.outlook.com/
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/svm.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c
index 033b25886e57..d7c98c5fa4e7 100644
.
Let's use RESPONSE_INVALID instead for now, so that the device state
machine doesn't enter HALT state.
Suggested-by: Ashok Raj
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/svm.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel
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