Hello Steven,
On Mon, 15 Apr 2024 04:44:30 -0400
Steven Rostedt wrote:
> On Mon, 18 Mar 2024 16:43:07 +0100
> Luca Ceresoli wrote:
>
> > However the arrows are still reversed.
>
> This requires a kernel change. The problem is that the print fmt has:
>
> print fm
Hello Steven,
On Fri, 15 Mar 2024 14:58:52 -0400
Steven Rostedt wrote:
> On Fri, 15 Mar 2024 19:03:12 +0100
> Luca Ceresoli wrote:
>
> > > >
> > > > I've come across an unexpected behaviour in the kernel tracing
> > > > infrastructure that looks
Hello Steven,
thanks for the quick feedback!
On Fri, 15 Mar 2024 13:21:46 -0400
Steven Rostedt wrote:
> On Fri, 15 Mar 2024 17:49:00 +0100
> Luca Ceresoli wrote:
>
> > Hello Linux tracing maintainers,
>
> Hi Luca!
>
> >
> > I've come across an unexpe
ws are still wrong with trace-cmd.
I have no idea how to further debug this and after a quick look at the
macros I can honestly say I'm not feeling brave enough to dig into them
in a late Friday afternoon.
Any hints?
Am I doing anything wrong?
Is %c supposed to work in tracing macros?
Best regards,
Luca
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
/u8:4-215 [000] 1436.383503: snd_soc_bias_level_start:
card=vscn-2046 component=ff56.codec val=3
kworker/u8:4-215 [000] 1436.383513: snd_soc_bias_level_done:
card=vscn-2046 component=ff56.codec val=3
Signed-off-by: Luca Ceresoli
---
include/trace/events/asoc.h | 29
: snd_soc_dapm_done:card=vscn-2046
event=1
aplay-214 [000] 694.537349: snd_soc_dapm_start: card=vscn-2046
event=2
aplay-214 [000] 694.563241: snd_soc_dapm_done:card=vscn-2046
event=2
Signed-off-by: Luca Ceresoli
---
include/trace/events/asoc.h | 16
This small series adds parameters to existing DAPM trace events to make
them more informative.
Signed-off-by: Luca Ceresoli
---
Luca Ceresoli (2):
ASoC: trace: add component to set_bias_level trace events
ASoC: trace: add event to snd_soc_dapm trace events
include/trace/events
ll clock outputs when enabling
a FOD.
See "VersaClock ® 6E Family Register Descriptions and Programming Guide"
(August 30, 2018), Table 116 "Power Up VDD check", page 58:
https://www.renesas.com/us/en/document/mau/versaclock-6e-family-register-descriptions-and-programming-guide
On 16/03/21 20:48, Rob Herring wrote:
> Properties with standard unit suffixes already have a type and don't need
> type references. Fix a few more cases which have gotten added.
>
> Cc: Luca Ceresoli
> Cc: Jonathan Cameron
> Cc: Dmitry Torokhov
> Cc: Bjorn Andersson
Optionally handle the NRST pin (active low reset) in order to start from a
known state during boot and to shut down the chip when rebooting.
Signed-off-by: Luca Ceresoli
---
drivers/mfd/lp87565.c | 27 +++
include/linux/mfd/lp87565.h | 1 +
2 files changed, 28
Document the LP8756x-Q1 and LP87524-Q1 ICs reset pin.
Signed-off-by: Luca Ceresoli
---
Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml | 4
Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml | 4
Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml | 4
3 files
This enum is used only internally to the regulator driver for buck indexes.
Signed-off-by: Luca Ceresoli
---
drivers/regulator/lp87565-regulator.c | 11 +++
include/linux/mfd/lp87565.h | 11 ---
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers
"GOIO" should be "GPIO" here.
Signed-off-by: Luca Ceresoli
---
drivers/gpio/gpio-lp87565.c | 6 +++---
include/linux/mfd/lp87565.h | 28 ++--
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpio/gpio-lp87565.c b/drivers/gpio/
This define appears incorrect, but it is completely unused so it can be
removed.
Signed-off-by: Luca Ceresoli
---
include/linux/mfd/lp87565.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/linux/mfd/lp87565.h b/include/linux/mfd/lp87565.h
index 2620554f357a..a8799ae50dcf 100644
This line is part of the code snippet, so it has to be nested in order
to be rendered correctly.
Signed-off-by: Luca Ceresoli
---
Documentation/iio/iio_configfs.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/iio/iio_configfs.rst
b/Documentation/iio
This 2nd-level bullet list is not properly ReST-formatted and thus it gets
rendered as a unique paragraph quite unreadable. Fix by adding spaces as
needed.
While there also swap "shift" and "repeat" so they are in the correct
order.
Signed-off-by: Luca Ceresoli
---
Docu
Here are a few minor fixes and improvements to the IIO documentation.
Luca Ceresoli (5):
docs: iio: fix example formatting
docs: iio: fix directory naming
docs: iio: document the 'index' attribute too
docs: iio: fix bullet list formatting
docs: iio: mark "repeat" sysfs
Two out of three attributes are documented, document the third one too.
Signed-off-by: Luca Ceresoli
---
Documentation/driver-api/iio/buffers.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/driver-api/iio/buffers.rst
b/Documentation/driver-api/iio/buffers.rst
index
Show that this field is optional, just like the shift value.
Signed-off-by: Luca Ceresoli
---
Documentation/driver-api/iio/buffers.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/driver-api/iio/buffers.rst
b/Documentation/driver-api/iio/buffers.rst
index
This directory is a, well, directory, not a file.
Signed-off-by: Luca Ceresoli
---
Documentation/driver-api/iio/buffers.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/driver-api/iio/buffers.rst
b/Documentation/driver-api/iio/buffers.rst
index 3ddebddc02ca
-off-by: Adam Ford
Reviewed-by: Luca Ceresoli
--
Luca
by using the dev_err_probe() helper function.
Signed-off-by: Luca Ceresoli
Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during
write_init")
Fixes: 061c97d13f1a ("fpga manager: Add Xilinx slave serial SPI driver")
---
drivers/fpga/xilinx-spi.c | 24 +---
Hi,
On 21/01/21 04:21, Chunyou Tang wrote:
> On Wed, 20 Jan 2021 19:09:05 -0800
> Joe Perches wrote:
>
>> On Wed, 2021-01-20 at 19:02 -0800, Randy Dunlap wrote:
>>> On 1/20/21 6:07 PM, ChunyouTang wrote:
From: tangchunyou
Increase direcly,maping,manger spelling error check
Hi Adam,
On 19/01/21 22:21, Adam Ford wrote:
> There are two registers which can set the load capacitance for
> XTAL1 and XTAL2. These are optional registers when using an
> external crystal. Since XTAL1 and XTAL2 will set to the same value,
> update the binding to support a single property
Hi Adam,
On 19/01/21 22:21, Adam Ford wrote:
> There are two registers which can set the load capacitance for
> XTAL1 and XTAL2. These are optional registers when using an
> external crystal. Parse the device tree and set the
> corresponding registers accordingly.
>
> Signed-off-by: Adam Ford
Hi Adam,
On 09/01/21 03:48, Adam Ford wrote:
> On Fri, Jan 8, 2021 at 4:49 PM Luca Ceresoli wrote:
>>
>> Hi Adam,
>>
>> On 06/01/21 18:38, Adam Ford wrote:
>>> There are two registers which can set the load capacitance for
>>> XTAL1 and X
Hi Adam,
On 13/01/21 13:31, Adam Ford wrote:
> On Tue, Jan 12, 2021 at 9:16 PM Rob Herring wrote:
>>
>> On Wed, Jan 06, 2021 at 11:38:59AM -0600, Adam Ford wrote:
>>> There are two registers which can set the load capacitance for
>>> XTAL1 and XTAL2. These are optional registers when using an
Hi Adam,
On 12/01/21 18:00, Adam Ford wrote:
> On Tue, Jan 12, 2021 at 10:45 AM Luca Ceresoli wrote:
>>
>> Hi Adam,
>>
>> On 11/01/21 17:40, Adam Ford wrote:
>>> On Sat, Jan 9, 2021 at 12:02 PM Luca Ceresoli wrote:
>>>>
>>>> Hi Adam
Hi Adam,
On 11/01/21 17:40, Adam Ford wrote:
> On Sat, Jan 9, 2021 at 12:02 PM Luca Ceresoli wrote:
>>
>> Hi Adam,
>>
>> On 09/01/21 04:00, Adam Ford wrote:
>>> On Fri, Jan 8, 2021 at 4:49 PM Luca Ceresoli wrote:
>>>>
>>&g
Hi Adam,
On 09/01/21 04:00, Adam Ford wrote:
> On Fri, Jan 8, 2021 at 4:49 PM Luca Ceresoli wrote:
>>
>> Hi Adam,
>>
>> On 06/01/21 18:39, Adam Ford wrote:
>>> There are two registers which can set the load capacitance for
>>> XTAL1 and X
Hi Adam,
On 06/01/21 18:39, Adam Ford wrote:
> There are two registers which can set the load capacitance for
> XTAL1 and XTAL2. These are optional registers when using an
> external crystal. Parse the device tree and set the
> corresponding registers accordingly.
No need to repeat the first 2
Hi Adam,
On 06/01/21 18:38, Adam Ford wrote:
> There are two registers which can set the load capacitance for
> XTAL1 and XTAL2. These are optional registers when using an
> external crystal. Update the bindings to support them.
>
> Signed-off-by: Adam Ford
> ---
>
_output,
> {
> u32 value;
>
> - if (!of_property_read_u32(np_output,
> - "idt,voltage-microvolts", )) {
> + if (!of_property_read_u32(np_output, "idt,voltage-microvolt",
> + )) {
Reviewed-
On 22/09/20 10:47, Sakari Ailus wrote:
> Hi Luca,
>
> On Tue, Sep 22, 2020 at 10:09:33AM +0200, Luca Ceresoli wrote:
>> Hi,
>>
>> On 21/09/20 23:39, Sowjanya Komatineni wrote:
>>> Sensor should already be in standby during remove and there is no
>>>
Hi Sakari,
On 23/09/20 13:08, Sakari Ailus wrote:
> Hi Luca,
>
> On Mon, Sep 14, 2020 at 06:49:29PM +0200, Luca Ceresoli wrote:
>> Hi Sakari,
>>
>> On 14/09/20 11:47, Sakari Ailus wrote:
>>> Hi Luca,
>>>
>>> On Mon, Sep 14, 2020 at
Hi,
On 21/09/20 23:39, Sowjanya Komatineni wrote:
> Sensor should already be in standby during remove and there is no
> need to configure sensor registers for stream stop.
I beg your pardon for the newbie question: does the V4L2 framework
guarantee that the stream is stopped (.s_stream(..., 0))
Fix "will to" -> "will do".
Reviewed-by: Jacopo Mondi
Signed-off-by: Luca Ceresoli
---
Changes in v2: none
---
Documentation/driver-api/media/v4l2-subdev.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/driver-api/media/v4l2-subd
Fix "Helper functions exists" -> "Helper functions exist".
Signed-off-by: Luca Ceresoli
---
This patch is new in v2
---
Documentation/driver-api/media/v4l2-subdev.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/driver-api/m
ew section as it has an introductory content.
Suggested-by: Jacopo Mondi
Signed-off-by: Luca Ceresoli
---
Changes in v2:
- replaces the simpler patch 3/3 upon suggestion by Jacopo
---
.../driver-api/media/v4l2-subdev.rst | 88 ++-
1 file changed, 46 insertions(+), 42 deletion
Hi Jacopo,
On 15/09/20 15:45, Jacopo Mondi wrote:
> Hi Luca,
>
> On Fri, Sep 04, 2020 at 11:51:40PM +0200, Luca Ceresoli wrote:
>> The subdev registration topic is pretty lengthy, and takes more than
>> half of the "V4L2 sub-devices" section. Help readers
hs, but since
adding a subsubsection would be overkill, just emphasize them in bold.
Reviewed-by: Jacopo Mondi
Signed-off-by: Luca Ceresoli
---
Changes in v2: none
---
Documentation/driver-api/media/v4l2-subdev.rst | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/
Hi Jacopo,
thanks for reviewing.
On 15/09/20 15:34, Jacopo Mondi wrote:
> Hi Luca,
>
> On Fri, Sep 04, 2020 at 11:51:41PM +0200, Luca Ceresoli wrote:
>> This paragraph provides generic information to explain what v4l2_subdev is
>> useful for. Placing it in the middle of
onger preserved
> when doing subsampling in this mode.
>
> Signed-off-by: Eugen Hristev
Reviewed-by: Luca Ceresoli
--
Luca
Hi,
On 15/09/20 11:04, Eugen Hristev wrote:
> Binning enum is unused. Remove from driver.
>
> Suggested-by: Sakari Ailus
> Signed-off-by: Eugen Hristev
Reviewed-by: Luca Ceresoli
--
Luca
Hi Sakari,
On 14/09/20 11:47, Sakari Ailus wrote:
> Hi Luca,
>
> On Mon, Sep 14, 2020 at 09:58:24AM +0200, Luca Ceresoli wrote:
>> Hi Sakari,
>>
>> On 11/09/20 15:01, Sakari Ailus wrote:
>>> Hi Luca,
>>>
>>> On Fri, Sep 11, 2020 at
Hi Sakari,
On 11/09/20 15:01, Sakari Ailus wrote:
> Hi Luca,
>
> On Fri, Sep 11, 2020 at 02:49:26PM +0200, Luca Ceresoli wrote:
>> Hi Sakari,
>>
>> On 03/09/20 10:15, Sakari Ailus wrote:
>>>
>>> Hi all,
>>>
>>> These patches enabl
Hi,
On 11/09/20 23:44, Sakari Ailus wrote:
> Hi Eugen,
>
> Thanks for the patch.
>
> On Wed, Sep 09, 2020 at 01:53:28PM +0300, Eugen Hristev wrote:
>> Add support for the mode 6 for the sensor, this mode uses
>> 3/8 subsampling and 3 horizontal binning.
>> Aspect ratio is changed.
>> Split the
Hi Sakari,
On 03/09/20 10:15, Sakari Ailus wrote:
>
> Hi all,
>
> These patches enable calling (and finishing) a driver's probe function
> without powering on the respective device on busses where the practice is
> to power on the device for probe. While it generally is a driver's job to
>
hs, but since
adding a subsubsection would be overkill, just emphasize them in bold.
Signed-off-by: Luca Ceresoli
---
Documentation/driver-api/media/v4l2-subdev.rst | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/Documentation/driver-api/media/v4l2-subdev.rst
b/Docu
and
before going into its details.
Signed-off-by: Luca Ceresoli
---
Documentation/driver-api/media/v4l2-subdev.rst | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/driver-api/media/v4l2-subdev.rst
b/Documentation/driver-api/media/v4l2-subdev.rst
index
Fix "will to" -> "will do".
Signed-off-by: Luca Ceresoli
---
Documentation/driver-api/media/v4l2-subdev.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/driver-api/media/v4l2-subdev.rst
b/Documentation/driver-api/media/v4l2-subdev
Add the LP87524-Q1 to the bindings along with an example. This is a variant
of the LP87565-Q1 and LP87561-Q1 chips which already have bindings.
Signed-off-by: Luca Ceresoli
---
Changes in v5:
- describe the "regulators" node too (Rob)
- add 'additionalProperties: false' (Ro
emove "MFD driver" from the title as it is implementation specific
- replace "PMIC" with "buck converter" in title as it is more informative
Signed-off-by: Luca Ceresoli
---
Changes in v5:
- describe the "regulators" node too (Rob)
- add 'additionalPrope
Add support for the LP87524B/J/P-Q1 Four 4-MHz Buck Converter. This is a
variant of the LP87565 having 4 single-phase outputs and up to 10 A of
total output current.
Signed-off-by: Luca Ceresoli
Acked-for-MFD-by: Lee Jones
---
Changes in v5: none
Changes in v4: none
Changes in v3: none
l.org/lkml/2020/6/3/908
v2: https://lkml.org/lkml/2020/6/17/492
v3: https://lkml.org/lkml/2020/6/22/1139
v4: https://lkml.org/lkml/2020/8/17/830
Luca
Luca Ceresoli (3):
dt-bindings: mfd: lp87565: convert to yaml
dt-bindings: mfd: add LP87524-Q1
mfd: lp87565: add LP87524-Q1 variant
.../
Hi again...
On 02/09/20 08:46, Luca Ceresoli wrote:
> Hi Sowjanya,
>
> On 02/09/20 04:04, Sowjanya Komatineni wrote:
>> This patch adds IMX274 optional external clock input and voltage
>> supplies to device tree bindings.
>>
>> Reviewed-by: Luca Ceresoli
>
Hi Sowjanya,
On 02/09/20 04:04, Sowjanya Komatineni wrote:
> This patch adds IMX274 optional external clock input and voltage
> supplies to device tree bindings.
>
> Reviewed-by: Luca Ceresoli
> Signed-off-by: Sowjanya Komatineni
> ---
> .../devicetree/bindings/media
is required by the hardware.
Reported-by: Tom Rix
Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
---
Changes in v4:
- add Reviewed-by Tom Rix
- fix uninitialized variable
(Reported-by: kernel test robot )
Changes in v3:
- completely rewrite the loop after Tom pointed out the 'sleep
Most dev_err messages in this file have no final dot. Remove the only two
exceptions to make them consistent.
Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
---
Changes in v4:
- add Reviewed-by Tom Rix
Changes in v3: none.
Changes in v2:
- move before the "provide better diagno
Current code calls gpiod_get_value() without error checking. Should the
GPIO controller fail, execution would continue without any error message.
Fix by checking for negative error values.
Reported-by: Tom Rix
Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
---
Changes in v4:
- add
Remove comment committed by mistake.
Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during
write_init")
Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
---
Changes in v4:
- add Reviewed-by Tom Rix
Changes in v3: none.
Changes in v2: none.
---
drivers/fpga/xi
When the DONE pin does not go high after programming to confirm programming
success, the INIT_B pin provides some info on the reason. Use it if
available to provide a more explanatory error message.
Reviewed-by: Tom Rix
Signed-off-by: Luca Ceresoli
---
Changes in v4:
- add Reviewed-by Tom
ng git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Luca-Ceresoli/fpga-manager-xilinx-spi-remo
Current code calls gpiod_get_value() without error checking. Should the
GPIO controller fail, execution would continue without any error message.
Fix by checking for negative error values.
Reported-by: Tom Rix
Signed-off-by: Luca Ceresoli
---
Changes in v3:
- rebase on previous patches
Most dev_err messages in this file have no final dot. Remove the only two
exceptions to make them consistent.
Signed-off-by: Luca Ceresoli
---
Changes in v3: none.
Changes in v2:
- move before the "provide better diagnostics on programming failure"
patch for clarity
---
dr
Remove comment committed by mistake.
Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during
write_init")
Signed-off-by: Luca Ceresoli
---
Changes in v3: none.
Changes in v2: none.
---
drivers/fpga/xilinx-spi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/dr
is required by the hardware.
Reported-by: Tom Rix
Signed-off-by: Luca Ceresoli
---
Changes in v3:
- completely rewrite the loop after Tom pointed out the 'sleep' bug
This patch is new in v2
---
drivers/fpga/xilinx-spi.c | 23 +++
1 file changed, 15 insertions(+), 8
When the DONE pin does not go high after programming to confirm programming
success, the INIT_B pin provides some info on the reason. Use it if
available to provide a more explanatory error message.
Signed-off-by: Luca Ceresoli
---
Changes in v3: none.
Changes in v2:
- also check
Hi Tom,
On 27/08/20 21:34, Tom Rix wrote:
>
> On 8/27/20 12:26 PM, Luca Ceresoli wrote:
>> Hi Tom,
>>
>> thanks for the prompt feedback!
>>
>> On 27/08/20 20:59, Tom Rix wrote:
>>> On 8/27/20 7:32 AM, Luca Ceresoli wrote:
>>>> In prepar
Hi Tom,
thanks for the prompt feedback!
On 27/08/20 20:59, Tom Rix wrote:
>
> On 8/27/20 7:32 AM, Luca Ceresoli wrote:
>> In preparation to add error checking for gpiod_get_value(), rework
>> the loop to avoid the duplication of these lines:
>>
>>
Most dev_err messages in this file have no final dot. Remove the only two
exceptions to make them consistent.
Signed-off-by: Luca Ceresoli
---
Changes in v2:
- move before the "provide better diagnostics on programming failure"
patch for clarity
---
drivers/fpga/xilinx-spi.c |
Remove comment committed by mistake.
Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during
write_init")
Signed-off-by: Luca Ceresoli
---
Changes in v2: none.
Note: Moritz replied "Applied to for-next", but it doesn't show up yet.
---
drivers/fpga/xilinx
ror checking will expand these two lines to five, making code
duplication more annoying.
Signed-off-by: Luca Ceresoli
---
This patch is new in v2
---
drivers/fpga/xilinx-spi.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/fpga/xilinx-spi.c b/drivers/f
Current code calls gpiod_get_value() without error checking. Should the
GPIO controller fail, execution would continue without any error message.
Fix by checking for negative error values.
Reported-by: Tom Rix
Signed-off-by: Luca Ceresoli
---
This patch is new in v2
---
drivers/fpga/xilinx
When the DONE pin does not go high after programming to confirm programming
success, the INIT_B pin provides some info on the reason. Use it if
available to provide a more explanatory error message.
Signed-off-by: Luca Ceresoli
---
Changes in v2:
- also check for gpiod_get_value() errors (Tom
Hi Tom,
On 19/08/20 18:32, Luca Ceresoli wrote:
> On 18/08/20 16:21, Tom Rix wrote:
>>
>> On 8/18/20 3:20 AM, Luca Ceresoli wrote:
>>> [a question for GPIO maintainers below]
>>>
>>> Hi Tom,
>>>
>>> thanks for your review!
>>
Hi Moritz,
On 20/08/20 06:11, Moritz Fischer wrote:
> On Mon, Aug 17, 2020 at 06:59:09PM +0200, Luca Ceresoli wrote:
>> Remove comment committed by mistake.
>>
>> Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during
>> write_init&q
On 18/08/20 16:21, Tom Rix wrote:
>
> On 8/18/20 3:20 AM, Luca Ceresoli wrote:
>> [a question for GPIO maintainers below]
>>
>> Hi Tom,
>>
>> thanks for your review!
>>
>> On 17/08/20 20:15, Tom Rix wrote:
>>> The other two patches
[a question for GPIO maintainers below]
Hi Tom,
thanks for your review!
On 17/08/20 20:15, Tom Rix wrote:
> The other two patches are fine.
>
> On 8/17/20 9:59 AM, Luca Ceresoli wrote:
>> When the DONE pin does not go high after programming to confirm programming
>> su
Remove comment committed by mistake.
Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during
write_init")
Signed-off-by: Luca Ceresoli
---
drivers/fpga/xilinx-spi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-s
Most dev_err messages in this file have no final dot. Remove the only two
exceptions to make them consistent.
Signed-off-by: Luca Ceresoli
---
drivers/fpga/xilinx-spi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c
When the DONE pin does not go high after programming to confirm programming
success, the INIT_B pin provides some info on the reason. Use it if
available to provide a more explanatory error message.
Signed-off-by: Luca Ceresoli
---
drivers/fpga/xilinx-spi.c | 11 ++-
1 file changed, 10
/lkml/2020/6/3/908
v2: https://lkml.org/lkml/2020/6/17/492
v3: https://lkml.org/lkml/2020/6/22/1139
Luca
Luca Ceresoli (3):
dt-bindings: mfd: lp87565: convert to yaml
dt-bindings: mfd: add LP87524-Q1
mfd: lp87565: add LP87524-Q1 variant
.../devicetree/bindings/mfd/lp87565.txt | 79
- remove "MFD driver" from the title as it is implementation specific
- replace "PMIC" with "buck converter" in title as it is more informative
Signed-off-by: Luca Ceresoli
---
Changes in v4:
- split in two different bindings (Rob)
- remove "MFD driver
Add support for the LP87524B/J/P-Q1 Four 4-MHz Buck Converter. This is a
variant of the LP87565 having 4 single-phase outputs and up to 10 A of
total output current.
Signed-off-by: Luca Ceresoli
Acked-for-MFD-by: Lee Jones
---
Changes in v4: none
Changes in v3: none
Changes in v2
Add the LP87524-Q1 to the bindings along with an example. This is a variant
of the LP87565-Q1 and LP87561-Q1 chips which already have bindings.
Signed-off-by: Luca Ceresoli
---
Changes in v4:
- reformat as a standalone file
Changes in v3:
- fix yaml errors
Changes in v2:
- RFC,v1
Hi,
On 14/08/20 16:51, Rob Herring wrote:
> On Thu, Aug 13, 2020 at 4:31 AM Luca Ceresoli wrote:
>>
>> Hi Rob,
>>
>> On 12/08/20 22:36, Rob Herring wrote:
>>> Clean-up incorrect indentation, extra spaces, long lines, and missing
>>> EOF newline in sch
uring probes.
>
> Signed-off-by: Stephen Kitt
Reviewed-by: Luca Ceresoli
--
Luca
uring probes.
>
> Signed-off-by: Stephen Kitt
Reviewed-by: Luca Ceresoli
--
Luca
uring probes.
>
> Signed-off-by: Stephen Kitt
Reviewed-by: Luca Ceresoli
--
Luca
Hi Rob,
On 12/08/20 22:36, Rob Herring wrote:
> Clean-up incorrect indentation, extra spaces, long lines, and missing
> EOF newline in schema files. Most of the clean-ups are for list
> indentation which should always be 2 spaces more than the preceding
> keyword.
>
> Found with yamllint (which
Hi,
On 23/07/20 03:49, Stephen Boyd wrote:
> Quoting Luca Ceresoli (2020-07-21 09:46:52)
>> 'idt' is misspelled 'itd' in a few places, fix it.
>>
>> Fixes: 34662f6e3084 ("dt: Add additional option bindings for IDT VersaClock")
>> Signed-off-by: Luca
Marek has been the primary developer of this driver (thanks!). Now as
he is not working on it anymore he suggested I take over maintainership.
Cc: Marek Vasut
Signed-off-by: Luca Ceresoli
---
Changes in v4: none.
Changes in v3: none
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1
Convert to yaml the VersaClock bindings document. The mapping between
clock specifier and physical pins cannot be described formally in yaml
schema, then keep it verbatim in the description field.
Signed-off-by: Luca Ceresoli
---
Changes in v4: none.
Changes in v3:
- schema syntax fixes: use
://lkml.org/lkml/2020/7/21/939
[1] https://lkml.org/lkml/2020/7/23/128
Luca Ceresoli (3):
dt-bindings: clk: versaclock5: fix 'idt' prefix typos
MAINTAINERS: take over IDT VersaClock 5 clock driver
dt-bindings: clk: versaclock5: convert to yaml
.../bindings/clock/idt,versaclock5.txt
'idt' is misspelled 'itd' in a few places, fix it.
Fixes: 34662f6e3084 ("dt: Add additional option bindings for IDT VersaClock")
Signed-off-by: Luca Ceresoli
Reviewed-by: Rob Herring
---
Changes in v4: none.
Changes in v3: add Reviewed-by: Rob Herring
---
Documentation/devicetre
for the output drivers.
Use a dedicated struct for the output drivers so that each block uses
exactly the fields it needs, not more.
Signed-off-by: Luca Ceresoli
---
Changes in v4:
- slightly rephrase commit message
- but split this patch from the original series
(https://lkml.org/lkml/2020/7/21
Convert to yaml the VersaClock bindings document. The mapping between
clock specifier and physical pins cannot be described formally in yaml
schema, then keep it verbatim in the description field.
Signed-off-by: Luca Ceresoli
---
Changes in v3:
- schema syntax fixes: use enum to constrain reg
Marek has been the primary developer of this driver (thanks!). Now as
he is not working on it anymore he suggested I take over maintainership.
Cc: Marek Vasut
Signed-off-by: Luca Ceresoli
---
Changes in v3: none
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
'idt' is misspelled 'itd' in a few places, fix it.
Fixes: 34662f6e3084 ("dt: Add additional option bindings for IDT VersaClock")
Signed-off-by: Luca Ceresoli
Reviewed-by: Rob Herring
---
Changes in v3: add Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/clock/idt,v
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