IBM pseries platform nmem* device
performance stats using this interface.
Result from power9 pseries lpar with 2 nvdimm device:
Patchset looks fine to me.
Reviewed-by: Madhavan Srinivasan
Ex: List all event by perf list
command:# perf list nmem
nmem0/cache_rh_cnt
On 3/25/21 6:36 PM, Arnaldo Carvalho de Melo wrote:
Em Wed, Mar 24, 2021 at 10:05:23AM +0530, Madhavan Srinivasan escreveu:
On 3/22/21 8:27 PM, Athira Rajeev wrote:
Performance Monitoring Unit (PMU) registers in powerpc provides
information on cycles elapsed between different stages
structure.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/core-book3s.c | 4 ++--
arch/powerpc/perf/isa207-common.c| 29
On 11/24/20 10:21 AM, Namhyung Kim wrote:
Hello,
On Mon, Nov 23, 2020 at 8:00 PM Michael Ellerman wrote:
Namhyung Kim writes:
Hi Peter and Kan,
(Adding PPC folks)
On Tue, Nov 17, 2020 at 2:01 PM Namhyung Kim wrote:
Hello,
On Thu, Nov 12, 2020 at 4:54 AM Liang, Kan wrote:
On
On 6/10/20 8:37 PM, Oleg Nesterov wrote:
Hi,
looks like this patch was forgotten.
yep, I missed this. But mpe did have comments for the patch.
https://lkml.org/lkml/2019/9/19/107
Maddy
Do you think this should be fixed or should we document that
PTRACE_GETREGS is not consistent with
to the kernel to capture the extended registers
in each sample. Hence decide the mask value based on the processor
version.
Signed-off-by: Anju T Sudhakar
[Decide extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
tools/arch/powerpc/include
except for couple minor nits (extra tabs and newline
issue).
Reviewed-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/perf_event_server.h | 8 +++
arch/powerpc/include/uapi/asm/perf_regs.h| 14 +++-
arch/powerpc/perf/core-book3s.c | 1 +
arch/powerpc/perf
On 5/19/20 11:45 AM, Athira Rajeev wrote:
From: Anju T Sudhakar
Add support for perf extended register capability in powerpc.
The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the
PMU which support extended registers. The generic code define the mask
of extended registers
On 4/29/20 11:34 AM, Anju T Sudhakar wrote:
The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the
PMU which support extended registers. The generic code define the mask
of extended registers as 0 for non supported architectures.
Add support for extended registers in POWER9
ips values.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Kajol Jain
---
arch/powerpc/platforms/pseries/mobility.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/mobility.c
b/arch/powerpc/platforms/pseries/mobili
On 3/27/20 12:06 PM, Kajol Jain wrote:
To expose the system dependent parameter like total number of
sockets and numbers of chips per socket, patch adds two sysfs files.
"sockets" and "chips" are added to /sys/devices/hv_24x7/interface/
of the "hv_24x7" pmu.
Signed-off-by: Kajol Jain
---
69997 22
hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
Signed-off-by: Kajol Jain
Suggested-by: Sukadev Bhattiprolu
Tested-by: Madhavan Srinivasan
---
arch/powerpc/perf/hv-24x7.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/
values like number of sockets and chips per socket.
Rtas_call with token "PROCESSOR_MODULE_INFO"
is used to get these values.
Patch looks good to me.
Reviewed-by: Madhavan Srinivasan
Sub-sequent patch exports these values via sysfs.
Patch also make these parameters default to 1.
called by any path other than
power_pmu_add(), ppmu->config_bhrb(-1) will set mmcra to -1.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Ravi Bangoria
---
arch/powerpc/perf/core-book3s.c | 6 --
arch/powerpc/perf/power8-pmu.c | 3 +++
arch/powerpc/perf/power9-pmu.c | 3 +++
On 14/12/18 2:41 PM, Anju T Sudhakar wrote:
Add PMU functions to support trace-imc.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Anju T Sudhakar
---
arch/powerpc/perf/imc-pmu.c | 175
1 file changed, 175 insertions(+)
diff --git a/arch/powerpc
On 14/12/18 2:41 PM, Anju T Sudhakar wrote:
Patch detects trace-imc events, does memory initilizations for each online
cpu, and registers cpuhotplug call-backs.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Anju T Sudhakar
---
arch/powerpc/perf/imc-pmu.c | 91
, the mode bit of ldbar should be set to 'trace'. So to
accommodate trace-mode of IMC, reposition setting of ldbar for thread-imc
to thread_imc_event_add(). Also reset ldbar at thread_imc_event_del().
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Anju T Sudhakar
opal-calls for IMC.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Anju T Sudhakar
---
arch/powerpc/include/asm/imc-pmu.h | 39 +
arch/powerpc/include/asm/opal-api.h | 1 +
2 files changed, 40 insertions(+)
diff --git a/arch/powerpc/include/asm/imc-pmu
for exclusion
flags.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Andrew Murray
---
arch/powerpc/perf/hv-24x7.c | 10 +-
arch/powerpc/perf/hv-gpci.c | 10 +-
arch/powerpc/perf/imc-pmu.c | 19 +--
3 files changed, 3 insertions(+), 36 deletions(-)
diff
belongs to 'perf_hw_context' in
collect_events().
Reviewed-By: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
Signed-off-by: Ravi Bangoria <ravi.bango...@linux.vnet.ibm.com>
---
arch/powerpc/perf/core-book3s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/
belongs to 'perf_hw_context' in
collect_events().
Reviewed-By: Madhavan Srinivasan
Signed-off-by: Ravi Bangoria
---
arch/powerpc/perf/core-book3s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index
On Friday 10 November 2017 02:32 AM, Michael Ellerman wrote:
Anju T Sudhakar writes:
IMC_MAX_PMU is used for static storage (per_nest_pmu_arr) which holds
nest pmu information. Current value for the macro is 32 based on
the initial number of nest pmu units supported
On Friday 10 November 2017 02:32 AM, Michael Ellerman wrote:
Anju T Sudhakar writes:
IMC_MAX_PMU is used for static storage (per_nest_pmu_arr) which holds
nest pmu information. Current value for the macro is 32 based on
the initial number of nest pmu units supported by the nest microcode.
On Friday 03 November 2017 05:49 AM, Michael Ellerman wrote:
Madhavan Srinivasan <ma...@linux.vnet.ibm.com> writes:
On Wednesday 01 November 2017 06:22 AM, Michael Ellerman wrote:
Anju T Sudhakar <a...@linux.vnet.ibm.com> writes:
Call trace observed during boot:
What's the
On Friday 03 November 2017 05:49 AM, Michael Ellerman wrote:
Madhavan Srinivasan writes:
On Wednesday 01 November 2017 06:22 AM, Michael Ellerman wrote:
Anju T Sudhakar writes:
Call trace observed during boot:
What's the actual oops?
I could recreate this in mambo with CPUS=2
On Wednesday 01 November 2017 06:22 AM, Michael Ellerman wrote:
Anju T Sudhakar writes:
Call trace observed during boot:
What's the actual oops?
I could recreate this in mambo with CPUS=2 and THREAD=2
Here is the complete stack trace.
[ 0.045367] core_imc
On Wednesday 01 November 2017 06:22 AM, Michael Ellerman wrote:
Anju T Sudhakar writes:
Call trace observed during boot:
What's the actual oops?
I could recreate this in mambo with CPUS=2 and THREAD=2
Here is the complete stack trace.
[ 0.045367] core_imc memory allocation for cpu 2
On Thursday 12 October 2017 01:21 PM, Stewart Smith wrote:
Anju T Sudhakar writes:
On Wednesday 11 October 2017 01:55 AM, Stewart Smith wrote:
Michael Ellerman writes:
Anju T Sudhakar writes:
Add a kernel command
On Thursday 12 October 2017 01:21 PM, Stewart Smith wrote:
Anju T Sudhakar writes:
On Wednesday 11 October 2017 01:55 AM, Stewart Smith wrote:
Michael Ellerman writes:
Anju T Sudhakar writes:
Add a kernel command line parameter option to disable In-Memory Collection
(IMC) counters and
fix is.
mpe,
We have just re-factored the code to handle the memory freeing and fixed
a leak.
This is minimal fix. And there are no risks in taking this in.
Reviewed-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
Maddy
cheers
.
This is minimal fix. And there are no risks in taking this in.
Reviewed-by: Madhavan Srinivasan
Maddy
cheers
On Tuesday 19 September 2017 03:30 PM, Michael Ellerman wrote:
Ravi Bangoria writes:
Kernel crashes if power pmu is not registered and user tries to dump
regs with 'echo p > /proc/sysrq-trigger'. Sample log:
Unable to handle kernel paging request for
On Tuesday 19 September 2017 03:30 PM, Michael Ellerman wrote:
Ravi Bangoria writes:
Kernel crashes if power pmu is not registered and user tries to dump
regs with 'echo p > /proc/sysrq-trigger'. Sample log:
Unable to handle kernel paging request for data at address 0x0008
o root or
privileged user.
Tested-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
Signed-off-by: Kan Liang <kan.li...@intel.com>
---
This patch is kernel patch.
The user space patch can be found here.
https://urldefense.proofpoint.com/v2/url?u=https-3A__www.spinics.net_lists_kern
.
Tested-by: Madhavan Srinivasan
Signed-off-by: Kan Liang
---
This patch is kernel patch.
The user space patch can be found here.
https://urldefense.proofpoint.com/v2/url?u=https-3A__www.spinics.net_lists_kernel_msg2587093.html=DwIBaQ=jf_iaSHvJObTbx-siA1ZOg
my bad, missed to change the authership of this patch.
From: Anju T Sudhakar <a...@linux.vnet.ibm.com>
On Wednesday 19 July 2017 03:06 AM, Madhavan Srinivasan wrote:
Add support to register Thread In-Memory Collection pmu counters.
Patch adds thread imc specific data structures,
my bad, missed to change the authership of this patch.
From: Anju T Sudhakar
On Wednesday 19 July 2017 03:06 AM, Madhavan Srinivasan wrote:
Add support to register Thread In-Memory Collection pmu counters.
Patch adds thread imc specific data structures, along with memory
init functions
my bad, missed to change the authership of this patch.
From: Anju T Sudhakar <a...@linux.vnet.ibm.com>
On Wednesday 19 July 2017 03:06 AM, Madhavan Srinivasan wrote:
Add support to register Core In-Memory Collection pmu counters.
Patch adds core imc specific data structures, along with
my bad, missed to change the authership of this patch.
From: Anju T Sudhakar
On Wednesday 19 July 2017 03:06 AM, Madhavan Srinivasan wrote:
Add support to register Core In-Memory Collection pmu counters.
Patch adds core imc specific data structures, along with memory
init functions
my bad, missed to change the authership of this patch.
From: Anju T Sudhakar <a...@linux.vnet.ibm.com>
On Wednesday 19 July 2017 03:06 AM, Madhavan Srinivasan wrote:
Add support to register Nest In-Memory Collection pmu counters.
Patch adds a new device file called "imc-pmu.c&quo
my bad, missed to change the authership of this patch.
From: Anju T Sudhakar
On Wednesday 19 July 2017 03:06 AM, Madhavan Srinivasan wrote:
Add support to register Nest In-Memory Collection pmu counters.
Patch adds a new device file called "imc-pmu.c" under powerpc/perf
folder to c
;
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/perf/imc-pmu.c | 303 +++-
include/linux/cpuhotplug.h | 1 +
2 files changed, 299 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/pe
Add support to register Core In-Memory Collection pmu counters.
Patch adds core imc specific data structures, along with memory
init functions and cpuhotplug support.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/imc-pmu.c
/skiboot/blob/master/doc/opal-api/opal-imc-counters.rst
Patch updates the kernel side powernv platform code to support the new OPAL APIs
Signed-off-by: Hemant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Anju T Sudhakar <a...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Sr
/skiboot/blob/master/doc/opal-api/opal-imc-counters.rst
Patch updates the kernel side powernv platform code to support the new OPAL APIs
Signed-off-by: Hemant Kumar
Signed-off-by: Anju T Sudhakar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/opal-api.h| 11
;
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/perf/imc-pmu.c | 269 +++-
include/linux/cpuhotplug.h | 1 +
2 files changed, 266 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/pe
inux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/imc-pmu.h| 128 +
arch/powerpc/platforms/powernv/Makefile | 2 +-
arch/powerpc/platforms/powernv/opal-imc.c | 221 ++
arch/powe
Add support to register Thread In-Memory Collection pmu counters.
Patch adds thread imc specific data structures, along with memory
init functions and cpuhotplug support.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/imc
as device
memory sizes, event nodes information, base address for reserve
memory access (if any) and so on. Simple bare-minimum sutdown
function added which only "stops" the engines.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/pow
-by: Anju T Sudhakar <a...@linux.vnet.ibm.com>
Signed-off-by: Hemant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/perf/Makefile| 1 +
arch/powerpc/perf/imc-pmu.c | 748
Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/Makefile| 1 +
arch/powerpc/perf/imc-pmu.c | 748 ++
arch/powerpc/platforms/powernv/opal-imc.c | 5 +
include/linux/cpuhotplug.h
.
This patchset enables the nest IMC, core IMC and thread IMC
PMUs and is based on the initial work done by Madhavan Srinivasan.
"Nest Instrumentation Support" :
https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-August/132078.html
v1 for this patchset can be found here :
https://lwn.net/Artic
.
This patchset enables the nest IMC, core IMC and thread IMC
PMUs and is based on the initial work done by Madhavan Srinivasan.
"Nest Instrumentation Support" :
https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-August/132078.html
v1 for this patchset can be found here :
https://lwn.net/Artic
On Thursday 29 June 2017 01:11 AM, Thomas Gleixner wrote:
On Thu, 29 Jun 2017, Anju T Sudhakar wrote:
+static void cleanup_all_core_imc_memory(struct imc_pmu *pmu_ptr)
+{
+ struct imc_mem_info *ptr;
+
+ for (ptr = pmu_ptr->mem_info; ptr; ptr++) {
+ if (ptr->vbase[0])
On Thursday 29 June 2017 01:11 AM, Thomas Gleixner wrote:
On Thu, 29 Jun 2017, Anju T Sudhakar wrote:
+static void cleanup_all_core_imc_memory(struct imc_pmu *pmu_ptr)
+{
+ struct imc_mem_info *ptr;
+
+ for (ptr = pmu_ptr->mem_info; ptr; ptr++) {
+ if (ptr->vbase[0])
Monitor Mode Control Register 2 (MMCR2) is a 64-bit
register that contains 9-bit control fields for
controlling the operation of PMC1 - PMC6. Patch
to expose the MMCR2 spr in sysfs.
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/kernel/sysfs.c | 8
Monitor Mode Control Register 2 (MMCR2) is a 64-bit
register that contains 9-bit control fields for
controlling the operation of PMC1 - PMC6. Patch
to expose the MMCR2 spr in sysfs.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/kernel/sysfs.c | 8
1 file changed, 8 insertions
quot;)
Reported-by: Anton Blanchard <an...@samba.org>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/perf/power9-events-list.h | 4 +++-
arch/powerpc/perf/power9-pmu.c | 8 +++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/a
Correct "branch" event code of Power9 is "r4d05e".
Replace the current "branch" event code with "r4d05e"
and add a hack to use "r10012" as event code for
power9 dd1.
Fixes: d89f473ff6f8 ("powerpc/perf: Fix PM_BRU_CMPL event code for power9&
-ci/linux/commits/Madhavan-Srinivasan/IMC-Instrumentation-Support/20170609-183528
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
-ci/linux/commits/Madhavan-Srinivasan/IMC-Instrumentation-Support/20170609-183528
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
On Thursday 08 June 2017 01:45 PM, Peter Zijlstra wrote:
On Wed, Jun 07, 2017 at 04:22:24PM -0700, Andi Kleen wrote:
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index b1c0b187acfe..95daade294d7 100644
--- a/include/uapi/linux/perf_event.h
+++
On Thursday 08 June 2017 01:45 PM, Peter Zijlstra wrote:
On Wed, Jun 07, 2017 at 04:22:24PM -0700, Andi Kleen wrote:
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index b1c0b187acfe..95daade294d7 100644
--- a/include/uapi/linux/perf_event.h
+++
ctions for thread_imc, a new state
CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE is added to the list of existing
states.
Signed-off-by: Anju T Sudhakar <a...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/p
CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE is added to the list of existing
states.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/imc-pmu.c | 42 +++---
include/linux/cpuhotplug.h | 1 +
2 files changed, 40 insertions
n when the task is scheduled on to
different cpus.
Signed-off-by: Anju T Sudhakar <a...@linux.vnet.ibm.com>
Signed-off-by: Hemant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/imc-pmu.h| 4
on to
different cpus.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/imc-pmu.h| 4 +
arch/powerpc/perf/imc-pmu.c | 219 +-
arch/powerpc/platforms/powernv/opal-imc.c | 2
ibm.com>
Signed-off-by: Hemant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/imc-pmu.h| 1 +
arch/powerpc/include/asm/opal-api.h | 1 +
arch/powerpc/perf/imc-pmu.c | 1 +
arch/po
From: Anju T Sudhakar
Code to add support for detection of thread IMC events. It adds a new
domain IMC_DOMAIN_THREAD and it is determined with the help of the
"type" property in the imc device-tree.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan
: Anju T Sudhakar <a...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/imc-pmu.h| 1 +
arch/powerpc/include/asm/opal-api.h | 1 +
arch/powerpc/perf/imc-pmu.c | 265 ++
-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/imc-pmu.h| 1 +
arch/powerpc/include/asm/opal-api.h | 1 +
arch/powerpc/perf/imc-pmu.c | 265 +-
arch/powerpc/platforms/powernv/opal-imc.c | 7 +
include/linux/cpuhotplug.h
com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/opal-api.h| 14 +-
arch/powerpc/include/asm/opal.h| 4 +
arch/powerpc/perf/imc-pmu.c| 211 -
arch/powerpc/platforms/power
(for nest
units) is designated as new cpu to read counters. For this purpose, we
introduce a new state : CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/opal-api.h| 14
emant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/imc-pmu.h| 2 ++
arch/powerpc/include/asm/opal-api.h | 3 +++
arch/powerpc/perf/imc-pmu.c | 4
arch/powerpc/platf
This patch adds support for detection of core IMC events along with the
Nest IMC events. It adds a new domain IMC_DOMAIN_CORE and its determined
with the help of the "type" property in the IMC device tree.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by
its.
Signed-off-by: Anju T Sudhakar <a...@linux.vnet.ibm.com>
Signed-off-by: Hemant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/imc-pmu.h| 2 +
arch/powerpc/perf/Makefile|
T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/imc-pmu.h| 2 +
arch/powerpc/perf/Makefile| 3 +
arch/powerpc/perf/imc-pmu.c | 268 ++
arch/powerpc/platforms/powernv/opal-i
y this PMU
inherit the scale and unit properties of the PMU itself. For those
events, we need to set the common unit and scale values.
For failure to initialize any unit or any event, disable that unit and
continue setting up the rest of them.
Signed-off-by: Hemant Kumar <hem...@linux.vnet.i
y this PMU
inherit the scale and unit properties of the PMU itself. For those
events, we need to set the common unit and scale values.
For failure to initialize any unit or any event, disable that unit and
continue setting up the rest of them.
Signed-off-by: Hemant Kumar
Signed-off-by: Anju T Sudhak
Anju T Sudhakar <a...@linux.vnet.ibm.com>
Signed-off-by: Hemant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/Kconfig| 10 +
arch/powerpc/platforms/powernv/Makefile | 1 +
arch/powerpc
ar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/platforms/powernv/Kconfig| 10 +
arch/powerpc/platforms/powernv/Makefile | 1 +
arch/powerpc/platforms/powernv/opal-imc.c | 73 +++
arch/powerpc/platforms/powernv/opal.c | 18
4 files ch
Create a new header file to add the data structures and
macros needed for In-Memory Collection (IMC) counter support.
Signed-off-by: Anju T Sudhakar <a...@linux.vnet.ibm.com>
Signed-off-by: Hemant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@lin
Create a new header file to add the data structures and
macros needed for In-Memory Collection (IMC) counter support.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/imc-pmu.h | 99
.
This patchset enables the nest IMC, core IMC and thread IMC
PMUs and is based on the initial work done by Madhavan Srinivasan.
"Nest Instrumentation Support" :
https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-August/132078.html
v1 for this patchset can be found here :
https://lwn.net/Artic
.
This patchset enables the nest IMC, core IMC and thread IMC
PMUs and is based on the initial work done by Madhavan Srinivasan.
"Nest Instrumentation Support" :
https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-August/132078.html
v1 for this patchset can be found here :
https://lwn.net/Artic
On Tuesday 06 June 2017 03:57 PM, Thomas Gleixner wrote:
On Mon, 5 Jun 2017, Anju T Sudhakar wrote:
static void thread_imc_mem_alloc(int cpu_id)
{
- u64 ldbar_addr, ldbar_value;
int phys_id = topology_physical_package_id(cpu_id);
per_cpu_add[cpu_id] =
On Tuesday 06 June 2017 03:57 PM, Thomas Gleixner wrote:
On Mon, 5 Jun 2017, Anju T Sudhakar wrote:
static void thread_imc_mem_alloc(int cpu_id)
{
- u64 ldbar_addr, ldbar_value;
int phys_id = topology_physical_package_id(cpu_id);
per_cpu_add[cpu_id] =
On Thursday 01 June 2017 01:57 PM, Shriya wrote:
Add support for POWER8+ PVR 004c0100 for Garrison
patch title could have been,
tools/perf/pmu-events: Support additional POWER8+ PVR in mapfile
But other than that,
Reviewed-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
Sign
On Thursday 01 June 2017 01:57 PM, Shriya wrote:
Add support for POWER8+ PVR 004c0100 for Garrison
patch title could have been,
tools/perf/pmu-events: Support additional POWER8+ PVR in mapfile
But other than that,
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Shriya
---
tools
ucture. Patch to fix the same.
Fixes: 8d911904f3ce4 ('powerpc/perf: Add restrictions to PMC5 in power9 DD1')
Reported-by: Shriya <shri...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/perf/power9-pmu.c | 4 ++--
1 file changed, 2 insertion
ucture. Patch to fix the same.
Fixes: 8d911904f3ce4 ('powerpc/perf: Add restrictions to PMC5 in power9 DD1')
Reported-by: Shriya
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/power9-pmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf/power9-pmu.c
Sorry for delayed response.
On Wednesday 10 May 2017 05:39 PM, Thomas Gleixner wrote:
On Thu, 4 May 2017, Anju T Sudhakar wrote:
+/*
+ * nest_init : Initializes the nest imc engine for the current chip.
+ * by default the nest engine is disabled.
+ */
+static void nest_init(int *cpu_opal_rc)
Sorry for delayed response.
On Wednesday 10 May 2017 05:39 PM, Thomas Gleixner wrote:
On Thu, 4 May 2017, Anju T Sudhakar wrote:
+/*
+ * nest_init : Initializes the nest imc engine for the current chip.
+ * by default the nest engine is disabled.
+ */
+static void nest_init(int *cpu_opal_rc)
hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/Kconfig| 10 +++
arch/powerpc/platforms/powernv/Makefile | 1 +
arch/powerpc/platforms/powernv/opal-imc.c | 140 ++
arch/powerpc/
evice tree parsing logic is separated from the PMU creation
functions (which is done in subsequent patches).
Patch also adds a CONFIG_HV_PERF_IMC_CTRS for the IMC driver.
Signed-off-by: Anju T Sudhakar
Signed-off-by: Hemant Kumar
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/platfor
On Friday 12 May 2017 09:03 AM, Michael Ellerman wrote:
Stewart Smith <stew...@linux.vnet.ibm.com> writes:
Madhavan Srinivasan <ma...@linux.vnet.ibm.com> writes:
* in patch 9 should opal_imc_counters_init return something other
than OPAL_SUCCESS in the cas
On Friday 12 May 2017 09:03 AM, Michael Ellerman wrote:
Stewart Smith writes:
Madhavan Srinivasan writes:
* in patch 9 should opal_imc_counters_init return something other
than OPAL_SUCCESS in the case on invalid arguments? Maybe
OPAL_PARAMETER? (I think you fix
On Friday 12 May 2017 07:48 AM, Stewart Smith wrote:
Madhavan Srinivasan <ma...@linux.vnet.ibm.com> writes:
* in patch 9 should opal_imc_counters_init return something other
than OPAL_SUCCESS in the case on invalid arguments? Maybe
OPAL_PARAMETER? (I think y
On Friday 12 May 2017 07:48 AM, Stewart Smith wrote:
Madhavan Srinivasan writes:
* in patch 9 should opal_imc_counters_init return something other
than OPAL_SUCCESS in the case on invalid arguments? Maybe
OPAL_PARAMETER? (I think you fix this in a later patch anyway
igned-off-by: Hemant Kumar <hem...@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <ma...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/imc-pmu.h | 4 +
arch/powerpc/include/asm/opal-api.h| 12 +-
arch/powerpc/include/asm/opal.h| 4
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