Re: [PATCH v2 2/3] powerpc/powernv/idle: save-restore DAWR0,DAWRX0 for P10

On Fri, 2020-07-10 at 10:52 +0530, Pratik Rajesh Sampat wrote: > Additional registers DAWR0, DAWRX0 may be lost on Power 10 for > stop levels < 4. > Therefore save the values of these SPRs before entering a "stop" > state and restore their values on wakeup. > > Signed-off-by: Pratik Rajesh

CVE-2019-15031: Linux kernel: powerpc: data leak with FP/VMX triggerable by interrupt in transaction

The Linux kernel for powerpc since v4.15 has a bug in it's TM handling during interrupts where any user can read the FP/VMX registers of a difference user's process. Users of TM + FP/VMX can also experience corruption of their FP/VMX state. To trigger the bug, a process starts a transaction with

CVE-2019-15030: Linux kernel: powerpc: data leak with FP/VMX triggerable by unavailable exception in transaction

The Linux kernel for powerpc since v4.12 has a bug in it's TM handling where any user can read the FP/VMX registers of a difference user's process. Users of TM + FP/VMX can also experience corruption of their FP/VMX state. To trigger the bug, a process starts a transaction and reads a FP/VMX

CVE-2019-13648: Linux kernel: powerpc: kernel crash in TM handling triggerable by any local user

The Linux kernel for powerpc since v3.9 has a bug in the TM handling where any unprivileged local user may crash the operating system. This bug affects machines using 64-bit CPUs where Transactional Memory (TM) is not present or has been disabled (see below for more details on affected CPUs).

Re: [PATCH 5/5] Powerpc/Watchpoint: Fix length calculation for unaligned target

On Tue, 2019-06-18 at 09:57 +0530, Ravi Bangoria wrote: > Watchpoint match range is always doubleword(8 bytes) aligned on > powerpc. If the given range is crossing doubleword boundary, we > need to increase the length such that next doubleword also get > covered. Ex, > > address len =

Re: [PATCH 0/5] Powerpc/hw-breakpoint: Fixes plus Code refactor

On Tue, 2019-06-18 at 08:01 +0200, Christophe Leroy wrote: > > Le 18/06/2019 à 06:27, Ravi Bangoria a écrit : > > patch 1-3: Code refactor > > patch 4: Speedup disabling breakpoint > > patch 5: Fix length calculation for unaligned targets > > While you are playing with hw breakpoints, did you

Re: [PATCH 4/5] Powerpc/hw-breakpoint: Optimize disable path

On Tue, 2019-06-18 at 09:57 +0530, Ravi Bangoria wrote: > Directly setting dawr and dawrx with 0 should be enough to > disable watchpoint. No need to reset individual bits in > variable and then set in hw. This seems like a pointless optimisation to me. I'm all for adding more code/complexity

Re: [PATCH 3/5] Powerpc/hw-breakpoint: Refactor set_dawr()

This is going to collide with this patch https://patchwork.ozlabs.org/patch/1109594/ Mikey On Tue, 2019-06-18 at 09:57 +0530, Ravi Bangoria wrote: > Remove unnecessary comments. Code itself is self explanatory. > And, ISA already talks about MRD field. I Don't think we need > to re-describe

Re: [PATCH 1/5] Powerpc/hw-breakpoint: Replace stale do_dabr() with do_break()

> Subject: Powerpc/hw-breakpoint: Replace stale do_dabr() with do_break() Can you add the word "comment" to this subject. Currently it implies there are code changes here. Mikey On Tue, 2019-06-18 at 09:57 +0530, Ravi Bangoria wrote: > do_dabr() was renamed with do_break() long ago. But I

Re: [PATCH] Powerpc/Watchpoint: Restore nvgprs while returning from exception

On Thu, 2019-06-06 at 12:59 +0530, Ravi Bangoria wrote: > Powerpc hw triggers watchpoint before executing the instruction. > To make trigger-after-execute behavior, kernel emulates the > instruction. If the instruction is 'load something into non- > volatile register', exception handler should

Re: [PATCH 0/7] powerpc: Modernize unhandled signals message

On Tue, 2018-07-24 at 16:27 -0300, Murilo Opsfelder Araujo wrote: > Hi, everyone. > > This series was inspired by the need to modernize and display more > informative messages about unhandled signals. > > The "unhandled signal NN" is not very informative. We thought it would > be helpful

Re: [PATCH 0/7] powerpc: Modernize unhandled signals message

On Tue, 2018-07-24 at 16:27 -0300, Murilo Opsfelder Araujo wrote: > Hi, everyone. > > This series was inspired by the need to modernize and display more > informative messages about unhandled signals. > > The "unhandled signal NN" is not very informative. We thought it would > be helpful

Re: [RESEND][PATCH] powerpc/powernv : Save/Restore SPRG3 on entry/exit from stop.

On Wed, 2018-07-18 at 13:42 +0530, Gautham R Shenoy wrote: > Hello Mikey, > > On Wed, Jul 18, 2018 at 09:24:19AM +1000, Michael Neuling wrote: > > > > > DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); > > > diff --git a/arch/powerpc/kernel/idle_book3s.S > >

Re: [RESEND][PATCH] powerpc/powernv : Save/Restore SPRG3 on entry/exit from stop.

On Wed, 2018-07-18 at 13:42 +0530, Gautham R Shenoy wrote: > Hello Mikey, > > On Wed, Jul 18, 2018 at 09:24:19AM +1000, Michael Neuling wrote: > > > > > DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); > > > diff --git a/arch/powerpc/kernel/idle_book3s.S > >

Re: [PATCH 2/2] powerpc: Enable ASYM_SMT on interleaved big-core systems

On Fri, 2018-05-11 at 16:47 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > Each of the SMT4 cores forming a fused-core are more or less > independent units. Thus when multiple tasks are scheduled to run on > the fused core, we get the best performance

Re: [PATCH 2/2] powerpc: Enable ASYM_SMT on interleaved big-core systems

On Fri, 2018-05-11 at 16:47 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > Each of the SMT4 cores forming a fused-core are more or less > independent units. Thus when multiple tasks are scheduled to run on > the fused core, we get the best performance when the tasks are spread >

Re: [PATCH 1/2] powerpc: Detect the presence of big-core with interleaved threads

Thanks for posting this... A couple of comments below. On Fri, 2018-05-11 at 16:47 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > A pair of IBM POWER9 SMT4 cores can be fused together to form a > big-core with 8 SMT threads. This can be discovered via

Re: [PATCH 1/2] powerpc: Detect the presence of big-core with interleaved threads

Thanks for posting this... A couple of comments below. On Fri, 2018-05-11 at 16:47 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > A pair of IBM POWER9 SMT4 cores can be fused together to form a > big-core with 8 SMT threads. This can be discovered via the > "ibm,thread-groups"

[PATCH] nvme-pci: Fix NULL ptr deref in EEH code

+0x124/0x170 [c00ff50f3dc0] c008fed0 kthread+0x14c/0x154 [c00ff50f3e30] c000b594 ret_from_kernel_thread+0x5c/0xc8 This fixes the NULL ptr deref. Signed-off-by: Michael Neuling <mi...@neuling.org> --- drivers/nvme/host/pci.c | 3 +++ 1 file changed, 3 insertions(+) diff

[PATCH] nvme-pci: Fix NULL ptr deref in EEH code

+0x124/0x170 [c00ff50f3dc0] c008fed0 kthread+0x14c/0x154 [c00ff50f3e30] c000b594 ret_from_kernel_thread+0x5c/0xc8 This fixes the NULL ptr deref. Signed-off-by: Michael Neuling --- drivers/nvme/host/pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/nvme

Re: [PATCH v2 15/18] powerpc: Emulate paste instruction

@ -1924,6 +1987,7 @@ struct ppc_emulated ppc_emulated = { >   WARN_EMULATED_SETUP(mfdscr), >   WARN_EMULATED_SETUP(mtdscr), >   WARN_EMULATED_SETUP(lq_stq), > + WARN_EMULATED_SETUP(paste), You'll need to rebase this on powerpc/next as this has changed upstream. Mikey

Re: [PATCH v2 15/18] powerpc: Emulate paste instruction

@ -1924,6 +1987,7 @@ struct ppc_emulated ppc_emulated = { >   WARN_EMULATED_SETUP(mfdscr), >   WARN_EMULATED_SETUP(mtdscr), >   WARN_EMULATED_SETUP(lq_stq), > + WARN_EMULATED_SETUP(paste), You'll need to rebase this on powerpc/next as this has changed upstream. Mikey

Re: [PATCH v8 00/10] Enable VAS

py_crb() and > vas_paste_crb() calls in drivers/crypto/nx/nx-842-powernv.c. > See also PATCH 10/10. > > Git Tree: > > https://github.com/sukadev/linux/  > Branch: vas-kern-v8 > > Thanks to input from Ben Herrenschmidt, Michael Neuling, Michael

Re: [PATCH v8 00/10] Enable VAS

vas_paste_crb() calls in drivers/crypto/nx/nx-842-powernv.c. > See also PATCH 10/10. > > Git Tree: > > https://github.com/sukadev/linux/  > Branch: vas-kern-v8 > > Thanks to input from Ben Herrenschmidt, Michael Neuling, Michael Ellerman &g

Re: Status of reverted Linux patch "tty: Fix ldisc crash on reopened tty", Linux 4.9 kernel frequent crashes

el. > > > > > > Mikulas reported he's able to trigger the same crash on Linux 4.10: > > https://www.spinics.net/lists/kernel/msg2440637.html > > https://lists.gt.net/linux/kernel/2664604?search_string=ldisc%20reopened;#26 > > 64604 > > > > Michael Ne

Re: Status of reverted Linux patch "tty: Fix ldisc crash on reopened tty", Linux 4.9 kernel frequent crashes

el. > > > > > > Mikulas reported he's able to trigger the same crash on Linux 4.10: > > https://www.spinics.net/lists/kernel/msg2440637.html > > https://lists.gt.net/linux/kernel/2664604?search_string=ldisc%20reopened;#26 > > 64604 > > > > Michael Ne

Re: [PATCH v6 17/17] powerpc/vas: Document FTW API/usage

On Tue, 2017-08-08 at 16:07 -0700, Sukadev Bhattiprolu wrote: > Document the usage of the VAS Fast thread-wakeup API. > > Thanks for input/comments from Benjamin Herrenschmidt, Michael Neuling, > Michael Ellerman, Robert Blackmore, Ian Munsie, Haren Myneni, Paul Mackerras. >

Re: [PATCH v6 17/17] powerpc/vas: Document FTW API/usage

On Tue, 2017-08-08 at 16:07 -0700, Sukadev Bhattiprolu wrote: > Document the usage of the VAS Fast thread-wakeup API. > > Thanks for input/comments from Benjamin Herrenschmidt, Michael Neuling, > Michael Ellerman, Robert Blackmore, Ian Munsie, Haren Myneni, Paul Mackerras. >

Re: [PATCH v6 14/17] powerpc: Add support for setting SPRN_TIDR

On Tue, 2017-08-08 at 16:06 -0700, Sukadev Bhattiprolu wrote: > We need the SPRN_TIDR to bet set for use with fast thread-wakeup > (core-to-core wakeup).  Each thread in a process needs to have a > unique id within the process but as explained below, for now, we > assign globally unique thread ids

Re: [PATCH v6 14/17] powerpc: Add support for setting SPRN_TIDR

On Tue, 2017-08-08 at 16:06 -0700, Sukadev Bhattiprolu wrote: > We need the SPRN_TIDR to bet set for use with fast thread-wakeup > (core-to-core wakeup).  Each thread in a process needs to have a > unique id within the process but as explained below, for now, we > assign globally unique thread ids

Re: [PATCH 2/3] powernv:idle: Decouple TB restore & Per-core SPRs restore

On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > The idle-exit code assumes that if Timebase is not lost, then neither > are the per-core hypervisor resources lost. Double negative! How about: The idle-exit code assumes that

Re: [PATCH 2/3] powernv:idle: Decouple TB restore & Per-core SPRs restore

On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > The idle-exit code assumes that if Timebase is not lost, then neither > are the per-core hypervisor resources lost. Double negative! How about: The idle-exit code assumes that if the timebase is

Re: [PATCH 1/3] powernv:idle: Use correct IDLE_THREAD_BITS in POWER8/9

On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > This patch ensures that POWER8 and POWER9 processors use the correct > value of IDLE_THREAD_BITS as POWER8 has 8 threads per core and hence > the IDLE_THREAD_BITS should be 0xFF

Re: [PATCH 1/3] powernv:idle: Use correct IDLE_THREAD_BITS in POWER8/9

On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > This patch ensures that POWER8 and POWER9 processors use the correct > value of IDLE_THREAD_BITS as POWER8 has 8 threads per core and hence > the IDLE_THREAD_BITS should be 0xFF while POWER9 has only 4

Re: [PATCH 3/3] powernv:idle: Set LPCR_UPRT on wakeup from deep-stop

On Thu, 2017-04-13 at 14:12 +1000, Benjamin Herrenschmidt wrote: > On Thu, 2017-04-13 at 09:28 +0530, Aneesh Kumar K.V wrote: > > >   #endif > > >    mtctr   r12 > > >    bctrl > > > +/* > > > + * cur_cpu_spec->cpu_restore would restore LPCR to a > > > + * sane value that is set at early

Re: [PATCH 3/3] powernv:idle: Set LPCR_UPRT on wakeup from deep-stop

On Thu, 2017-04-13 at 14:12 +1000, Benjamin Herrenschmidt wrote: > On Thu, 2017-04-13 at 09:28 +0530, Aneesh Kumar K.V wrote: > > >   #endif > > >    mtctr   r12 > > >    bctrl > > > +/* > > > + * cur_cpu_spec->cpu_restore would restore LPCR to a > > > + * sane value that is set at early

Re: [PATCH] tty:tty_ldisc: add tty_ldisc_lock|unlock to prevent concurrent update to ldisc in tty_ldisc_deinit

Wang, Applying this, with the other one on top and it doesn't fix the problem (applied on next-20170405). I tried each patch by itself, with the same bad result. Thanks for the help but the backtrace is the same: Unable to handle kernel paging request for data at address 0x2260 Faulting

Re: [PATCH] tty:tty_ldisc: add tty_ldisc_lock|unlock to prevent concurrent update to ldisc in tty_ldisc_deinit

Wang, Applying this, with the other one on top and it doesn't fix the problem (applied on next-20170405). I tried each patch by itself, with the same bad result. Thanks for the help but the backtrace is the same: Unable to handle kernel paging request for data at address 0x2260 Faulting

Re: [PATCH] tty: Fix crash with flush_to_ldisc()

Al, On Fri, 2017-04-07 at 05:12 +0100, Al Viro wrote: > On Fri, Apr 07, 2017 at 01:50:53PM +1000, Michael Neuling wrote: > > > diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c > > index bdf0e6e899..a2a9832a42 100644 > > --- a/drivers/tty/n_tty.c >

Re: [PATCH] tty: Fix crash with flush_to_ldisc()

Al, On Fri, 2017-04-07 at 05:12 +0100, Al Viro wrote: > On Fri, Apr 07, 2017 at 01:50:53PM +1000, Michael Neuling wrote: > > > diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c > > index bdf0e6e899..a2a9832a42 100644 > > --- a/drivers/tty/n_tty.c >

[PATCH] tty: Fix crash with flush_to_ldisc()

Cc: <sta...@vger.kernel.org> [4.10+] Signed-off-by: Michael Neuling <mi...@neuling.org> --- drivers/tty/n_tty.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c index bdf0e6e899..a2a9832a42 100644 --- a/drivers/tty/n_tty.

[PATCH] tty: Fix crash with flush_to_ldisc()

Cc: [4.10+] Signed-off-by: Michael Neuling --- drivers/tty/n_tty.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c index bdf0e6e899..a2a9832a42 100644 --- a/drivers/tty/n_tty.c +++ b/drivers/tty/n_tty.c @@ -1668,11 +1668,17 @@ sta

Re: tty crash in tty_ldisc_receive_buf()

t;termios_rwsem); > > +   ldata = tty->disc_data; I did try just that alone and it didn't help. Mikey ------------ >From 75c2a0369450692946ca8cc7ac148a98deaecd2a Mon Sep 17 00:00:00 2001 From: Michael Neuling <mi...@neulin

Re: tty crash in tty_ldisc_receive_buf()

t;termios_rwsem); > > +   ldata = tty->disc_data; I did try just that alone and it didn't help. Mikey ------------ >From 75c2a0369450692946ca8cc7ac148a98deaecd2a Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: F

Re: tty crash in tty_ldisc_receive_buf()

> > If anyone has an idea, I'm happy to try a patch. > > Can you try this one [1]. Rob, I'm still hitting it when I apply that on next-20170405. Crash below.. Any other clues? [  229.422825] Unable to handle kernel paging request for data at address 0x2260 [  229.423681] Faulting

Re: tty crash in tty_ldisc_receive_buf()

> > If anyone has an idea, I'm happy to try a patch. > > Can you try this one [1]. Rob, I'm still hitting it when I apply that on next-20170405. Crash below.. Any other clues? [  229.422825] Unable to handle kernel paging request for data at address 0x2260 [  229.423681] Faulting

tty crash in tty_ldisc_receive_buf()

Hi all, We are seeing the following crash (in linux-next but has been around since at least v4.10). [  417.514499] Unable to handle kernel paging request for data at address 0x2260 [  417.515361] Faulting instruction address: 0xc06fad80 cpu 0x15: Vector: 300 (Data Access) at

tty crash in tty_ldisc_receive_buf()

Hi all, We are seeing the following crash (in linux-next but has been around since at least v4.10). [  417.514499] Unable to handle kernel paging request for data at address 0x2260 [  417.515361] Faulting instruction address: 0xc06fad80 cpu 0x15: Vector: 300 (Data Access) at

Re: linux-next: manual merge of the tty tree with the tty.current tree

On Mon, 2017-03-20 at 10:26 +0100, Dmitry Vyukov wrote: > On Mon, Mar 20, 2017 at 10:21 AM, Dmitry Vyukov wrote: > > On Mon, Mar 20, 2017 at 3:28 AM, Stephen Rothwell > > wrote: > > > Hi Greg, > > > > > > Today's linux-next merge of the tty tree got a

Re: linux-next: manual merge of the tty tree with the tty.current tree

On Mon, 2017-03-20 at 10:26 +0100, Dmitry Vyukov wrote: > On Mon, Mar 20, 2017 at 10:21 AM, Dmitry Vyukov wrote: > > On Mon, Mar 20, 2017 at 3:28 AM, Stephen Rothwell > > wrote: > > > Hi Greg, > > > > > > Today's linux-next merge of the tty tree got a conflict in: > > > > > >  

[PATCH] tty: Fix ldisc crash on reopened tty

892d1fa7eaae ("tty: Destroy ldisc instance on hangup") Reported-by: Mikulas Patocka <mpato...@redhat.com> Signed-off-by: Peter Hurley <pe...@hurleysoftware.com> Signed-off-by: Michael Neuling <mi...@neuling.org> --- gregkh, can you take this? It never made i

[PATCH] tty: Fix ldisc crash on reopened tty

stroy ldisc instance on hangup") Reported-by: Mikulas Patocka Signed-off-by: Peter Hurley Signed-off-by: Michael Neuling --- gregkh, can you take this? It never made it upstream and Peter Hurley doesn't seem to be responding to email since mid 2016. I'm reposting this from https://patchwork.

Re: tty crash in Linux 4.6

> This patch works, I've had no tty crashes since applying it. > > I've seen that you haven't sent this patch yet to Linux-4.7-rc and > Linux-4.6-stable. Will you? Or did you create a different patch? We are hitting this now on powerpc. This patch never seemed to make it upstream

Re: tty crash in Linux 4.6

> This patch works, I've had no tty crashes since applying it. > > I've seen that you haven't sent this patch yet to Linux-4.7-rc and > Linux-4.6-stable. Will you? Or did you create a different patch? We are hitting this now on powerpc. This patch never seemed to make it upstream

Re: [PATCH 1/2] mm/autonuma: Let architecture override how the write bit should be stashed in a protnone pte.

t; > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> FWIW this is pretty simple and helps with us in powerpc... Acked-By: Michael Neuling <mi...@neuling.org> > --- >  include/asm-generic/pgtable.h | 16 >  mm/huge_memory.c 

Re: [PATCH 1/2] mm/autonuma: Let architecture override how the write bit should be stashed in a protnone pte.

t; > Signed-off-by: Aneesh Kumar K.V FWIW this is pretty simple and helps with us in powerpc... Acked-By: Michael Neuling > --- >  include/asm-generic/pgtable.h | 16 >  mm/huge_memory.c  |  4 ++-- >  mm/memory.c   |  2 +- >  mm/mpro

Re: [PATCH 2/2] powerpc/mm/autonuma: Switch ppc64 to its own implementeation of saved write

h pte, we will > clear > the _PAGE_PRIVILEGED bit. The pte still remain non-accessible from both user > and kernel. > > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> FWIW I've tested this, so: Acked-By: Michael Neuling <mi...@neuling.org> > --- &g

Re: [PATCH 2/2] powerpc/mm/autonuma: Switch ppc64 to its own implementeation of saved write

h pte, we will > clear > the _PAGE_PRIVILEGED bit. The pte still remain non-accessible from both user > and kernel. > > Signed-off-by: Aneesh Kumar K.V FWIW I've tested this, so: Acked-By: Michael Neuling > --- >  arch/powerpc/include/asm/book3s/64/mmu-hash.h |  3 +++ >  a

Re: [PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online

R. Shenoy <e...@linux.vnet.ibm.com> Tested here on my configuration... FWIW Acked-By: Michael Neuling <mi...@neuling.org> > --- >  arch/powerpc/kernel/cpu_setup_power.S | 2 ++ >  1 file changed, 2 insertions(+) > > diff --git a/arch/powerpc/kernel/cpu_setup_power.S >

Re: [PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online

configuration... FWIW Acked-By: Michael Neuling > --- >  arch/powerpc/kernel/cpu_setup_power.S | 2 ++ >  1 file changed, 2 insertions(+) > > diff --git a/arch/powerpc/kernel/cpu_setup_power.S > b/arch/powerpc/kernel/cpu_setup_power.S > index 52ff3f0..37ad045 100644 > ---

Re: [PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online

On Wed, 2016-11-23 at 10:30 +1100, Michael Ellerman wrote: > "Gautham R. Shenoy" writes: > > > From: "Gautham R. Shenoy" > > > > Ensure that PSSCR is set to a safe value corresponding to no > > state-loss each time a POWER9 CPU comes online. >

Re: [PATCH] powernv: Clear SPRN_PSSCR when a POWER9 CPU comes online

On Wed, 2016-11-23 at 10:30 +1100, Michael Ellerman wrote: > "Gautham R. Shenoy" writes: > > > From: "Gautham R. Shenoy" > > > > Ensure that PSSCR is set to a safe value corresponding to no > > state-loss each time a POWER9 CPU comes online. > > Is this a bug fix? I can't tell from the change

Re: [PATCH v7 07/11] powerpc/powernv: Add platform support for stop instruction

> > > > > > @@ -439,7 +540,18 @@ timebase_resync: > > >    */ > > >   bne cr4,clear_lock > > >   > > > - /* Restore per core state */ > > > + /* > > > +  * First thread in the core to wake up and its waking up > > > with > > > +  * complete hypervisor state loss. Restore per core > > >

Re: [PATCH v7 07/11] powerpc/powernv: Add platform support for stop instruction

> > > > > > @@ -439,7 +540,18 @@ timebase_resync: > > >    */ > > >   bne cr4,clear_lock > > >   > > > - /* Restore per core state */ > > > + /* > > > +  * First thread in the core to wake up and its waking up > > > with > > > +  * complete hypervisor state loss. Restore per core > > >

Re: [PATCH v7 00/11] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states

Except for the issue with patch 7 I've already commented on the rest of this series is good with me.  FWIW: Acked-by: Michael Neuling <mi...@neuling.org> Thanks. On Fri, 2016-07-08 at 02:17 +0530, Shreyas B. Prabhu wrote: > POWER ISA v3 defines a new idle processor core mechanism. I

Re: [PATCH v7 00/11] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states

Except for the issue with patch 7 I've already commented on the rest of this series is good with me.  FWIW: Acked-by: Michael Neuling Thanks. On Fri, 2016-07-08 at 02:17 +0530, Shreyas B. Prabhu wrote: > POWER ISA v3 defines a new idle processor core mechanism. In summary, >  

Re: [PATCH v7 09/11] cpuidle/powernv: cleanup powernv_add_idle_states

>   /* > @@ -230,7 +238,7 @@ static int powernv_add_idle_states(void) >   strcpy(powernv_states[nr_idle_states].desc, > "FastSleep"); >   powernv_states[nr_idle_states].flags = > CPUIDLE_FLAG_TIMER_STOP; >  

Re: [PATCH v7 09/11] cpuidle/powernv: cleanup powernv_add_idle_states

>   /* > @@ -230,7 +238,7 @@ static int powernv_add_idle_states(void) >   strcpy(powernv_states[nr_idle_states].desc, > "FastSleep"); >   powernv_states[nr_idle_states].flags = > CPUIDLE_FLAG_TIMER_STOP; >  

Re: [PATCH v7 07/11] powerpc/powernv: Add platform support for stop instruction

> diff --git a/arch/powerpc/include/asm/cpuidle.h > b/arch/powerpc/include/asm/cpuidle.h > index d2f99ca..3d7fc06 100644 > --- a/arch/powerpc/include/asm/cpuidle.h > +++ b/arch/powerpc/include/asm/cpuidle.h > @@ -13,6 +13,8 @@ >  #ifndef __ASSEMBLY__ >  extern u32

Re: [PATCH v7 07/11] powerpc/powernv: Add platform support for stop instruction

> diff --git a/arch/powerpc/include/asm/cpuidle.h > b/arch/powerpc/include/asm/cpuidle.h > index d2f99ca..3d7fc06 100644 > --- a/arch/powerpc/include/asm/cpuidle.h > +++ b/arch/powerpc/include/asm/cpuidle.h > @@ -13,6 +13,8 @@ >  #ifndef __ASSEMBLY__ >  extern u32

Re: [PATCH v6 07/11] powerpc/powernv: set power_save func after the idle states are initialized

> > Please merge that one as-is now, no need to wait for the rest, as > otherwise pwoer9 crashes at boot. It doesn't need to wait for the > rest of the series. Acked-by: Michael Neuling <mi...@neuling.org> For the same reason. Without this we need powersave=off on the cmdline on POWER9.

Re: [PATCH v6 07/11] powerpc/powernv: set power_save func after the idle states are initialized

9 crashes at boot. It doesn't need to wait for the > rest of the series. Acked-by: Michael Neuling For the same reason. Without this we need powersave=off on the cmdline on POWER9. Mikey > > Cheers, > Ben. > > > > > --- > > - No changes since v1 > > > >  ar

Re: [v6, 08/11] powerpc/powernv: Add platform support for stop instruction

> > > +#define OPAL_PM_TIMEBASE_STOP0x0002 > > > +#define OPAL_PM_LOSE_HYP_CONTEXT 0x2000 > > > +#define OPAL_PM_LOSE_FULL_CONTEXT0x4000 > > >  #define OPAL_PM_NAP_ENABLED 0x0001 > > >  #define OPAL_PM_SLEEP_ENABLED0x0002 > > >  

Re: [v6, 08/11] powerpc/powernv: Add platform support for stop instruction

> > > +#define OPAL_PM_TIMEBASE_STOP0x0002 > > > +#define OPAL_PM_LOSE_HYP_CONTEXT 0x2000 > > > +#define OPAL_PM_LOSE_FULL_CONTEXT0x4000 > > >  #define OPAL_PM_NAP_ENABLED 0x0001 > > >  #define OPAL_PM_SLEEP_ENABLED0x0002 > > >  

Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction

On Wed, 2016-06-08 at 22:31 +0530, Shreyas B Prabhu wrote: > Hi Ben, > > Sorry for the delayed response. > > On 06/06/2016 03:58 AM, Benjamin Herrenschmidt wrote: > > > > On Thu, 2016-06-02 at 07:38 -0500, Shreyas B. Prabhu wrote: > > > > > > @@ -61,8 +72,13 @@ save_sprs_to_stack: > > >    

Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction

On Wed, 2016-06-08 at 22:31 +0530, Shreyas B Prabhu wrote: > Hi Ben, > > Sorry for the delayed response. > > On 06/06/2016 03:58 AM, Benjamin Herrenschmidt wrote: > > > > On Thu, 2016-06-02 at 07:38 -0500, Shreyas B. Prabhu wrote: > > > > > > @@ -61,8 +72,13 @@ save_sprs_to_stack: > > >    

Re: [RFC][PATCH 4/7] sched: Replace sd_busy/nr_busy_cpus with sched_domain_shared

On Thu, 2016-05-12 at 13:33 +0200, Peter Zijlstra wrote: > On Thu, May 12, 2016 at 09:07:52PM +1000, Michael Neuling wrote: > > > > On Thu, 2016-05-12 at 07:07 +0200, Peter Zijlstra wrote: > > > > > > > > But as per the above, Power7 and Power8 have expl

Re: [RFC][PATCH 4/7] sched: Replace sd_busy/nr_busy_cpus with sched_domain_shared

On Thu, 2016-05-12 at 13:33 +0200, Peter Zijlstra wrote: > On Thu, May 12, 2016 at 09:07:52PM +1000, Michael Neuling wrote: > > > > On Thu, 2016-05-12 at 07:07 +0200, Peter Zijlstra wrote: > > > > > > > > But as per the above, Power7 and Power8 have expl

Re: [RFC][PATCH 4/7] sched: Replace sd_busy/nr_busy_cpus with sched_domain_shared

On Thu, 2016-05-12 at 07:07 +0200, Peter Zijlstra wrote: > On Thu, May 12, 2016 at 12:05:37PM +1000, Michael Neuling wrote: > > > > On Wed, 2016-05-11 at 20:24 +0200, Peter Zijlstra wrote: > > > > > > On Wed, May 11, 2016 at 02:33:45PM +0200, Peter Zijlstra wro

Re: [RFC][PATCH 4/7] sched: Replace sd_busy/nr_busy_cpus with sched_domain_shared

On Thu, 2016-05-12 at 07:07 +0200, Peter Zijlstra wrote: > On Thu, May 12, 2016 at 12:05:37PM +1000, Michael Neuling wrote: > > > > On Wed, 2016-05-11 at 20:24 +0200, Peter Zijlstra wrote: > > > > > > On Wed, May 11, 2016 at 02:33:45PM +0200, Peter Zijlstra wro

Re: [RFC][PATCH 4/7] sched: Replace sd_busy/nr_busy_cpus with sched_domain_shared

On Wed, 2016-05-11 at 20:24 +0200, Peter Zijlstra wrote: > On Wed, May 11, 2016 at 02:33:45PM +0200, Peter Zijlstra wrote: > > > > Hmm, PPC folks; what does your topology look like? > > > > Currently your sched_domain_topology, as per arch/powerpc/kernel/smp.c > > seems to suggest your cores do

Re: [RFC][PATCH 4/7] sched: Replace sd_busy/nr_busy_cpus with sched_domain_shared

On Wed, 2016-05-11 at 20:24 +0200, Peter Zijlstra wrote: > On Wed, May 11, 2016 at 02:33:45PM +0200, Peter Zijlstra wrote: > > > > Hmm, PPC folks; what does your topology look like? > > > > Currently your sched_domain_topology, as per arch/powerpc/kernel/smp.c > > seems to suggest your cores do

Re: [PATCH 4.4 60/67] powerpc/tm: Check for already reclaimed tasks

On Tue, 2016-05-03 at 08:32 +0200, Jiri Slaby wrote: > On 01/27/2016, 07:12 PM, Greg Kroah-Hartman wrote: > > > > 4.4-stable review patch.  If anyone has any objections, please let me > > know. > > > > ---------- > > > > From: Michae

Re: [PATCH 4.4 60/67] powerpc/tm: Check for already reclaimed tasks

On Tue, 2016-05-03 at 08:32 +0200, Jiri Slaby wrote: > On 01/27/2016, 07:12 PM, Greg Kroah-Hartman wrote: > > > > 4.4-stable review patch.  If anyone has any objections, please let me > > know. > > > > ---------- > > >

Re: [PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

> diff --git a/arch/powerpc/include/asm/cputable.h > b/arch/powerpc/include/asm/cputable.h > index df4fb5f..a4739a1 100644 > --- a/arch/powerpc/include/asm/cputable.h > +++ b/arch/powerpc/include/asm/cputable.h > @@ -205,6 +205,7 @@ enum { >  #define CPU_FTR_DABRX >

Re: [PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

> diff --git a/arch/powerpc/include/asm/cputable.h > b/arch/powerpc/include/asm/cputable.h > index df4fb5f..a4739a1 100644 > --- a/arch/powerpc/include/asm/cputable.h > +++ b/arch/powerpc/include/asm/cputable.h > @@ -205,6 +205,7 @@ enum { >  #define CPU_FTR_DABRX >

Re: [PATCH 1/3] sched/fair: Fix asym packing to select correct cpu

On Wed, 2016-03-23 at 17:04 +0530, Srikar Dronamraju wrote: > If asymmetric packing is used when target cpu is busy, > update_sd_pick_busiest(), can select a lightly loaded cpu. > find_busiest_group() has checks to ensure asym packing is only used > when target cpu is not busy. However it may not

Re: [PATCH 1/3] sched/fair: Fix asym packing to select correct cpu

On Wed, 2016-03-23 at 17:04 +0530, Srikar Dronamraju wrote: > If asymmetric packing is used when target cpu is busy, > update_sd_pick_busiest(), can select a lightly loaded cpu. > find_busiest_group() has checks to ensure asym packing is only used > when target cpu is not busy. However it may not

Re: [PATCH v8 3/6] cpufreq: powernv: Remove cpu_to_chip_id() from hot-path

On Fri, 2016-03-18 at 15:04 +1100, Michael Neuling wrote: > On Wed, 2016-02-03 at 01:11 +0530, Shilpasri G Bhat wrote: > > > cpu_to_chip_id() does a DT walk through to find out the chip id by > > taking a contended device tree lock. This adds an unnecessary > > overhe

Re: [PATCH v8 3/6] cpufreq: powernv: Remove cpu_to_chip_id() from hot-path

On Fri, 2016-03-18 at 15:04 +1100, Michael Neuling wrote: > On Wed, 2016-02-03 at 01:11 +0530, Shilpasri G Bhat wrote: > > > cpu_to_chip_id() does a DT walk through to find out the chip id by > > taking a contended device tree lock. This adds an unnecessary > > overhe

Re: [PATCH v8 3/6] cpufreq: powernv: Remove cpu_to_chip_id() from hot-path

On Wed, 2016-02-03 at 01:11 +0530, Shilpasri G Bhat wrote: > cpu_to_chip_id() does a DT walk through to find out the chip id by > taking a contended device tree lock. This adds an unnecessary overhead > in a hot path. So instead of calling cpu_to_chip_id() everytime cache > the chip ids for all

Re: [PATCH v8 3/6] cpufreq: powernv: Remove cpu_to_chip_id() from hot-path

On Wed, 2016-02-03 at 01:11 +0530, Shilpasri G Bhat wrote: > cpu_to_chip_id() does a DT walk through to find out the chip id by > taking a contended device tree lock. This adds an unnecessary overhead > in a hot path. So instead of calling cpu_to_chip_id() everytime cache > the chip ids for all

Re: [PATCH v8 3/6] cpufreq: powernv: Remove cpu_to_chip_id() from hot-path

On Sat, 2016-03-19 at 09:37 +1100, Benjamin Herrenschmidt wrote: > On Fri, 2016-03-18 at 15:04 +1100, Michael Neuling wrote: > > > > static int nr_chips; > > +static DEFINE_PER_CPU(unsigned int, chip_id); > > > > /* > > * Note: The set of

Re: [PATCH v8 3/6] cpufreq: powernv: Remove cpu_to_chip_id() from hot-path

On Sat, 2016-03-19 at 09:37 +1100, Benjamin Herrenschmidt wrote: > On Fri, 2016-03-18 at 15:04 +1100, Michael Neuling wrote: > > > > static int nr_chips; > > +static DEFINE_PER_CPU(unsigned int, chip_id); > > > > /* > > * Note: The set of

Re: [PATCH v3 1/2] cxl: Add mechanism for delivering AFU driver specific events

On Wed, 2016-03-09 at 20:07 +0530, Vaibhav Jain wrote: > Hi Ian, > > Sorry for getting into this discussion late. I have few suggestions. > > Ian Munsie writes: > > > > diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig > > index 8756d06..560412c 100644 > >

Re: [PATCH v3 1/2] cxl: Add mechanism for delivering AFU driver specific events

On Wed, 2016-03-09 at 20:07 +0530, Vaibhav Jain wrote: > Hi Ian, > > Sorry for getting into this discussion late. I have few suggestions. > > Ian Munsie writes: > > > > diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig > > index 8756d06..560412c 100644 > > ---

Re: [PATCH] cxl: Add alternate MMIO error handling

ffset after any reads to a read/write offset. > > Due to these constraints, this functionality must be explicitly > requested by userspace when starting the context by passing in the > CXL_START_WORK_ERR_FF flag. > > Signed-off-by: Ian Munsie Acked-by: Michael Neuling

Re: [PATCH] cxl: Add alternate MMIO error handling

, this functionality must be explicitly requested by userspace when starting the context by passing in the CXL_START_WORK_ERR_FF flag. Signed-off-by: Ian Munsie imun...@au1.ibm.com Acked-by: Michael Neuling mi...@neuling.org --- drivers/misc/cxl/context.c | 14 ++ drivers/misc/cxl/cxl.h

Re: [PATCH 1/8] misc: cxl: clean up afu_read_config()

On Mon, 2015-07-27 at 00:18 +0300, Vladimir Zapolskiy wrote: > The sanity checks for overflow are not needed, because this is done on > caller side in fs/sysfs/file.c > > Signed-off-by: Vladimir Zapolskiy > Cc: linuxppc-...@lists.ozlabs.org > Cc: Ian Munsie > Cc: Mi

Re: [PATCH 1/8] misc: cxl: clean up afu_read_config()

: Michael Neuling mi...@neuling.org Acked-by: Michael Neuling mi...@neuling.org --- drivers/misc/cxl/sysfs.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/misc/cxl/sysfs.c b/drivers/misc/cxl/sysfs.c index 31f38bc..87cd747 100644 --- a/drivers/misc/cxl/sysfs.c

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