[tip:x86/cache] x86/intel_rdt/mba_sc: Feedback loop to dynamically update mem bandwidth

Commit-ID: de73f38f768021610bd305cf74ef3702fcf6a1eb Gitweb: https://git.kernel.org/tip/de73f38f768021610bd305cf74ef3702fcf6a1eb Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Fri, 20 Apr 2018 15:36:21 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mba_sc: Feedback loop to dynamically update mem bandwidth

Commit-ID: de73f38f768021610bd305cf74ef3702fcf6a1eb Gitweb: https://git.kernel.org/tip/de73f38f768021610bd305cf74ef3702fcf6a1eb Author: Vikas Shivappa AuthorDate: Fri, 20 Apr 2018 15:36:21 -0700 Committer: Thomas Gleixner CommitDate: Sat, 19 May 2018 13:16:44 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/mba_sc: Prepare for feedback loop

Commit-ID: ba0f26d8529c2dfc9aa6d9e8a338180737f8c1be Gitweb: https://git.kernel.org/tip/ba0f26d8529c2dfc9aa6d9e8a338180737f8c1be Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Fri, 20 Apr 2018 15:36:20 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mba_sc: Prepare for feedback loop

Commit-ID: ba0f26d8529c2dfc9aa6d9e8a338180737f8c1be Gitweb: https://git.kernel.org/tip/ba0f26d8529c2dfc9aa6d9e8a338180737f8c1be Author: Vikas Shivappa AuthorDate: Fri, 20 Apr 2018 15:36:20 -0700 Committer: Thomas Gleixner CommitDate: Sat, 19 May 2018 13:16:44 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/mba_sc: Add schemata support

Commit-ID: 8205a078ba7819c23558e31af4b3bda04d9b3bae Gitweb: https://git.kernel.org/tip/8205a078ba7819c23558e31af4b3bda04d9b3bae Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Fri, 20 Apr 2018 15:36:19 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mba_sc: Add schemata support

Commit-ID: 8205a078ba7819c23558e31af4b3bda04d9b3bae Gitweb: https://git.kernel.org/tip/8205a078ba7819c23558e31af4b3bda04d9b3bae Author: Vikas Shivappa AuthorDate: Fri, 20 Apr 2018 15:36:19 -0700 Committer: Thomas Gleixner CommitDate: Sat, 19 May 2018 13:16:44 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/mba_sc: Enable/disable MBA software controller

Commit-ID: 19c635ab24a1e94a759e82bfb34554a6a0db215e Gitweb: https://git.kernel.org/tip/19c635ab24a1e94a759e82bfb34554a6a0db215e Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Fri, 20 Apr 2018 15:36:17 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mba_sc: Enable/disable MBA software controller

Commit-ID: 19c635ab24a1e94a759e82bfb34554a6a0db215e Gitweb: https://git.kernel.org/tip/19c635ab24a1e94a759e82bfb34554a6a0db215e Author: Vikas Shivappa AuthorDate: Fri, 20 Apr 2018 15:36:17 -0700 Committer: Thomas Gleixner CommitDate: Sat, 19 May 2018 13:16:43 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/mba_sc: Documentation for MBA software controller(mba_sc)

Commit-ID: d6c64a4f49fdea0ae79addc3282ae8eb8581bdfc Gitweb: https://git.kernel.org/tip/d6c64a4f49fdea0ae79addc3282ae8eb8581bdfc Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Fri, 20 Apr 2018 15:36:16 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mba_sc: Documentation for MBA software controller(mba_sc)

Commit-ID: d6c64a4f49fdea0ae79addc3282ae8eb8581bdfc Gitweb: https://git.kernel.org/tip/d6c64a4f49fdea0ae79addc3282ae8eb8581bdfc Author: Vikas Shivappa AuthorDate: Fri, 20 Apr 2018 15:36:16 -0700 Committer: Thomas Gleixner CommitDate: Sat, 19 May 2018 13:16:42 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/mba_sc: Add initialization support

Commit-ID: 1bd2a63b4f0deefe745aa0fd969c07b2eb9ee99e Gitweb: https://git.kernel.org/tip/1bd2a63b4f0deefe745aa0fd969c07b2eb9ee99e Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Fri, 20 Apr 2018 15:36:18 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mba_sc: Add initialization support

Commit-ID: 1bd2a63b4f0deefe745aa0fd969c07b2eb9ee99e Gitweb: https://git.kernel.org/tip/1bd2a63b4f0deefe745aa0fd969c07b2eb9ee99e Author: Vikas Shivappa AuthorDate: Fri, 20 Apr 2018 15:36:18 -0700 Committer: Thomas Gleixner CommitDate: Sat, 19 May 2018 13:16:43 +0200 x86/intel_rdt

[PATCH 3/6] x86/intel_rdt/mba_sc: Add initialization support

lot of factors like QPI link, number of memory channels, memory channel frequency, its width and memory speed, how many channels are configured and also if memory interleaving is enabled. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu

[PATCH 3/6] x86/intel_rdt/mba_sc: Add initialization support

lot of factors like QPI link, number of memory channels, memory channel frequency, its width and memory speed, how many channels are configured and also if memory interleaving is enabled. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.c | 37 ++

[PATCH 5/6] x86/intel_rdt/mba_sc: Prepare for feedback loop

l only be used by the feedback loop patch. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu/intel_rdt.h | 10 arch/x86/kernel/cpu/intel_rdt_monitor.c | 45 - 2 files changed, 49 insertions(+), 6 deletions(

[PATCH 2/6] x86/intel_rdt/mba_sc: Enable/disable MBA software controller

pl2][mba_MBps]] /sys/fs/resctrl Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu/intel_rdt.c | 8 arch/x86/kernel/cpu/intel_rdt.h | 3 +++ arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 30 ++ 3 fi

[PATCH V2 0/6] Memory bandwidth allocation software controller(mba_sc)

value when mounted is max_u32. $ echo "L3:0=3;1=c\nMB:0=1024;1=500" > /sys/fs/resctrl/p0/schemata $ echo "L3:0=3;1=3\nMB:0=1024;1=500" > /sys/fs/resctrl/p1/schemata In the above example the tasks in "p1" and "p0" rdtgroup would use a max bandwidth of 1024MBp

[PATCH V2 0/6] Memory bandwidth allocation software controller(mba_sc)

value when mounted is max_u32. $ echo "L3:0=3;1=c\nMB:0=1024;1=500" > /sys/fs/resctrl/p0/schemata $ echo "L3:0=3;1=3\nMB:0=1024;1=500" > /sys/fs/resctrl/p1/schemata In the above example the tasks in "p1" and "p0" rdtgroup would use a max bandwidth of 1024MBp

[PATCH 5/6] x86/intel_rdt/mba_sc: Prepare for feedback loop

l only be used by the feedback loop patch. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.h | 10 arch/x86/kernel/cpu/intel_rdt_monitor.c | 45 - 2 files changed, 49 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu

[PATCH 2/6] x86/intel_rdt/mba_sc: Enable/disable MBA software controller

pl2][mba_MBps]] /sys/fs/resctrl Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.c | 8 arch/x86/kernel/cpu/intel_rdt.h | 3 +++ arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 30 ++ 3 files changed, 41 insertions(+) diff --git a

[PATCH 4/6] x86/intel_rdt/mba_sc: Add schemata support

d of being specified in percentage. We do not write the IA32_MBA_THRTL_MSRs when the schemata is updated as that is handled separately. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu/intel_rdt.c | 2 +- arch/x86/kernel/cpu/intel_rdt_ct

[PATCH 4/6] x86/intel_rdt/mba_sc: Add schemata support

d of being specified in percentage. We do not write the IA32_MBA_THRTL_MSRs when the schemata is updated as that is handled separately. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.c | 2 +- arch/x86/kernel/cpu/intel_rdt_ctrlmondata.c | 24 +++- 2 fil

[PATCH 1/6] x86/intel_rdt/mba_sc: Documentation for MBA software controller(mba_sc)

Add documentation about the feedback loop mechanism (MBA software controller) which lets the user specify the memory bandwidth allocation in MBps. This includes some changes to "schemata" formati with examples. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- D

[PATCH 1/6] x86/intel_rdt/mba_sc: Documentation for MBA software controller(mba_sc)

Add documentation about the feedback loop mechanism (MBA software controller) which lets the user specify the memory bandwidth allocation in MBps. This includes some changes to "schemata" formati with examples. Signed-off-by: Vikas Shivappa --- Documentation/x86/intel_rdt_u

[PATCH 6/6] x86/intel_rdt/mba_sc: Feedback loop to dynamically update mem bandwidth

nitial phases -> mba_sc kicks in and reduced bandwidth percentage values -> but after some it has mostly "L2 <-> L3" traffic. In this scenario mba_sc increases the bandwidth percentage when there is lesser memory traffic. Signed-off-by: Vikas Shivappa <vikas.shiva...

[PATCH 6/6] x86/intel_rdt/mba_sc: Feedback loop to dynamically update mem bandwidth

nitial phases -> mba_sc kicks in and reduced bandwidth percentage values -> but after some it has mostly "L2 <-> L3" traffic. In this scenario mba_sc increases the bandwidth percentage when there is lesser memory traffic. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cp

[PATCH 3/6] x86/intel_rdt/mba_sc: Add initialization support

When MBA software controller is enabled, we need a per domain storage for user specified bandwidth in MB and the raw b/w percentage values which are programmed into the MSR. Add support for these data structures and initialization. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.

[PATCH 3/6] x86/intel_rdt/mba_sc: Add initialization support

When MBA software controller is enabled, we need a per domain storage for user specified bandwidth in MB and the raw b/w percentage values which are programmed into the MSR. Add support for these data structures and initialization. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu

[PATCH 4/6] x86/intel_rdt/mba_sc: Add schemata support

in percentage values. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu/intel_rdt.c | 10 +- arch/x86/kernel/cpu/intel_rdt_ctrlmondata.c | 10 -- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/int

[PATCH 4/6] x86/intel_rdt/mba_sc: Add schemata support

in percentage values. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.c | 10 +- arch/x86/kernel/cpu/intel_rdt_ctrlmondata.c | 10 -- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/inte

[PATCH 5/6] x86/intel_rdt/mba_sc: Add counting for MBA software controller

d the delta b/w when the b/w MSR values change. We do this by taking the time stamp every time a the counter is read and then keeping a history of b/w. This will be used to support internal queries for the bandwidth in Megabytes. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com>

[PATCH 5/6] x86/intel_rdt/mba_sc: Add counting for MBA software controller

d the delta b/w when the b/w MSR values change. We do this by taking the time stamp every time a the counter is read and then keeping a history of b/w. This will be used to support internal queries for the bandwidth in Megabytes. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.c

[PATCH RFC 0/6] Memory b/w allocation software controller

1024;1=500" > /sys/fs/resctrl/p1/schemata In the above example the tasks in "p1" and "p0" rdtgroup would use a max b/w of 1024MBps on socket0 and 500MBps on socket1. Vikas Shivappa (6): x86/intel_rdt/mba_sc: Add documentation for MBA software controller x86/intel_r

[PATCH 6/6] x86/intel_rdt/mba_sc: Add support to dynamically update the memory b/w

alues written to the MSR are also cached so that we donot do a rdmsr for every 1s. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu/intel_rdt.c | 2 +- arch/x86/kernel/cpu/intel_rdt.h | 1 + arch/x86/kernel/cpu/intel_rdt_monitor.c | 71 +++

[PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

Add documentation about usage which includes the "schemata" format and use case for MBA software controller. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- Documentation/x86/intel_rdt_ui.txt | 63 ++ 1 file changed, 63 ins

[PATCH RFC 0/6] Memory b/w allocation software controller

1024;1=500" > /sys/fs/resctrl/p1/schemata In the above example the tasks in "p1" and "p0" rdtgroup would use a max b/w of 1024MBps on socket0 and 500MBps on socket1. Vikas Shivappa (6): x86/intel_rdt/mba_sc: Add documentation for MBA software controller x86/intel_r

[PATCH 6/6] x86/intel_rdt/mba_sc: Add support to dynamically update the memory b/w

alues written to the MSR are also cached so that we donot do a rdmsr for every 1s. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.c | 2 +- arch/x86/kernel/cpu/intel_rdt.h | 1 + arch/x86/kernel/cpu/intel_rdt_monitor.c | 71 +++-- 3 f

[PATCH 1/6] x86/intel_rdt/mba_sc: Add documentation for MBA software controller

Add documentation about usage which includes the "schemata" format and use case for MBA software controller. Signed-off-by: Vikas Shivappa --- Documentation/x86/intel_rdt_ui.txt | 63 ++ 1 file changed, 63 insertions(+) diff --git a/Documen

[PATCH 2/6] x86/intel_rdt/mba_sc: Add support to enable/disable via mount option

Specify a new mount option "mba_MB" to enable the user to specify MBA bandwidth in Megabytes(Software Controller/SC) instead of b/w percentage: $mount -t resctrl resctrl [-o cdp[,cdpl2][mba_MB]] /sys/fs/resctrl Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> ---

[PATCH 2/6] x86/intel_rdt/mba_sc: Add support to enable/disable via mount option

Specify a new mount option "mba_MB" to enable the user to specify MBA bandwidth in Megabytes(Software Controller/SC) instead of b/w percentage: $mount -t resctrl resctrl [-o cdp[,cdpl2][mba_MB]] /sys/fs/resctrl Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.h

[tip:x86/cache] x86/intel_rdt/cqm: Improve limbo list processing

Commit-ID: 24247aeeabe99eab13b798c2dec066dd6f07 Gitweb: http://git.kernel.org/tip/24247aeeabe99eab13b798c2dec066dd6f07 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 15 Aug 2017 18:00:43 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Improve limbo list processing

Commit-ID: 24247aeeabe99eab13b798c2dec066dd6f07 Gitweb: http://git.kernel.org/tip/24247aeeabe99eab13b798c2dec066dd6f07 Author: Vikas Shivappa AuthorDate: Tue, 15 Aug 2017 18:00:43 -0700 Committer: Thomas Gleixner CommitDate: Wed, 16 Aug 2017 12:05:41 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt/mbm: Fix MBM overflow handler during CPU hotplug

Commit-ID: bbc4615e0b7df5e21d0991adb4b2798508354924 Gitweb: http://git.kernel.org/tip/bbc4615e0b7df5e21d0991adb4b2798508354924 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 15 Aug 2017 18:00:42 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mbm: Fix MBM overflow handler during CPU hotplug

Commit-ID: bbc4615e0b7df5e21d0991adb4b2798508354924 Gitweb: http://git.kernel.org/tip/bbc4615e0b7df5e21d0991adb4b2798508354924 Author: Vikas Shivappa AuthorDate: Tue, 15 Aug 2017 18:00:42 -0700 Committer: Thomas Gleixner CommitDate: Wed, 16 Aug 2017 12:05:41 +0200 x86/intel_rdt/mbm

[PATCH 1/2] x86/intel_rdt/mbm: Fix MBM overflow handler during hot cpu

immediately on a different cpu in same domain. We donot flush the worker because the MBM overflow worker reschedules the worker on same CPU and scans the domain->cpu_mask to get the domain pointer. Reported-by: Thomas Gleixner <t...@linutronix.de> Signed-off-by: Vikas Shivappa <

[PATCH 1/2] x86/intel_rdt/mbm: Fix MBM overflow handler during hot cpu

immediately on a different cpu in same domain. We donot flush the worker because the MBM overflow worker reschedules the worker on same CPU and scans the domain->cpu_mask to get the domain pointer. Reported-by: Thomas Gleixner Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rd

[PATCH 0/2 V4] Cqm3 support based on resctrl along with MBM

the rmid->busy correctly in case of domain going offline and to use the correct work_cpu. Vikas Shivappa (2): x86/intel_rdt/mbm: Fix MBM overflow handler during hot cpu x86/intel_rdt/cqm: Improve limbo list processing arch/x86/kernel/cpu/intel_rdt.c | 34 - arch/x86/kernel/

[PATCH 0/2 V4] Cqm3 support based on resctrl along with MBM

the rmid->busy correctly in case of domain going offline and to use the correct work_cpu. Vikas Shivappa (2): x86/intel_rdt/mbm: Fix MBM overflow handler during hot cpu x86/intel_rdt/cqm: Improve limbo list processing arch/x86/kernel/cpu/intel_rdt.c | 34 - arch/x86/kernel/

[PATCH 2/2] x86/intel_rdt/cqm: Improve limbo list processing

ist is empty or would return -EBUSY if there are RMIDs on limbo but not on free list. As a side effect of not accessing the limbo list in parallel on IPIs we simplify some of the related data structures. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu/in

[PATCH 2/2] x86/intel_rdt/cqm: Improve limbo list processing

ist is empty or would return -EBUSY if there are RMIDs on limbo but not on free list. As a side effect of not accessing the limbo list in parallel on IPIs we simplify some of the related data structures. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.c | 32 - arch/

[tip:x86/cache] x86/intel_rdt: Modify the intel_pqr_state for better performance

Commit-ID: a9110b552d44fedbd1221eb0e5bde81da32d9350 Gitweb: http://git.kernel.org/tip/a9110b552d44fedbd1221eb0e5bde81da32d9350 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Wed, 9 Aug 2017 11:46:34 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt: Modify the intel_pqr_state for better performance

Commit-ID: a9110b552d44fedbd1221eb0e5bde81da32d9350 Gitweb: http://git.kernel.org/tip/a9110b552d44fedbd1221eb0e5bde81da32d9350 Author: Vikas Shivappa AuthorDate: Wed, 9 Aug 2017 11:46:34 -0700 Committer: Thomas Gleixner CommitDate: Mon, 14 Aug 2017 11:47:47 +0200 x86/intel_rdt: Modify

[tip:x86/cache] x86/intel_rdt/cqm: Clear the default RMID during hotcpu

Commit-ID: eda61c265f3656be8345fdf0334b3a77829437fc Gitweb: http://git.kernel.org/tip/eda61c265f3656be8345fdf0334b3a77829437fc Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Wed, 9 Aug 2017 11:46:33 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Clear the default RMID during hotcpu

Commit-ID: eda61c265f3656be8345fdf0334b3a77829437fc Gitweb: http://git.kernel.org/tip/eda61c265f3656be8345fdf0334b3a77829437fc Author: Vikas Shivappa AuthorDate: Wed, 9 Aug 2017 11:46:33 -0700 Committer: Thomas Gleixner CommitDate: Mon, 14 Aug 2017 11:47:46 +0200 x86/intel_rdt/cqm

[PATCH 2/3] x86/intel_rdt: Modify the intel_pqr_state for better performance

t;t...@linutronix.de> Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/include/asm/intel_rdt_sched.h | 30 +- arch/x86/kernel/cpu/intel_rdt.c | 10 -- arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 10 +- 3 files

[PATCH 2/3] x86/intel_rdt: Modify the intel_pqr_state for better performance

-by: Vikas Shivappa --- arch/x86/include/asm/intel_rdt_sched.h | 30 +- arch/x86/kernel/cpu/intel_rdt.c | 10 -- arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 10 +- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/arch/x86

[PATCH 3/3] x86/intel_rdt/cqm: Improve limbo list processing

ist is empty or would return -EBUSY if there are RMIDs on limbo but not on free list. As a side effect of not accessing the limbo list in parallel on IPIs we simplify some of the related data structures. Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu/in

[PATCH 3/3] x86/intel_rdt/cqm: Improve limbo list processing

ist is empty or would return -EBUSY if there are RMIDs on limbo but not on free list. As a side effect of not accessing the limbo list in parallel on IPIs we simplify some of the related data structures. Signed-off-by: Vikas Shivappa --- arch/x86/kernel/cpu/intel_rdt.c | 25 +++- arch/x86/ker

[PATCH 0/3 V3] Cqm3 based on resctrl fs with MBM support

/cache (where the V2 was merged) Vikas Shivappa (3): x86/intel_rdt/cqm: Add fix to clear the default RMID during hotcpu x86/intel_rdt: Modify the intel_pqr_state for better performance x86/intel_rdt/cqm: Improve limbo list processing arch/x86/include/asm/intel_rdt_sched.h | 30 +++-- arch/x86

[PATCH 0/3 V3] Cqm3 based on resctrl fs with MBM support

/cache (where the V2 was merged) Vikas Shivappa (3): x86/intel_rdt/cqm: Add fix to clear the default RMID during hotcpu x86/intel_rdt: Modify the intel_pqr_state for better performance x86/intel_rdt/cqm: Improve limbo list processing arch/x86/include/asm/intel_rdt_sched.h | 30 +++-- arch/x86

[PATCH 1/3] x86/intel_rdt/cqm: Add fix to clear the default RMID during hotcpu

rak...@intel.com> Signed-off-by: Vikas Shivappa <vikas.shiva...@linux.intel.com> --- arch/x86/kernel/cpu/intel_rdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c index da4f389..4b9edb2 100644 --- a/arch/x86/kernel/cpu

[PATCH 1/3] x86/intel_rdt/cqm: Add fix to clear the default RMID during hotcpu

The user configured per cpu default RMID is not cleared during cpu hotplug. This may lead to incorrect RMID values after a cpu goes offline and again comes back online. Clear the per cpu default RMID during cpu offline and online handling. Reported-by: Prakyha Sai Praneeth Signed-off-by: Vikas

[tip:x86/cache] x86/intel_rdt/mbm: Handle counter overflow

Commit-ID: e33026831bdb5f051499fec6a606f79fe1f94cc8 Gitweb: http://git.kernel.org/tip/e33026831bdb5f051499fec6a606f79fe1f94cc8 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:47 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mbm: Handle counter overflow

Commit-ID: e33026831bdb5f051499fec6a606f79fe1f94cc8 Gitweb: http://git.kernel.org/tip/e33026831bdb5f051499fec6a606f79fe1f94cc8 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:47 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:29 +0200 x86/intel_rdt/mbm

[tip:x86/cache] x86/intel_rdt/mbm: Add mbm counter initialization

Commit-ID: a4de1dfdd726537e2a78b55759fc646d9b0a0be8 Gitweb: http://git.kernel.org/tip/a4de1dfdd726537e2a78b55759fc646d9b0a0be8 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:46 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/mbm: Add mbm counter initialization

Commit-ID: a4de1dfdd726537e2a78b55759fc646d9b0a0be8 Gitweb: http://git.kernel.org/tip/a4de1dfdd726537e2a78b55759fc646d9b0a0be8 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:46 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:29 +0200 x86/intel_rdt/mbm

[tip:x86/cache] x86/intel_rdt/cqm: Add CPU hotplug support

Commit-ID: 895c663ecef16c8138e20a7d5c052e0fcc400241 Gitweb: http://git.kernel.org/tip/895c663ecef16c8138e20a7d5c052e0fcc400241 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:44 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add CPU hotplug support

Commit-ID: 895c663ecef16c8138e20a7d5c052e0fcc400241 Gitweb: http://git.kernel.org/tip/895c663ecef16c8138e20a7d5c052e0fcc400241 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:44 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:28 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt/cqm: Add rmdir support

Commit-ID: f3cbeacaa06e2b8c2f3ce8531e9aa3fe1f2762cd Gitweb: http://git.kernel.org/tip/f3cbeacaa06e2b8c2f3ce8531e9aa3fe1f2762cd Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:40 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add mount,umount support

Commit-ID: 4af4a88e0c9246990f95c88eeba781265f27c58e Gitweb: http://git.kernel.org/tip/4af4a88e0c9246990f95c88eeba781265f27c58e Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:41 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add rmdir support

Commit-ID: f3cbeacaa06e2b8c2f3ce8531e9aa3fe1f2762cd Gitweb: http://git.kernel.org/tip/f3cbeacaa06e2b8c2f3ce8531e9aa3fe1f2762cd Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:40 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:27 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt/cqm: Add mount,umount support

Commit-ID: 4af4a88e0c9246990f95c88eeba781265f27c58e Gitweb: http://git.kernel.org/tip/4af4a88e0c9246990f95c88eeba781265f27c58e Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:41 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:27 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt/cqm: Add sched_in support

Commit-ID: 748b6b881ccdda8f0663c68605f431279e06f49a Gitweb: http://git.kernel.org/tip/748b6b881ccdda8f0663c68605f431279e06f49a Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:43 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add sched_in support

Commit-ID: 748b6b881ccdda8f0663c68605f431279e06f49a Gitweb: http://git.kernel.org/tip/748b6b881ccdda8f0663c68605f431279e06f49a Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:43 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:28 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt: Introduce rdt_enable_key for scheduling

Commit-ID: 4be6c078428b08d1a948cc09faca8f1326231866 Gitweb: http://git.kernel.org/tip/4be6c078428b08d1a948cc09faca8f1326231866 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:42 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt: Introduce rdt_enable_key for scheduling

Commit-ID: 4be6c078428b08d1a948cc09faca8f1326231866 Gitweb: http://git.kernel.org/tip/4be6c078428b08d1a948cc09faca8f1326231866 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:42 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:27 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt: Separate the ctrl bits from rmdir

Commit-ID: f9049547f7e72377049d717354b2f56f36a5854a Gitweb: http://git.kernel.org/tip/f9049547f7e72377049d717354b2f56f36a5854a Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:39 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt: Separate the ctrl bits from rmdir

Commit-ID: f9049547f7e72377049d717354b2f56f36a5854a Gitweb: http://git.kernel.org/tip/f9049547f7e72377049d717354b2f56f36a5854a Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:39 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:26 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/cqm: Add mon_data

Commit-ID: d89b7379015fc561060a4094676d143e6ed264e7 Gitweb: http://git.kernel.org/tip/d89b7379015fc561060a4094676d143e6ed264e7 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:38 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add mon_data

Commit-ID: d89b7379015fc561060a4094676d143e6ed264e7 Gitweb: http://git.kernel.org/tip/d89b7379015fc561060a4094676d143e6ed264e7 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:38 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:26 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt: Prepare for RDT monitor data support

Commit-ID: 90c403e83101c87ee9e6df8c8d30ea8628ff8bfc Gitweb: http://git.kernel.org/tip/90c403e83101c87ee9e6df8c8d30ea8628ff8bfc Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:37 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt: Prepare for RDT monitor data support

Commit-ID: 90c403e83101c87ee9e6df8c8d30ea8628ff8bfc Gitweb: http://git.kernel.org/tip/90c403e83101c87ee9e6df8c8d30ea8628ff8bfc Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:37 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:25 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/cqm: Add cpus file support

Commit-ID: a9fcf8627dc01049c390023bbb0323db3c785b91 Gitweb: http://git.kernel.org/tip/a9fcf8627dc01049c390023bbb0323db3c785b91 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:36 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add cpus file support

Commit-ID: a9fcf8627dc01049c390023bbb0323db3c785b91 Gitweb: http://git.kernel.org/tip/a9fcf8627dc01049c390023bbb0323db3c785b91 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:36 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:25 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt: Change closid type from int to u32

Commit-ID: 0734ded1abee9439b0c5d7b62af1ead78aab895b Gitweb: http://git.kernel.org/tip/0734ded1abee9439b0c5d7b62af1ead78aab895b Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:33 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt: Prepare to add RDT monitor cpus file support

Commit-ID: b09d981b3f346690dafa3e4ebedfcf3e44b68e83 Gitweb: http://git.kernel.org/tip/b09d981b3f346690dafa3e4ebedfcf3e44b68e83 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:35 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt: Change closid type from int to u32

Commit-ID: 0734ded1abee9439b0c5d7b62af1ead78aab895b Gitweb: http://git.kernel.org/tip/0734ded1abee9439b0c5d7b62af1ead78aab895b Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:33 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:24 +0200 x86/intel_rdt: Change

[tip:x86/cache] x86/intel_rdt: Prepare to add RDT monitor cpus file support

Commit-ID: b09d981b3f346690dafa3e4ebedfcf3e44b68e83 Gitweb: http://git.kernel.org/tip/b09d981b3f346690dafa3e4ebedfcf3e44b68e83 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:35 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:25 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/cqm: Add tasks file support

Commit-ID: d6aaba615a482ce7d3ec218cf7b8d02d0d5753b8 Gitweb: http://git.kernel.org/tip/d6aaba615a482ce7d3ec218cf7b8d02d0d5753b8 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:34 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add tasks file support

Commit-ID: d6aaba615a482ce7d3ec218cf7b8d02d0d5753b8 Gitweb: http://git.kernel.org/tip/d6aaba615a482ce7d3ec218cf7b8d02d0d5753b8 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:34 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:24 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt/cqm: Add info files for RDT monitoring

Commit-ID: d4ab33201029913b594ae785a9665f45040396ab Gitweb: http://git.kernel.org/tip/d4ab33201029913b594ae785a9665f45040396ab Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:30 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add info files for RDT monitoring

Commit-ID: d4ab33201029913b594ae785a9665f45040396ab Gitweb: http://git.kernel.org/tip/d4ab33201029913b594ae785a9665f45040396ab Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:30 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:22 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt/cqm: Add mkdir support for RDT monitoring

Commit-ID: c7d9aac6131148abe29ed1dc6bd73ad1213d1f56 Gitweb: http://git.kernel.org/tip/c7d9aac6131148abe29ed1dc6bd73ad1213d1f56 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:32 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add mkdir support for RDT monitoring

Commit-ID: c7d9aac6131148abe29ed1dc6bd73ad1213d1f56 Gitweb: http://git.kernel.org/tip/c7d9aac6131148abe29ed1dc6bd73ad1213d1f56 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:32 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:23 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt/cqm: Add RMID (Resource monitoring ID) management

Commit-ID: edf6fa1c4a951b3a03e94b63e6483c5d9da3ab11 Gitweb: http://git.kernel.org/tip/edf6fa1c4a951b3a03e94b63e6483c5d9da3ab11 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:28 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt: Prepare for RDT monitoring mkdir support

Commit-ID: 65b4f403057e32da73c36e33d403890173c4c324 Gitweb: http://git.kernel.org/tip/65b4f403057e32da73c36e33d403890173c4c324 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:31 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add RMID (Resource monitoring ID) management

Commit-ID: edf6fa1c4a951b3a03e94b63e6483c5d9da3ab11 Gitweb: http://git.kernel.org/tip/edf6fa1c4a951b3a03e94b63e6483c5d9da3ab11 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:28 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:21 +0200 x86/intel_rdt/cqm

[tip:x86/cache] x86/intel_rdt: Prepare for RDT monitoring mkdir support

Commit-ID: 65b4f403057e32da73c36e33d403890173c4c324 Gitweb: http://git.kernel.org/tip/65b4f403057e32da73c36e33d403890173c4c324 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:31 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:23 +0200 x86/intel_rdt

[tip:x86/cache] x86/intel_rdt/cqm: Add RDT monitoring initialization

Commit-ID: 6a445edce657810992594c7b9e679219aaf78ad9 Gitweb: http://git.kernel.org/tip/6a445edce657810992594c7b9e679219aaf78ad9 Author: Vikas Shivappa <vikas.shiva...@linux.intel.com> AuthorDate: Tue, 25 Jul 2017 14:14:27 -0700 Committer: Thomas Gleixner <t...@linutronix.de>

[tip:x86/cache] x86/intel_rdt/cqm: Add RDT monitoring initialization

Commit-ID: 6a445edce657810992594c7b9e679219aaf78ad9 Gitweb: http://git.kernel.org/tip/6a445edce657810992594c7b9e679219aaf78ad9 Author: Vikas Shivappa AuthorDate: Tue, 25 Jul 2017 14:14:27 -0700 Committer: Thomas Gleixner CommitDate: Tue, 1 Aug 2017 22:41:21 +0200 x86/intel_rdt/cqm

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