Re: [net-next PATCH 0/8] configuration support for switch headers & phy

On Thu, Mar 25, 2021 at 6:51 PM Andrew Lunn wrote: > > On Thu, Mar 25, 2021 at 06:32:12PM +0530, Sunil Kovvuri wrote: > > On Thu, Mar 25, 2021 at 6:20 PM Andrew Lunn wrote: > > > > > > > > So you completely skipped how this works with mv88e6xxx or > >

Re: [net-next PATCH 0/8] configuration support for switch headers & phy

On Thu, Mar 25, 2021 at 6:20 PM Andrew Lunn wrote: > > > > So you completely skipped how this works with mv88e6xxx or > > > prestera. If you need this private flag for some out of mainline > > > Marvell SDK, it is very unlikely to be accepted. > > > > > > Andrew > > > > What we are trying

Re: [net-next PATCH 0/8] configuration support for switch headers & phy

> > > Hi Hariprasad > > > > > > Private flags sound very wrong here. I would expect to see some > > > integration > > > between the switchdev/DSA driver and the MAC driver. > > > Please show how this works in combination with drivers/net/dsa/mv88e6xxx > > > or

Re: [PATCH net-next] octeontx2: fix -Wnonnull warning

On Tue, Mar 23, 2021 at 6:26 PM Arnd Bergmann wrote: > > From: Arnd Bergmann > > When compile testing this driver on a platform on which probe() is > known to fail at compile time, gcc warns about the cgx_lmactype_string[] > array being uninitialized: > > In function 'strncpy', > inlined

Re: [PATCH] octeontx2-af: Fix memory leak of object buf

On Tue, Mar 23, 2021 at 6:07 PM Colin King wrote: > > From: Colin Ian King > > Currently the error return path when lfs fails to allocate is not free'ing > the memory allocated to buf. Fix this by adding the missing kfree. > > Addresses-Coverity: ("Resource leak") > Fixes: f7884097141b

Re: [net-next PATCH] octeontx2-af: cn10k: Fixes CN10K RPM reference issue

On Mon, Feb 15, 2021 at 11:27 PM Geetha sowjanya wrote: > > This patch fixes references to uninitialized variables and > debugfs entry name for CN10K platform and HW_TSO flag check. > > Signed-off-by: Geetha sowjanya > Signed-off-by: Sunil Goutham > > This patch fixes the bug introduced by the

Re: [PATCH] octeontx2-af: fix memory leak of lmac and lmac->name

On Thu, Jan 7, 2021 at 6:11 PM Colin King wrote: > > From: Colin Ian King > > Currently the error return paths don't kfree lmac and lmac->name > leading to some memory leaks. Fix this by adding two error return > paths that kfree these objects > > Addresses-Coverity: ("Resource leak") > Fixes:

Re: [PATCH net-next] octeontx2-af: debugfs: delete dead code

On Wed, Dec 2, 2020 at 12:28 PM Dan Carpenter wrote: > > These debugfs never return NULL so all this code will never be run. > > In the normal case, (and in this case particularly), the debugfs > functions are not supposed to be checked for errors so all this error > checking code can be safely

Re: [PATCH v2 net-next 3/3] octeontx2-af: Add devlink health reporters for NIX

On Sat, Nov 7, 2020 at 2:28 AM Saeed Mahameed wrote: > > On Fri, 2020-11-06 at 00:59 +0530, Sunil Kovvuri wrote: > > > > > > Output: > > > > > > # ./devlink health > > > > > > pci/0002:01:00.0: > > > > > >reporte

Re: [PATCH v2 net-next 3/3] octeontx2-af: Add devlink health reporters for NIX

> > > > Output: > > > > # ./devlink health > > > > pci/0002:01:00.0: > > > >reporter npa > > > > state healthy error 0 recover 0 > > > >reporter nix > > > > state healthy error 0 recover 0 > > > > # ./devlink health dump show pci/0002:01:00.0 reporter nix > > > >

Re: [PATCH v3 00/15] soc: octeontx2: Add RVU admin function driver

On Tue, Sep 11, 2018 at 7:07 PM Arnd Bergmann wrote: > > On Tue, Sep 11, 2018 at 2:37 PM Sunil Kovvuri wrote: > > > > Didn't receive any feedback for the v3 patch series over a week's time. > > Can you please pick up these patches to merge into arm-soc ? > > I would

Re: [PATCH v3 00/15] soc: octeontx2: Add RVU admin function driver

On Tue, Sep 11, 2018 at 7:07 PM Arnd Bergmann wrote: > > On Tue, Sep 11, 2018 at 2:37 PM Sunil Kovvuri wrote: > > > > Didn't receive any feedback for the v3 patch series over a week's time. > > Can you please pick up these patches to merge into arm-soc ? > > I would

Re: [PATCH v2 00/15] soc: octeontx2: Add RVU admin function driver

On Tue, Sep 4, 2018 at 6:16 PM Andrew Lunn wrote: > > On Tue, Sep 04, 2018 at 05:24:35PM +0530, sunil.kovv...@gmail.com wrote: > > From: Sunil Goutham > > > > Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports > > multiple PCIe SRIOV physical functions (PFs) and virtual

Re: [PATCH v2 00/15] soc: octeontx2: Add RVU admin function driver

On Tue, Sep 4, 2018 at 6:16 PM Andrew Lunn wrote: > > On Tue, Sep 04, 2018 at 05:24:35PM +0530, sunil.kovv...@gmail.com wrote: > > From: Sunil Goutham > > > > Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports > > multiple PCIe SRIOV physical functions (PFs) and virtual

[PATCH v2 14/15] soc: octeontx2: Register for CGX lmac events

From: Linu Cherian Added support in RVU AF driver to register for CGX LMAC link status change events from firmware and managing them. Processing part will be added in followup patches. - Introduced eventqueue for posting events from cgx lmac. Queueing mechanism will ensure that events can be

[PATCH v2 15/15] MAINTAINERS: Add entry for Marvell OcteonTX2 Admin Function driver

From: Sunil Goutham Added maintainers entry for Marvell OcteonTX2 SOC's RVU admin function driver. Signed-off-by: Sunil Goutham --- MAINTAINERS | 10 ++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e178f2b..38f874c 100644 --- a/MAINTAINERS +++

[PATCH v2 15/15] MAINTAINERS: Add entry for Marvell OcteonTX2 Admin Function driver

From: Sunil Goutham Added maintainers entry for Marvell OcteonTX2 SOC's RVU admin function driver. Signed-off-by: Sunil Goutham --- MAINTAINERS | 10 ++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e178f2b..38f874c 100644 --- a/MAINTAINERS +++

[PATCH v2 14/15] soc: octeontx2: Register for CGX lmac events

From: Linu Cherian Added support in RVU AF driver to register for CGX LMAC link status change events from firmware and managing them. Processing part will be added in followup patches. - Introduced eventqueue for posting events from cgx lmac. Queueing mechanism will ensure that events can be

[PATCH v2 12/15] soc: octeontx2: Set RVU PFs to CGX LMACs mapping

From: Linu Cherian Each of the enabled CGX LMAC is considered a physical interface and RVU PFs are mapped to these. VFs of these SRIOV PFs will be virtual interfaces and share CGX LMAC along with PF. This mapping info will be used later on for Rx/Tx pkt steering. Signed-off-by: Linu Cherian

[PATCH v2 13/15] soc: octeontx2: Add support for CGX link management

From: Linu Cherian CGX LMAC initialization, link status polling etc is done by low level secure firmware. For link management this patch adds a interface or communication mechanism between firmware and this kernel CGX driver. - Firmware interface specification is defined in cgx_fw_if.h. -

[PATCH v2 13/15] soc: octeontx2: Add support for CGX link management

From: Linu Cherian CGX LMAC initialization, link status polling etc is done by low level secure firmware. For link management this patch adds a interface or communication mechanism between firmware and this kernel CGX driver. - Firmware interface specification is defined in cgx_fw_if.h. -

[PATCH v2 12/15] soc: octeontx2: Set RVU PFs to CGX LMACs mapping

From: Linu Cherian Each of the enabled CGX LMAC is considered a physical interface and RVU PFs are mapped to these. VFs of these SRIOV PFs will be virtual interfaces and share CGX LMAC along with PF. This mapping info will be used later on for Rx/Tx pkt steering. Signed-off-by: Linu Cherian

[PATCH v2 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

From: Sunil Goutham This patch adds basic template for Marvell OcteonTX2's CGX ethernet interface driver. Just the probe. RVU AF driver will use APIs exported by this driver for various things like PF to physical interface mapping, loopback mode, interface stats etc. Hence marged both drivers

[PATCH v2 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

From: Sunil Goutham This patch adds basic template for Marvell OcteonTX2's CGX ethernet interface driver. Just the probe. RVU AF driver will use APIs exported by this driver for various things like PF to physical interface mapping, loopback mode, interface stats etc. Hence marged both drivers

[PATCH v2 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

From: Geetha sowjanya HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence create a IOMMU mapping for the physcial address configured by firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. Signed-off-by: Geetha sowjanya Signed-off-by: Sunil Goutham ---

[PATCH v2 09/15] soc: octeontx2: Configure block LF's MSIX vector offset

From: Sunil Goutham Firmware configures a certain number of MSIX vectors to each of enabled RVU PF/VF. When a block LF is attached to a PF/VF, number of MSIX vectors needed by that LF are set aside (out of PF/VF's total MSIX vectors) and LF's msix_offset is configured in HW. Also added support

[PATCH v2 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

From: Geetha sowjanya HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence create a IOMMU mapping for the physcial address configured by firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. Signed-off-by: Geetha sowjanya Signed-off-by: Sunil Goutham ---

[PATCH v2 09/15] soc: octeontx2: Configure block LF's MSIX vector offset

From: Sunil Goutham Firmware configures a certain number of MSIX vectors to each of enabled RVU PF/VF. When a block LF is attached to a PF/VF, number of MSIX vectors needed by that LF are set aside (out of PF/VF's total MSIX vectors) and LF's msix_offset is configured in HW. Also added support

[PATCH v2 08/15] soc: octeontx2: Add RVU block LF provisioning support

From: Sunil Goutham Added support for a RVU PF/VF to request AF via mailbox to attach or detach NPA/NIX/SSO/SSOW/TIM/CPT block LFs. Also supports partial detachment and modifying current LF attached count of a certian block type. Signed-off-by: Sunil Goutham ---

[PATCH v2 08/15] soc: octeontx2: Add RVU block LF provisioning support

From: Sunil Goutham Added support for a RVU PF/VF to request AF via mailbox to attach or detach NPA/NIX/SSO/SSOW/TIM/CPT block LFs. Also supports partial detachment and modifying current LF attached count of a certian block type. Signed-off-by: Sunil Goutham ---

[PATCH v2 00/15] soc: octeontx2: Add RVU admin function driver

From: Sunil Goutham Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs). PF0 is called administrative / admin function (AF) and has privilege access to registers to provision different RVU functional

[PATCH v2 06/15] soc: octeontx2: Convert mbox msg id check to a macro

From: Aleksey Makarov With 10's of mailbox messages expected to be handled in future, checking for message id could become a lengthy switch case. Hence added a macro to auto generate the switch case for each msg id. Signed-off-by: Aleksey Makarov --- drivers/soc/marvell/octeontx2/rvu.c | 44

[PATCH v2 02/15] soc: octeontx2: Reset all RVU blocks

From: Sunil Goutham Go through all BLKADDRs and check which ones are implemented on this silicon and do a HW reset of each implemented block. Also added all RVU AF and PF register offsets. Signed-off-by: Sunil Goutham --- drivers/soc/marvell/octeontx2/rvu.c| 78

[PATCH v2 04/15] soc: octeontx2: Add mailbox support infra

From: Aleksey Makarov This patch adds mailbox support infrastructure APIs. Each RVU device has a dedicated 64KB mailbox region shared with it's peer for communication. RVU AF has a separate mailbox region shared with each of RVU PFs and a RVU PF has a separate region shared with each of it's VF.

[PATCH v2 05/15] soc: octeontx2: Add mailbox IRQ and msg handlers

From: Sunil Goutham This patch adds support for mailbox interrupt and message handling. Mapped mailbox region and registered a workqueue for message handling. Enabled mailbox IRQ of RVU PFs and registered a interrupt handler. When IRQ is triggered work is added to the mbox workqueue for msgs to

[PATCH v2 00/15] soc: octeontx2: Add RVU admin function driver

From: Sunil Goutham Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs). PF0 is called administrative / admin function (AF) and has privilege access to registers to provision different RVU functional

[PATCH v2 06/15] soc: octeontx2: Convert mbox msg id check to a macro

From: Aleksey Makarov With 10's of mailbox messages expected to be handled in future, checking for message id could become a lengthy switch case. Hence added a macro to auto generate the switch case for each msg id. Signed-off-by: Aleksey Makarov --- drivers/soc/marvell/octeontx2/rvu.c | 44

[PATCH v2 02/15] soc: octeontx2: Reset all RVU blocks

From: Sunil Goutham Go through all BLKADDRs and check which ones are implemented on this silicon and do a HW reset of each implemented block. Also added all RVU AF and PF register offsets. Signed-off-by: Sunil Goutham --- drivers/soc/marvell/octeontx2/rvu.c| 78

[PATCH v2 04/15] soc: octeontx2: Add mailbox support infra

From: Aleksey Makarov This patch adds mailbox support infrastructure APIs. Each RVU device has a dedicated 64KB mailbox region shared with it's peer for communication. RVU AF has a separate mailbox region shared with each of RVU PFs and a RVU PF has a separate region shared with each of it's VF.

[PATCH v2 05/15] soc: octeontx2: Add mailbox IRQ and msg handlers

From: Sunil Goutham This patch adds support for mailbox interrupt and message handling. Mapped mailbox region and registered a workqueue for message handling. Enabled mailbox IRQ of RVU PFs and registered a interrupt handler. When IRQ is triggered work is added to the mbox workqueue for msgs to

[PATCH v2 07/15] soc: octeontx2: Scan blocks for LFs provisioned to PF/VF

From: Sunil Goutham Scan all RVU blocks to find any 'LF to RVU PF/VF' mapping done by low level firmware. If found any, mark them as used in respective block's LF bitmap and also save mapped PF/VF's PF_FUNC info. This is done to avoid reattaching a block LF to a different RVU PF/VF.

[PATCH v2 01/15] soc: octeontx2: Add Marvell OcteonTX2 RVU AF driver

From: Sunil Goutham This patch adds basic template for Marvell OcteonTX2's resource virtualization unit (RVU) admin function (AF) driver. Just the driver registration and probe. Signed-off-by: Sunil Goutham --- drivers/soc/Kconfig| 1 + drivers/soc/Makefile

[PATCH v2 03/15] soc: octeontx2: Gather RVU blocks HW info

From: Sunil Goutham This patch gathers NPA/NIX/SSO/SSOW/TIM/CPT RVU blocks's HW info like number of LFs. Important register offsets saved for later use to avoid code duplication for each block. A bitmap is allocated for each of the blocks which later on will be used to allocate a LF for a RVU

[PATCH v2 07/15] soc: octeontx2: Scan blocks for LFs provisioned to PF/VF

From: Sunil Goutham Scan all RVU blocks to find any 'LF to RVU PF/VF' mapping done by low level firmware. If found any, mark them as used in respective block's LF bitmap and also save mapped PF/VF's PF_FUNC info. This is done to avoid reattaching a block LF to a different RVU PF/VF.

[PATCH v2 01/15] soc: octeontx2: Add Marvell OcteonTX2 RVU AF driver

From: Sunil Goutham This patch adds basic template for Marvell OcteonTX2's resource virtualization unit (RVU) admin function (AF) driver. Just the driver registration and probe. Signed-off-by: Sunil Goutham --- drivers/soc/Kconfig| 1 + drivers/soc/Makefile

[PATCH v2 03/15] soc: octeontx2: Gather RVU blocks HW info

From: Sunil Goutham This patch gathers NPA/NIX/SSO/SSOW/TIM/CPT RVU blocks's HW info like number of LFs. Important register offsets saved for later use to avoid code duplication for each block. A bitmap is allocated for each of the blocks which later on will be used to allocate a LF for a RVU

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

On Fri, Aug 31, 2018 at 11:59 PM Arnd Bergmann wrote: > > On Fri, Aug 31, 2018 at 6:01 PM Sunil Kovvuri wrote: > > On Fri, Aug 31, 2018 at 7:50 PM Arnd Bergmann wrote: > > > > > Thanks for the suggestion, that does makes sense. > > Actually i did thou

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

On Fri, Aug 31, 2018 at 11:59 PM Arnd Bergmann wrote: > > On Fri, Aug 31, 2018 at 6:01 PM Sunil Kovvuri wrote: > > On Fri, Aug 31, 2018 at 7:50 PM Arnd Bergmann wrote: > > > > > Thanks for the suggestion, that does makes sense. > > Actually i did thou

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

On Fri, Aug 31, 2018 at 7:50 PM Arnd Bergmann wrote: > > On Thu, Aug 30, 2018 at 7:55 PM Sunil Kovvuri wrote: > > On Thu, Aug 30, 2018 at 7:37 PM Arnd Bergmann wrote: > > > On Tue, Aug 28, 2018 at 3:10 PM Sunil Kovvuri > > > wrote: > > > Ok, I think I un

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

On Fri, Aug 31, 2018 at 7:50 PM Arnd Bergmann wrote: > > On Thu, Aug 30, 2018 at 7:55 PM Sunil Kovvuri wrote: > > On Thu, Aug 30, 2018 at 7:37 PM Arnd Bergmann wrote: > > > On Tue, Aug 28, 2018 at 3:10 PM Sunil Kovvuri > > > wrote: > > > Ok, I think I un

Re: [PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

On Thu, Aug 30, 2018 at 7:23 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 3:17 PM Sunil Kovvuri wrote: > > On Tue, Aug 28, 2018 at 6:27 PM Arnd Bergmann wrote: > > > On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri > > > wrote: > > > > On Tue, Au

Re: [PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

On Thu, Aug 30, 2018 at 7:23 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 3:17 PM Sunil Kovvuri wrote: > > On Tue, Aug 28, 2018 at 6:27 PM Arnd Bergmann wrote: > > > On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri > > > wrote: > > > > On Tue, Au

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

On Thu, Aug 30, 2018 at 7:37 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 3:10 PM Sunil Kovvuri wrote: > > > > > > > If this is a regular PCI ethernet driver, why do you put it into > > > > > driver/soc

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

On Thu, Aug 30, 2018 at 7:37 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 3:10 PM Sunil Kovvuri wrote: > > > > > > > If this is a regular PCI ethernet driver, why do you put it into > > > > > driver/soc

Re: [PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

On Tue, Aug 28, 2018 at 6:27 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri wrote: > > > > On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann wrote: > > > > > > On Tue, Aug 28, 2018 at 12:58 PM wrote: > > > > > > &g

Re: [PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

On Tue, Aug 28, 2018 at 6:27 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri wrote: > > > > On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann wrote: > > > > > > On Tue, Aug 28, 2018 at 12:58 PM wrote: > > > > > > &g

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

> > > If this is a regular PCI ethernet driver, why do you put it into > > > driver/soc > > > rather than drivers/net/ethernet/ ? > > > > No, this is not a ethernet driver, as mentioned in the cover letter > > this driver and AF driver doesn't > > handle any IO. There will be a separate ethernet

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

> > > If this is a regular PCI ethernet driver, why do you put it into > > > driver/soc > > > rather than drivers/net/ethernet/ ? > > > > No, this is not a ethernet driver, as mentioned in the cover letter > > this driver and AF driver doesn't > > handle any IO. There will be a separate ethernet

Re: [PATCH 04/15] soc: octeontx2: Add mailbox support infra

On Tue, Aug 28, 2018 at 5:33 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 12:57 PM wrote: > > > > From: Aleksey Makarov > > > > This patch adds mailbox support infrastructure APIs. > > Each RVU device has a dedicated 64KB mailbox region > > shared with it's peer for communication. RVU AF

Re: [PATCH 04/15] soc: octeontx2: Add mailbox support infra

On Tue, Aug 28, 2018 at 5:33 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 12:57 PM wrote: > > > > From: Aleksey Makarov > > > > This patch adds mailbox support infrastructure APIs. > > Each RVU device has a dedicated 64KB mailbox region > > shared with it's peer for communication. RVU AF

Re: [PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 12:58 PM wrote: > > > > From: Geetha sowjanya > > > > HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence > > create a IOMMU mapping for the physcial address configured by > > firmware and reconfig

Re: [PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 12:58 PM wrote: > > > > From: Geetha sowjanya > > > > HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence > > create a IOMMU mapping for the physcial address configured by > > firmware and reconfig

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

On Tue, Aug 28, 2018 at 5:40 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 12:58 PM wrote: > > > > From: Sunil Goutham > > > > This patch adds basic template for Marvell OcteonTX2's > > CGX ethernet interface driver. Just the probe. > > RVU AF driver will use APIs exported by this driver

Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

On Tue, Aug 28, 2018 at 5:40 PM Arnd Bergmann wrote: > > On Tue, Aug 28, 2018 at 12:58 PM wrote: > > > > From: Sunil Goutham > > > > This patch adds basic template for Marvell OcteonTX2's > > CGX ethernet interface driver. Just the probe. > > RVU AF driver will use APIs exported by this driver

[PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

From: Sunil Goutham This patch adds basic template for Marvell OcteonTX2's CGX ethernet interface driver. Just the probe. RVU AF driver will use APIs exported by this driver for various things like PF to physical interface mapping, loopback mode, interface stats etc. Signed-off-by: Sunil

[PATCH 12/15] soc: octeontx2: Set RVU PFs to CGX LMACs mapping

From: Linu Cherian Each of the enabled CGX LMAC is considered a physical interface and RVU PFs are mapped to these. VFs of these SRIOV PFs will be virtual interfaces and share CGX LMAC along with PF. This mapping info will be used later on for Rx/Tx pkt steering. Signed-off-by: Linu Cherian

[PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver

From: Sunil Goutham This patch adds basic template for Marvell OcteonTX2's CGX ethernet interface driver. Just the probe. RVU AF driver will use APIs exported by this driver for various things like PF to physical interface mapping, loopback mode, interface stats etc. Signed-off-by: Sunil

[PATCH 12/15] soc: octeontx2: Set RVU PFs to CGX LMACs mapping

From: Linu Cherian Each of the enabled CGX LMAC is considered a physical interface and RVU PFs are mapped to these. VFs of these SRIOV PFs will be virtual interfaces and share CGX LMAC along with PF. This mapping info will be used later on for Rx/Tx pkt steering. Signed-off-by: Linu Cherian

[PATCH 09/15] soc: octeontx2: Configure block LF's MSIX vector offset

From: Sunil Goutham Firmware configures a certain number of MSIX vectors to each of enabled RVU PF/VF. When a block LF is attached to a PF/VF, number of MSIX vectors needed by that LF are set aside (out of PF/VF's total MSIX vectors) and LF's msix_offset is configured in HW. Also added support

[PATCH 08/15] soc: octeontx2: Add RVU block LF provisioning support

From: Sunil Goutham Added support for a RVU PF/VF to request AF via mailbox to attach or detach NPA/NIX/SSO/SSOW/TIM/CPT block LFs. Also supports partial detachment and modifying current LF attached count of a certian block type. Signed-off-by: Sunil Goutham ---

[PATCH 06/15] soc: octeontx2: Convert mbox msg id check to a macro

From: Aleksey Makarov With 10's of mailbox messages expected to be handled in future, checking for message id could become a lengthy switch case. Hence added a macro to auto generate the switch case for each msg id. Signed-off-by: Aleksey Makarov --- drivers/soc/marvell/octeontx2/rvu.c | 44

[PATCH 13/15] soc: octeontx2: Add support for CGX link management

From: Linu Cherian CGX LMAC initialization, link status polling etc is done by low level secure firmware. For link management this patch adds a interface or communication mechanism between firmware and this kernel CGX driver. - Firmware interface specification is defined in cgx_fw_if.h. -

[PATCH 15/15] MAINTAINERS: Add entry for Marvell OcteonTX2 Admin Function driver

From: Sunil Goutham Added maintainers entry for Marvell OcteonTX2 SOC's RVU admin function driver. Signed-off-by: Sunil Goutham --- MAINTAINERS | 10 ++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8bef28b..99ef6c1 100644 --- a/MAINTAINERS +++

[PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

From: Geetha sowjanya HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence create a IOMMU mapping for the physcial address configured by firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. Signed-off-by: Geetha sowjanya Signed-off-by: Sunil Goutham ---

[PATCH 09/15] soc: octeontx2: Configure block LF's MSIX vector offset

From: Sunil Goutham Firmware configures a certain number of MSIX vectors to each of enabled RVU PF/VF. When a block LF is attached to a PF/VF, number of MSIX vectors needed by that LF are set aside (out of PF/VF's total MSIX vectors) and LF's msix_offset is configured in HW. Also added support

[PATCH 08/15] soc: octeontx2: Add RVU block LF provisioning support

From: Sunil Goutham Added support for a RVU PF/VF to request AF via mailbox to attach or detach NPA/NIX/SSO/SSOW/TIM/CPT block LFs. Also supports partial detachment and modifying current LF attached count of a certian block type. Signed-off-by: Sunil Goutham ---

[PATCH 06/15] soc: octeontx2: Convert mbox msg id check to a macro

From: Aleksey Makarov With 10's of mailbox messages expected to be handled in future, checking for message id could become a lengthy switch case. Hence added a macro to auto generate the switch case for each msg id. Signed-off-by: Aleksey Makarov --- drivers/soc/marvell/octeontx2/rvu.c | 44

[PATCH 13/15] soc: octeontx2: Add support for CGX link management

From: Linu Cherian CGX LMAC initialization, link status polling etc is done by low level secure firmware. For link management this patch adds a interface or communication mechanism between firmware and this kernel CGX driver. - Firmware interface specification is defined in cgx_fw_if.h. -

[PATCH 15/15] MAINTAINERS: Add entry for Marvell OcteonTX2 Admin Function driver

From: Sunil Goutham Added maintainers entry for Marvell OcteonTX2 SOC's RVU admin function driver. Signed-off-by: Sunil Goutham --- MAINTAINERS | 10 ++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8bef28b..99ef6c1 100644 --- a/MAINTAINERS +++

[PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA

From: Geetha sowjanya HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence create a IOMMU mapping for the physcial address configured by firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. Signed-off-by: Geetha sowjanya Signed-off-by: Sunil Goutham ---

[PATCH 14/15] soc: octeontx2: Register for CGX lmac events

From: Linu Cherian Added support in RVU AF driver to register for CGX LMAC link status change events from firmware and managing them. Processing part will be added in followup patches. - Introduced eventqueue for posting events from cgx lmac. Queueing mechanism will ensure that events can be

[PATCH 14/15] soc: octeontx2: Register for CGX lmac events

From: Linu Cherian Added support in RVU AF driver to register for CGX LMAC link status change events from firmware and managing them. Processing part will be added in followup patches. - Introduced eventqueue for posting events from cgx lmac. Queueing mechanism will ensure that events can be

[PATCH 04/15] soc: octeontx2: Add mailbox support infra

From: Aleksey Makarov This patch adds mailbox support infrastructure APIs. Each RVU device has a dedicated 64KB mailbox region shared with it's peer for communication. RVU AF has a separate mailbox region shared with each of RVU PFs and a RVU PF has a separate region shared with each of it's VF.

[PATCH 04/15] soc: octeontx2: Add mailbox support infra

From: Aleksey Makarov This patch adds mailbox support infrastructure APIs. Each RVU device has a dedicated 64KB mailbox region shared with it's peer for communication. RVU AF has a separate mailbox region shared with each of RVU PFs and a RVU PF has a separate region shared with each of it's VF.

[PATCH 05/15] soc: octeontx2: Add mailbox IRQ and msg handlers

From: Sunil Goutham This patch adds support for mailbox interrupt and message handling. Mapped mailbox region and registered a workqueue for message handling. Enabled mailbox IRQ of RVU PFs and registered a interrupt handler. When IRQ is triggered work is added to the mbox workqueue for msgs to

[PATCH 03/15] soc: octeontx2: Gather RVU blocks HW info

From: Sunil Goutham This patch gathers NPA/NIX/SSO/SSOW/TIM/CPT RVU blocks's HW info like number of LFs. Important register offsets saved for later use to avoid code duplication for each block. A bitmap is allocated for each of the blocks which later on will be used to allocate a LF for a RVU

[PATCH 01/15] soc: octeontx2: Add Marvell OcteonTX2 RVU AF driver

From: Sunil Goutham This patch adds basic template for Marvell OcteonTX2's resource virtualization unit (RVU) admin function (AF) driver. Just the driver registration and probe. Signed-off-by: Sunil Goutham --- drivers/soc/Kconfig| 1 + drivers/soc/Makefile

[PATCH 07/15] soc: octeontx2: Scan blocks for LFs provisioned to PF/VF

From: Sunil Goutham Scan all RVU blocks to find any 'LF to RVU PF/VF' mapping done by low level firmware. If found any, mark them as used in respective block's LF bitmap and also save mapped PF/VF's PF_FUNC info. This is done to avoid reattaching a block LF to a different RVU PF/VF.

[PATCH 05/15] soc: octeontx2: Add mailbox IRQ and msg handlers

From: Sunil Goutham This patch adds support for mailbox interrupt and message handling. Mapped mailbox region and registered a workqueue for message handling. Enabled mailbox IRQ of RVU PFs and registered a interrupt handler. When IRQ is triggered work is added to the mbox workqueue for msgs to

[PATCH 03/15] soc: octeontx2: Gather RVU blocks HW info

From: Sunil Goutham This patch gathers NPA/NIX/SSO/SSOW/TIM/CPT RVU blocks's HW info like number of LFs. Important register offsets saved for later use to avoid code duplication for each block. A bitmap is allocated for each of the blocks which later on will be used to allocate a LF for a RVU

[PATCH 01/15] soc: octeontx2: Add Marvell OcteonTX2 RVU AF driver

From: Sunil Goutham This patch adds basic template for Marvell OcteonTX2's resource virtualization unit (RVU) admin function (AF) driver. Just the driver registration and probe. Signed-off-by: Sunil Goutham --- drivers/soc/Kconfig| 1 + drivers/soc/Makefile

[PATCH 07/15] soc: octeontx2: Scan blocks for LFs provisioned to PF/VF

From: Sunil Goutham Scan all RVU blocks to find any 'LF to RVU PF/VF' mapping done by low level firmware. If found any, mark them as used in respective block's LF bitmap and also save mapped PF/VF's PF_FUNC info. This is done to avoid reattaching a block LF to a different RVU PF/VF.

[PATCH 02/15] soc: octeontx2: Reset all RVU blocks

From: Sunil Goutham Go through all BLKADDRs and check which ones are implemented on this silicon and do a HW reset of each implemented block. Also added all RVU AF and PF register offsets. Signed-off-by: Sunil Goutham --- drivers/soc/marvell/octeontx2/rvu.c| 78

[PATCH 00/15] soc: octeontx2: Add RVU admin function driver

From: Sunil Goutham Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs). PF0 is called administrative / admin function (AF) and has privilege access to registers to provision different RVU functional

[PATCH 02/15] soc: octeontx2: Reset all RVU blocks

From: Sunil Goutham Go through all BLKADDRs and check which ones are implemented on this silicon and do a HW reset of each implemented block. Also added all RVU AF and PF register offsets. Signed-off-by: Sunil Goutham --- drivers/soc/marvell/octeontx2/rvu.c| 78

[PATCH 00/15] soc: octeontx2: Add RVU admin function driver

From: Sunil Goutham Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs). PF0 is called administrative / admin function (AF) and has privilege access to registers to provision different RVU functional

Re: net: thunder: change q_len's type to handle max ring size

On Fri, Feb 9, 2018 at 3:27 AM, Dean Nelson wrote: > On 02/08/2018 02:34 PM, David Miller wrote: >> >> From: Dean Nelson >> Date: >> >>> The Cavium thunder nicvf driver supports rx/tx rings of up to 65536 >>> entries per. >>> The number of entires are

Re: net: thunder: change q_len's type to handle max ring size

On Fri, Feb 9, 2018 at 3:27 AM, Dean Nelson wrote: > On 02/08/2018 02:34 PM, David Miller wrote: >> >> From: Dean Nelson >> Date: >> >>> The Cavium thunder nicvf driver supports rx/tx rings of up to 65536 >>> entries per. >>> The number of entires are stored in the q_len member of struct >>>

Re: [PATCH net] net: thunderx: Fix TCP/UDP checksum offload for IPv6 pkts

On Wed, Nov 22, 2017 at 9:27 PM, Eric Dumazet wrote: > On Wed, 2017-11-22 at 15:37 +0300, Aleksey Makarov wrote: >> From: Sunil Goutham >> >> This fixes a previous patch which missed some changes >> and due to which L3 checksum offload was getting

Re: [PATCH net] net: thunderx: Fix TCP/UDP checksum offload for IPv6 pkts

On Wed, Nov 22, 2017 at 9:27 PM, Eric Dumazet wrote: > On Wed, 2017-11-22 at 15:37 +0300, Aleksey Makarov wrote: >> From: Sunil Goutham >> >> This fixes a previous patch which missed some changes >> and due to which L3 checksum offload was getting enabled >> for IPv6 pkts. And HW is dropping

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