On Fri, Feb 05, 2021 at 09:44:59AM +, Russell King - ARM Linux admin wrote:
> On Fri, Feb 05, 2021 at 12:40:54AM +, Giancarlo Ferrari wrote:
> > Russell,
> >
> > On Fri, Feb 05, 2021 at 12:18:33AM +, Russell King - ARM Linux admin
> > wrote:
> > > On Thu, Feb 04, 2021 at 11:48:42PM
On Fri, Feb 05, 2021 at 12:40:54AM +, Giancarlo Ferrari wrote:
> Russell,
>
> On Fri, Feb 05, 2021 at 12:18:33AM +, Russell King - ARM Linux admin
> wrote:
> > On Thu, Feb 04, 2021 at 11:48:42PM +, Giancarlo Ferrari wrote:
> > > Can I ask about having it integrated ?
> >
> > Thanks
Sorry for polluting,
On Fri, Feb 05, 2021 at 12:40:54AM +, Giancarlo Ferrari wrote:
> Russell,
>
> On Fri, Feb 05, 2021 at 12:18:33AM +, Russell King - ARM Linux admin
> wrote:
> > On Thu, Feb 04, 2021 at 11:48:42PM +, Giancarlo Ferrari wrote:
> > > Can I ask about having it
Russell,
On Fri, Feb 05, 2021 at 12:18:33AM +, Russell King - ARM Linux admin wrote:
> On Thu, Feb 04, 2021 at 11:48:42PM +, Giancarlo Ferrari wrote:
> > Can I ask about having it integrated ?
>
> Thanks for testing. Are you willing for me to add:
>
> Tested-by: Giancarlo Ferrari
>
>
On Thu, Feb 04, 2021 at 11:48:42PM +, Giancarlo Ferrari wrote:
> Can I ask about having it integrated ?
Thanks for testing. Are you willing for me to add:
Tested-by: Giancarlo Ferrari
to the commit log?
I can move it into the fixes branch which I want to send to Linus by
Saturday at the
Hi all,
On Mon, Feb 01, 2021 at 10:18:26PM +, Giancarlo Ferrari wrote:
> Russell,
>
> On Mon, Feb 01, 2021 at 08:16:33PM +, Russell King - ARM Linux admin
> wrote:
> > On Mon, Feb 01, 2021 at 08:07:37PM +, Giancarlo Ferrari wrote:
> > > Hi,
> >
> > Hi,
> >
> > > Why we should
Russell,
On Mon, Feb 01, 2021 at 08:16:33PM +, Russell King - ARM Linux admin wrote:
> On Mon, Feb 01, 2021 at 08:07:37PM +, Giancarlo Ferrari wrote:
> > Hi,
>
> Hi,
>
> > Why we should align 3 ? For the fncpy I suppose.
>
> Slightly arbitary really - it gives a nice 8-byte alignment
On Mon, Feb 01, 2021 at 08:07:37PM +, Giancarlo Ferrari wrote:
> Hi,
Hi,
> Why we should align 3 ? For the fncpy I suppose.
Slightly arbitary really - it gives a nice 8-byte alignment to the data.
.align 2 would also be sufficient.
> I don't know now how to proceed now, as you (Mark and
Hi,
On Mon, Feb 01, 2021 at 04:08:38PM +, Russell King - ARM Linux admin wrote:
> On Mon, Feb 01, 2021 at 01:57:14PM +, Mark Rutland wrote:
> > We could simplify this slightly if we moved the kexec_& variables into a
> > struct (using asm-offset KEXEC_VAR_* offsets and a KEXEC_VAR_SIZE
Hi,
On Mon, Feb 01, 2021 at 03:30:12PM +, Mark Rutland wrote:
> Hi,
>
> On Mon, Feb 01, 2021 at 02:39:46PM +, Giancarlo Ferrari wrote:
> > On Mon, Feb 01, 2021 at 12:47:20PM +, Mark Rutland wrote:
> > > On Mon, Feb 01, 2021 at 12:44:56AM +, Giancarlo Ferrari wrote:
> > > >
On Mon, Feb 01, 2021 at 04:32:40PM +, Mark Rutland wrote:
> I reckon here we need:
>
> __cpuc_flush_dcache_area(reboot_code_buffer,
>relocate_new_kernel_size + sizeof(*data));
>
> ... to make sure both the instructions and data are visible with the MMU
>
On Mon, Feb 01, 2021 at 04:08:38PM +, Russell King - ARM Linux admin wrote:
> On Mon, Feb 01, 2021 at 01:57:14PM +, Mark Rutland wrote:
> > We could simplify this slightly if we moved the kexec_& variables into a
> > struct (using asm-offset KEXEC_VAR_* offsets and a KEXEC_VAR_SIZE region
On Mon, Feb 01, 2021 at 01:57:14PM +, Mark Rutland wrote:
> We could simplify this slightly if we moved the kexec_& variables into a
> struct (using asm-offset KEXEC_VAR_* offsets and a KEXEC_VAR_SIZE region
> reserved in the asm), then here we could do something like:
>
> static struct
Hi,
On Mon, Feb 01, 2021 at 02:39:46PM +, Giancarlo Ferrari wrote:
> On Mon, Feb 01, 2021 at 12:47:20PM +, Mark Rutland wrote:
> > On Mon, Feb 01, 2021 at 12:44:56AM +, Giancarlo Ferrari wrote:
> > > machine_kexec() need to set rw permission in text and rodata sections
> > > to assign
Hi,
On Mon, Feb 01, 2021 at 12:47:20PM +, Mark Rutland wrote:
> On Mon, Feb 01, 2021 at 12:44:56AM +, Giancarlo Ferrari wrote:
> > machine_kexec() need to set rw permission in text and rodata sections
> > to assign some variables (e.g. kexec_start_address). To do that at
> > the end
On Mon, Feb 01, 2021 at 01:03:45PM +, Russell King - ARM Linux admin wrote:
> On Mon, Feb 01, 2021 at 12:47:20PM +, Mark Rutland wrote:
> > 1. copy reloc code into buffer
> > 2. alter variables in copy of reloc code
> > 3. branch to buffer
> >
> > ... which would avoid this class of
On Mon, Feb 01, 2021 at 12:47:20PM +, Mark Rutland wrote:
> 1. copy reloc code into buffer
> 2. alter variables in copy of reloc code
> 3. branch to buffer
>
> ... which would avoid this class of problem too.
Yep, slightly messy to do though:
diff --git a/arch/arm/kernel/machine_kexec.c
On Mon, Feb 01, 2021 at 12:44:56AM +, Giancarlo Ferrari wrote:
> machine_kexec() need to set rw permission in text and rodata sections
> to assign some variables (e.g. kexec_start_address). To do that at
> the end (after flushing pdm in memory, etc.) it needs to invalidate
> TLB [section]
I wish others who know this code would get involved, and such stuff
wasn't left to me to research and work out whether a patch is correct
or not.
On Mon, Feb 01, 2021 at 12:44:56AM +, Giancarlo Ferrari wrote:
> machine_kexec() need to set rw permission in text and rodata sections
> to assign
Hi all,
On Tue, Jan 12, 2021 at 04:49:06PM +, Giancarlo Ferrari wrote:
> machine_kexec() need to set rw permission in text and rodata sections
> to assign some variables (e.g. kexec_start_address). To do that at
> the end (after flushing pdm in memory, inv D-Cache, etc.) it needs to
>
machine_kexec() need to set rw permission in text and rodata sections
to assign some variables (e.g. kexec_start_address). To do that at
the end (after flushing pdm in memory, etc.) it needs to invalidate
TLB [section] entries.
If during the TLB invalidation an interrupt occours, which might
machine_kexec() need to set rw permission in text and rodata sections
to assign some variables (e.g. kexec_start_address). To do that at
the end (after flushing pdm in memory, inv D-Cache, etc.) it needs to
invalidate TLB [section] entries.
If during the TLB invalidation an interrupt occours,
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