On Wed 08-03-17 18:07:42, Kirill A. Shutemov wrote:
> On Wed, Mar 08, 2017 at 03:25:01PM +0100, Michal Hocko wrote:
> > Btw. my build test machinery has reported this:
> > microblaze/allnoconfig
>
> Thanks.
>
> Fixup is below. I guess it should be folded into 4/7.
yes, this has passed the
On Wed 08-03-17 18:07:42, Kirill A. Shutemov wrote:
> On Wed, Mar 08, 2017 at 03:25:01PM +0100, Michal Hocko wrote:
> > Btw. my build test machinery has reported this:
> > microblaze/allnoconfig
>
> Thanks.
>
> Fixup is below. I guess it should be folded into 4/7.
yes, this has passed the
On Wed, Mar 08, 2017 at 03:25:01PM +0100, Michal Hocko wrote:
> Btw. my build test machinery has reported this:
> microblaze/allnoconfig
Thanks.
Fixup is below. I guess it should be folded into 4/7.
diff --git a/arch/microblaze/include/asm/page.h
b/arch/microblaze/include/asm/page.h
index
On Wed, Mar 08, 2017 at 03:25:01PM +0100, Michal Hocko wrote:
> Btw. my build test machinery has reported this:
> microblaze/allnoconfig
Thanks.
Fixup is below. I guess it should be folded into 4/7.
diff --git a/arch/microblaze/include/asm/page.h
b/arch/microblaze/include/asm/page.h
index
Btw. my build test machinery has reported this:
microblaze/allnoconfig
In file included from ./arch/microblaze/include/asm/pgtable.h:550:0,
from ./include/linux/mm.h:68,
from ./arch/microblaze/include/asm/io.h:17,
from ./include/linux/io.h:25,
Btw. my build test machinery has reported this:
microblaze/allnoconfig
In file included from ./arch/microblaze/include/asm/pgtable.h:550:0,
from ./include/linux/mm.h:68,
from ./arch/microblaze/include/asm/io.h:17,
from ./include/linux/io.h:25,
As per Linus' suggestion, I'm splitting generic part of 5-level paging
enabling into separate patchset.
I believe it's relatively low-risk and can be applied to v4.11.
Merging it now would make x86 5-level paging enabling in v4.12 easier.
The first patch is actually x86-specific: detect 5-level
As per Linus' suggestion, I'm splitting generic part of 5-level paging
enabling into separate patchset.
I believe it's relatively low-risk and can be applied to v4.11.
Merging it now would make x86 5-level paging enabling in v4.12 easier.
The first patch is actually x86-specific: detect 5-level
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