On 2021-02-24 14:06, Mark Rutland wrote:
On Fri, Feb 19, 2021 at 06:10:56PM +, Marc Zyngier wrote:
Hi Mark,
On Fri, 19 Feb 2021 11:38:56 +,
Mark Rutland wrote:
>
> Hector's M1 support series [1] shows that some platforms have critical
> interrupts wired to FIQ, and to support these
On Fri, Feb 19, 2021 at 06:10:56PM +, Marc Zyngier wrote:
> Hi Mark,
>
> On Fri, 19 Feb 2021 11:38:56 +,
> Mark Rutland wrote:
> >
> > Hector's M1 support series [1] shows that some platforms have critical
> > interrupts wired to FIQ, and to support these platforms we need to support
>
Hi Mark,
On Fri, 19 Feb 2021 11:38:56 +,
Mark Rutland wrote:
>
> Hector's M1 support series [1] shows that some platforms have critical
> interrupts wired to FIQ, and to support these platforms we need to support
> handling FIQ exceptions. Other contemporary platforms don't use FIQ (since
On Sat, Feb 20, 2021 at 12:41:01AM +0900, Hector Martin wrote:
> Hi Mark,
>
> Thanks for tackling this side of the problem!
No problem -- I have a vested interest in the arm64 exception management
code lookin the way I expect/prefer! ;)
> On 19/02/2021 20.38, Mark Rutland wrote:
> > I'm hoping
Hi Mark,
Thanks for tackling this side of the problem!
On 19/02/2021 20.38, Mark Rutland wrote:
The only functional difference here is that if an IRQ
is somehow taken prior to set_handle_irq() the default handler will directly
panic() rather than the vector branching to NULL.
That sounds
Hector's M1 support series [1] shows that some platforms have critical
interrupts wired to FIQ, and to support these platforms we need to support
handling FIQ exceptions. Other contemporary platforms don't use FIQ (since e.g.
this is usually routed to EL3), and as we never expect to take an FIQ,
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