Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On Thu, Apr 6, 2017 at 3:19 PM, Laxman Dewangan wrote: > On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote: >> On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: >>> On 05/04/17 15:13, Laxman Dewangan wrote: +state of the system. The configuration

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On Thu, Apr 6, 2017 at 3:19 PM, Laxman Dewangan wrote: > On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote: >> On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: >>> On 05/04/17 15:13, Laxman Dewangan wrote: +state of the system. The configuration of pin is provided via

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On 06/04/17 14:19, Laxman Dewangan wrote: > > On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote: >> * PGP Signed by an unknown key >> >> On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: >>> On 05/04/17 15:13, Laxman Dewangan wrote: +state of the system. The configuration

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On 06/04/17 14:19, Laxman Dewangan wrote: > > On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote: >> * PGP Signed by an unknown key >> >> On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: >>> On 05/04/17 15:13, Laxman Dewangan wrote: +state of the system. The configuration

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: On 05/04/17 15:13, Laxman Dewangan wrote: +state of the system. The configuration of pin is provided via the pinctrl +DT node as detailed in

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: On 05/04/17 15:13, Laxman Dewangan wrote: +state of the system. The configuration of pin is provided via the pinctrl +DT node as detailed in

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: > > On 05/04/17 15:13, Laxman Dewangan wrote: > > In some of NVIDIA Tegra's platform, PWM controller is used to > > control the PWM controlled regulators. PWM signal is connected to > > the VID pin of the regulator where duty cycle of

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: > > On 05/04/17 15:13, Laxman Dewangan wrote: > > In some of NVIDIA Tegra's platform, PWM controller is used to > > control the PWM controlled regulators. PWM signal is connected to > > the VID pin of the regulator where duty cycle of

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On 05/04/17 15:13, Laxman Dewangan wrote: > In some of NVIDIA Tegra's platform, PWM controller is used to > control the PWM controlled regulators. PWM signal is connected to > the VID pin of the regulator where duty cycle of PWM signal decide > the voltage level of the regulator output. > > The

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

On 05/04/17 15:13, Laxman Dewangan wrote: > In some of NVIDIA Tegra's platform, PWM controller is used to > control the PWM controlled regulators. PWM signal is connected to > the VID pin of the regulator where duty cycle of PWM signal decide > the voltage level of the regulator output. > > The

[PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. The tristate (high impedance of PWM pin form Tegra) also

[PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. The tristate (high impedance of PWM pin form Tegra) also